From: Paul Walmsley <paul.walmsley@sifive.com>
To: Yash Shah <yash.shah@sifive.com>
Cc: "sorear2@gmail.com" <sorear2@gmail.com>,
"aou@eecs.berkeley.edu" <aou@eecs.berkeley.edu>,
"alex@ghiti.fr" <alex@ghiti.fr>,
"catalin.marinas@arm.com" <catalin.marinas@arm.com>,
"Palmer Dabbelt \( Sifive\)" <palmer@g.sifive.com>,
"Anup.Patel@wdc.com" <Anup.Patel@wdc.com>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"Paul Walmsley \( Sifive\)" <paul.walmsley@g.sifive.com>,
"rppt@linux.ibm.com" <rppt@linux.ibm.com>,
Sachin Ghadi <sachin.ghadi@sifive.com>,
"logang@deltatee.com" <logang@deltatee.com>,
Greentime Hu <greentime.hu@g.sifive.com>,
"gregkh@linuxfoundation.org" <gregkh@linuxfoundation.org>,
"linux-riscv@lists.infradead.org"
<linux-riscv@lists.infradead.org>,
"will@kernel.org" <will@kernel.org>,
"tglx@linutronix.de" <tglx@linutronix.de>,
"allison@lohutok.net" <allison@lohutok.net>
Subject: Re: [PATCH v2] RISC-V: Add PCIe I/O BAR memory mapping
Date: Fri, 25 Oct 2019 08:53:19 -0700 (PDT) [thread overview]
Message-ID: <alpine.DEB.2.21.9999.1910250852420.28076@viisi.sifive.com> (raw)
In-Reply-To: <1571992163-6811-1-git-send-email-yash.shah@sifive.com>
On Fri, 25 Oct 2019, Yash Shah wrote:
> For legacy I/O BARs (non-MMIO BARs) to work correctly on RISC-V Linux,
> we need to establish a reserved memory region for them, so that drivers
> that wish to use the legacy I/O BARs can issue reads and writes against
> a memory region that is mapped to the host PCIe controller's I/O BAR
> mapping.
>
> Signed-off-by: Yash Shah <yash.shah@sifive.com>
Thanks. And just to confirm: this is a fix, right? Without this patch,
legacy PCIe I/O resources won't be accessible on RISC-V?
- Paul
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next prev parent reply other threads:[~2019-10-25 15:53 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-10-25 8:30 [PATCH v2] RISC-V: Add PCIe I/O BAR memory mapping Yash Shah
2019-10-25 15:53 ` Paul Walmsley [this message]
2019-10-29 4:19 ` Yash Shah
2019-10-29 18:22 ` Paul Walmsley
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