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Thu, 31 Oct 2019 16:57:47 -0700 (PDT) Date: Thu, 31 Oct 2019 16:57:45 -0700 (PDT) From: Paul Walmsley X-X-Sender: paulw@viisi.sifive.com To: Christoph Hellwig Subject: Re: [PATCH 05/12] riscv: implement remote sfence.i using IPIs In-Reply-To: <20191028121043.22934-6-hch@lst.de> Message-ID: References: <20191028121043.22934-1-hch@lst.de> <20191028121043.22934-6-hch@lst.de> User-Agent: Alpine 2.21.9999 (DEB 301 2018-08-15) MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191031_165749_026891_34F12662 X-CRM114-Status: UNSURE ( 9.73 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Anup Patel , Damien Le Moal , Palmer Dabbelt , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+infradead-linux-riscv=archiver.kernel.org@lists.infradead.org On Mon, 28 Oct 2019, Christoph Hellwig wrote: > The RISC-V ISA only supports flushing the instruction cache for the > local CPU core. Currently we always offload the remote TLB flushing to > the SBI, which then issues an IPI under the hoods. But with M-mode > we do not have an SBI so we have to do it ourselves. IPI to the > other nodes using the existing kernel helpers instead if we have > native clint support and thus can IPI directly from the kernel. > > Signed-off-by: Christoph Hellwig > Reviewed-by: Anup Patel Thanks, queued for v5.5-rc1 with a minor fix to one of the code comments. - Paul _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv