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Tue, 05 Nov 2019 10:01:10 -0800 (PST) Date: Tue, 5 Nov 2019 10:01:10 -0800 (PST) From: Paul Walmsley X-X-Sender: paulw@viisi.sifive.com To: daniel.lezcano@linaro.org, tglx@linutronix.de Subject: Re: [PATCH 06/12] riscv: add support for MMIO access to the timer registers In-Reply-To: <20191028121043.22934-7-hch@lst.de> Message-ID: References: <20191028121043.22934-1-hch@lst.de> <20191028121043.22934-7-hch@lst.de> User-Agent: Alpine 2.21.9999 (DEB 301 2018-08-15) MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191105_100112_174005_1A4FB1D1 X-CRM114-Status: GOOD ( 20.84 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Damien Le Moal , Anup Patel , Palmer Dabbelt , linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Christoph Hellwig Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+infradead-linux-riscv=archiver.kernel.org@lists.infradead.org Daniel, Thomas, On Mon, 28 Oct 2019, Christoph Hellwig wrote: > When running in M-mode we can't use the SBI to set the timer, and > don't have access to the time CSR as that usually is emulated by > M-mode. Instead provide code that directly accesses the MMIO for > the timer. > > Signed-off-by: Christoph Hellwig > Reviewed-by: Anup Patel Care to give a quick ack to the drivers/clocksource/timer-riscv.c changes? thanks, - Paul > --- > arch/riscv/include/asm/sbi.h | 3 ++- > arch/riscv/include/asm/timex.h | 19 +++++++++++++++++-- > drivers/clocksource/timer-riscv.c | 21 +++++++++++++++++---- > 3 files changed, 36 insertions(+), 7 deletions(-) > > diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h > index 0cb74eccc73f..a4774bafe033 100644 > --- a/arch/riscv/include/asm/sbi.h > +++ b/arch/riscv/include/asm/sbi.h > @@ -95,7 +95,8 @@ static inline void sbi_remote_sfence_vma_asid(const unsigned long *hart_mask, > SBI_CALL_4(SBI_REMOTE_SFENCE_VMA_ASID, hart_mask, start, size, asid); > } > #else /* CONFIG_RISCV_SBI */ > -/* stub to for code is only reachable under IS_ENABLED(CONFIG_RISCV_SBI): */ > +/* stubs to for code is only reachable under IS_ENABLED(CONFIG_RISCV_SBI): */ > +void sbi_set_timer(uint64_t stime_value); > void sbi_remote_fence_i(const unsigned long *hart_mask); > #endif /* CONFIG_RISCV_SBI */ > #endif /* _ASM_RISCV_SBI_H */ > diff --git a/arch/riscv/include/asm/timex.h b/arch/riscv/include/asm/timex.h > index c7ef131b9e4c..e17837d61667 100644 > --- a/arch/riscv/include/asm/timex.h > +++ b/arch/riscv/include/asm/timex.h > @@ -7,12 +7,25 @@ > #define _ASM_RISCV_TIMEX_H > > #include > +#include > > typedef unsigned long cycles_t; > > +extern u64 __iomem *riscv_time_val; > +extern u64 __iomem *riscv_time_cmp; > + > +#ifdef CONFIG_64BIT > +#define mmio_get_cycles() readq_relaxed(riscv_time_val) > +#else > +#define mmio_get_cycles() readl_relaxed(riscv_time_val) > +#define mmio_get_cycles_hi() readl_relaxed(((u32 *)riscv_time_val) + 1) > +#endif > + > static inline cycles_t get_cycles(void) > { > - return csr_read(CSR_TIME); > + if (IS_ENABLED(CONFIG_RISCV_SBI)) > + return csr_read(CSR_TIME); > + return mmio_get_cycles(); > } > #define get_cycles get_cycles > > @@ -24,7 +37,9 @@ static inline u64 get_cycles64(void) > #else /* CONFIG_64BIT */ > static inline u32 get_cycles_hi(void) > { > - return csr_read(CSR_TIMEH); > + if (IS_ENABLED(CONFIG_RISCV_SBI)) > + return csr_read(CSR_TIMEH); > + return mmio_get_cycles_hi(); > } > > static inline u64 get_cycles64(void) > diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-riscv.c > index d083bfb535f6..f3eb0c04401a 100644 > --- a/drivers/clocksource/timer-riscv.c > +++ b/drivers/clocksource/timer-riscv.c > @@ -3,9 +3,9 @@ > * Copyright (C) 2012 Regents of the University of California > * Copyright (C) 2017 SiFive > * > - * All RISC-V systems have a timer attached to every hart. These timers can be > - * read from the "time" and "timeh" CSRs, and can use the SBI to setup > - * events. > + * All RISC-V systems have a timer attached to every hart. These timers can > + * either be read from the "time" and "timeh" CSRs, and can use the SBI to > + * setup events, or directly accessed using MMIO registers. > */ > #include > #include > @@ -13,14 +13,27 @@ > #include > #include > #include > +#include > #include > #include > > +u64 __iomem *riscv_time_cmp; > +u64 __iomem *riscv_time_val; > + > +static inline void mmio_set_timer(u64 val) > +{ > + writeq_relaxed(val, > + riscv_time_cmp + cpuid_to_hartid_map(smp_processor_id())); > +} > + > static int riscv_clock_next_event(unsigned long delta, > struct clock_event_device *ce) > { > csr_set(CSR_IE, IE_TIE); > - sbi_set_timer(get_cycles64() + delta); > + if (IS_ENABLED(CONFIG_RISCV_SBI)) > + sbi_set_timer(get_cycles64() + delta); > + else > + mmio_set_timer(get_cycles64() + delta); > return 0; > } > > -- > 2.20.1 > > - Paul _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv