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[98.172.187.222]) by smtp.gmail.com with ESMTPSA id j129sm1579463oib.22.2019.11.13.23.45.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 13 Nov 2019 23:45:10 -0800 (PST) Date: Wed, 13 Nov 2019 23:45:10 -0800 (PST) From: Paul Walmsley X-X-Sender: paulw@viisi.sifive.com To: Christoph Hellwig Subject: Re: [PATCH 09/12] riscv: clear the instruction cache and all registers when booting In-Reply-To: <20191028121043.22934-10-hch@lst.de> Message-ID: References: <20191028121043.22934-1-hch@lst.de> <20191028121043.22934-10-hch@lst.de> User-Agent: Alpine 2.21.9999 (DEB 301 2018-08-15) MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191113_234512_308916_F1B065B1 X-CRM114-Status: UNSURE ( 7.87 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Anup Patel , Damien Le Moal , Palmer Dabbelt , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+infradead-linux-riscv=archiver.kernel.org@lists.infradead.org On Mon, 28 Oct 2019, Christoph Hellwig wrote: > When we get booted we want a clear slate without any leaks from previous > supervisors or the firmware. Flush the instruction cache and then clear > all registers to known good values. This is really important for the > upcoming nommu support that runs on M-mode, but can't really harm when > running in S-mode either. Vaguely based on the concepts from opensbi. > > Signed-off-by: Christoph Hellwig > Reviewed-by: Anup Patel Thanks, queued for v5.5-rc1. - Paul _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv