From: Paul Walmsley <paul.walmsley@sifive.com>
To: Yash Shah <yash.shah@sifive.com>
Cc: mark.rutland@arm.com, devicetree@vger.kernel.org,
aou@eecs.berkeley.edu, sachin.ghadi@sifive.com,
gregkh@linuxfoundation.org, linux-kernel@vger.kernel.org,
green.wan@sifive.com, alexios.zavras@intel.com,
robh+dt@kernel.org, palmer@dabbelt.com, bp@suse.de,
tglx@linutronix.de, bmeng.cn@gmail.com,
linux-riscv@lists.infradead.org, allison@lohutok.net
Subject: Re: [PATCH v2 1/2] riscv: dts: Add DT support for SiFive L2 cache controller
Date: Fri, 3 Jan 2020 16:57:21 -0800 (PST) [thread overview]
Message-ID: <alpine.DEB.2.21.9999.2001031657090.283180@viisi.sifive.com> (raw)
In-Reply-To: <1578024801-39039-2-git-send-email-yash.shah@sifive.com>
On Fri, 3 Jan 2020, Yash Shah wrote:
> Add the L2 cache controller DT node in SiFive FU540 soc-specific DT file
>
> Signed-off-by: Yash Shah <yash.shah@sifive.com>
> Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
Thanks, queued for v5.5-rc.
- Paul
next prev parent reply other threads:[~2020-01-04 0:57 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-01-03 4:13 [PATCH v2 0/2] L2 ccache DT and cacheinfo support to read no. of L2 cache ways enabled Yash Shah
2020-01-03 4:13 ` [PATCH v2 1/2] riscv: dts: Add DT support for SiFive L2 cache controller Yash Shah
2020-01-04 0:57 ` Paul Walmsley [this message]
2020-01-03 4:13 ` [PATCH v2 2/2] riscv: cacheinfo: Add support to determine no. of L2 cache way enabled Yash Shah
2020-01-06 9:10 ` Anup Patel
2020-01-07 3:55 ` Yash Shah
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