* [PATCH] riscv: move sifive_l2_cache.h to include/soc
@ 2020-01-08 6:09 Yash Shah
2020-01-08 8:17 ` Anup Patel
2020-01-11 1:04 ` Paul Walmsley
0 siblings, 2 replies; 5+ messages in thread
From: Yash Shah @ 2020-01-08 6:09 UTC (permalink / raw)
To: paul.walmsley, palmer
Cc: aou, tony.luck, linux-kernel, Yash Shah, rrichter, james.morse,
bp, linux-riscv, mchehab, linux-edac
The commit 9209fb51896f ("riscv: move sifive_l2_cache.c to drivers/soc")
moves the sifive L2 cache driver to driver/soc. It did not move the
header file along with the driver. Therefore this patch moves the header
file to driver/soc
Signed-off-by: Yash Shah <yash.shah@sifive.com>
---
arch/riscv/include/asm/sifive_l2_cache.h | 16 ----------------
drivers/edac/sifive_edac.c | 2 +-
drivers/soc/sifive/sifive_l2_cache.c | 2 +-
include/soc/sifive/sifive_l2_cache.h | 16 ++++++++++++++++
4 files changed, 18 insertions(+), 18 deletions(-)
delete mode 100644 arch/riscv/include/asm/sifive_l2_cache.h
create mode 100644 include/soc/sifive/sifive_l2_cache.h
diff --git a/arch/riscv/include/asm/sifive_l2_cache.h b/arch/riscv/include/asm/sifive_l2_cache.h
deleted file mode 100644
index 04f6748..0000000
--- a/arch/riscv/include/asm/sifive_l2_cache.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * SiFive L2 Cache Controller header file
- *
- */
-
-#ifndef _ASM_RISCV_SIFIVE_L2_CACHE_H
-#define _ASM_RISCV_SIFIVE_L2_CACHE_H
-
-extern int register_sifive_l2_error_notifier(struct notifier_block *nb);
-extern int unregister_sifive_l2_error_notifier(struct notifier_block *nb);
-
-#define SIFIVE_L2_ERR_TYPE_CE 0
-#define SIFIVE_L2_ERR_TYPE_UE 1
-
-#endif /* _ASM_RISCV_SIFIVE_L2_CACHE_H */
diff --git a/drivers/edac/sifive_edac.c b/drivers/edac/sifive_edac.c
index 413cdb4..c0cc72a 100644
--- a/drivers/edac/sifive_edac.c
+++ b/drivers/edac/sifive_edac.c
@@ -10,7 +10,7 @@
#include <linux/edac.h>
#include <linux/platform_device.h>
#include "edac_module.h"
-#include <asm/sifive_l2_cache.h>
+#include <soc/sifive/sifive_l2_cache.h>
#define DRVNAME "sifive_edac"
diff --git a/drivers/soc/sifive/sifive_l2_cache.c b/drivers/soc/sifive/sifive_l2_cache.c
index a9ffff3..a506939 100644
--- a/drivers/soc/sifive/sifive_l2_cache.c
+++ b/drivers/soc/sifive/sifive_l2_cache.c
@@ -9,7 +9,7 @@
#include <linux/interrupt.h>
#include <linux/of_irq.h>
#include <linux/of_address.h>
-#include <asm/sifive_l2_cache.h>
+#include <soc/sifive/sifive_l2_cache.h>
#define SIFIVE_L2_DIRECCFIX_LOW 0x100
#define SIFIVE_L2_DIRECCFIX_HIGH 0x104
diff --git a/include/soc/sifive/sifive_l2_cache.h b/include/soc/sifive/sifive_l2_cache.h
new file mode 100644
index 0000000..04f6748
--- /dev/null
+++ b/include/soc/sifive/sifive_l2_cache.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * SiFive L2 Cache Controller header file
+ *
+ */
+
+#ifndef _ASM_RISCV_SIFIVE_L2_CACHE_H
+#define _ASM_RISCV_SIFIVE_L2_CACHE_H
+
+extern int register_sifive_l2_error_notifier(struct notifier_block *nb);
+extern int unregister_sifive_l2_error_notifier(struct notifier_block *nb);
+
+#define SIFIVE_L2_ERR_TYPE_CE 0
+#define SIFIVE_L2_ERR_TYPE_UE 1
+
+#endif /* _ASM_RISCV_SIFIVE_L2_CACHE_H */
--
2.7.4
^ permalink raw reply related [flat|nested] 5+ messages in thread* Re: [PATCH] riscv: move sifive_l2_cache.h to include/soc
2020-01-08 6:09 [PATCH] riscv: move sifive_l2_cache.h to include/soc Yash Shah
@ 2020-01-08 8:17 ` Anup Patel
2020-01-11 1:04 ` Paul Walmsley
1 sibling, 0 replies; 5+ messages in thread
From: Anup Patel @ 2020-01-08 8:17 UTC (permalink / raw)
To: Yash Shah
Cc: Albert Ou, James Morse, linux-kernel@vger.kernel.org List,
rrichter, tony.luck, Borislav Petkov, Paul Walmsley,
Palmer Dabbelt, linux-riscv, mchehab, linux-edac
On Wed, Jan 8, 2020 at 11:39 AM Yash Shah <yash.shah@sifive.com> wrote:
>
> The commit 9209fb51896f ("riscv: move sifive_l2_cache.c to drivers/soc")
> moves the sifive L2 cache driver to driver/soc. It did not move the
> header file along with the driver. Therefore this patch moves the header
> file to driver/soc
>
> Signed-off-by: Yash Shah <yash.shah@sifive.com>
> ---
> arch/riscv/include/asm/sifive_l2_cache.h | 16 ----------------
> drivers/edac/sifive_edac.c | 2 +-
> drivers/soc/sifive/sifive_l2_cache.c | 2 +-
> include/soc/sifive/sifive_l2_cache.h | 16 ++++++++++++++++
> 4 files changed, 18 insertions(+), 18 deletions(-)
> delete mode 100644 arch/riscv/include/asm/sifive_l2_cache.h
> create mode 100644 include/soc/sifive/sifive_l2_cache.h
>
> diff --git a/arch/riscv/include/asm/sifive_l2_cache.h b/arch/riscv/include/asm/sifive_l2_cache.h
> deleted file mode 100644
> index 04f6748..0000000
> --- a/arch/riscv/include/asm/sifive_l2_cache.h
> +++ /dev/null
> @@ -1,16 +0,0 @@
> -/* SPDX-License-Identifier: GPL-2.0 */
> -/*
> - * SiFive L2 Cache Controller header file
> - *
> - */
> -
> -#ifndef _ASM_RISCV_SIFIVE_L2_CACHE_H
> -#define _ASM_RISCV_SIFIVE_L2_CACHE_H
> -
> -extern int register_sifive_l2_error_notifier(struct notifier_block *nb);
> -extern int unregister_sifive_l2_error_notifier(struct notifier_block *nb);
> -
> -#define SIFIVE_L2_ERR_TYPE_CE 0
> -#define SIFIVE_L2_ERR_TYPE_UE 1
> -
> -#endif /* _ASM_RISCV_SIFIVE_L2_CACHE_H */
> diff --git a/drivers/edac/sifive_edac.c b/drivers/edac/sifive_edac.c
> index 413cdb4..c0cc72a 100644
> --- a/drivers/edac/sifive_edac.c
> +++ b/drivers/edac/sifive_edac.c
> @@ -10,7 +10,7 @@
> #include <linux/edac.h>
> #include <linux/platform_device.h>
> #include "edac_module.h"
> -#include <asm/sifive_l2_cache.h>
> +#include <soc/sifive/sifive_l2_cache.h>
>
> #define DRVNAME "sifive_edac"
>
> diff --git a/drivers/soc/sifive/sifive_l2_cache.c b/drivers/soc/sifive/sifive_l2_cache.c
> index a9ffff3..a506939 100644
> --- a/drivers/soc/sifive/sifive_l2_cache.c
> +++ b/drivers/soc/sifive/sifive_l2_cache.c
> @@ -9,7 +9,7 @@
> #include <linux/interrupt.h>
> #include <linux/of_irq.h>
> #include <linux/of_address.h>
> -#include <asm/sifive_l2_cache.h>
> +#include <soc/sifive/sifive_l2_cache.h>
>
> #define SIFIVE_L2_DIRECCFIX_LOW 0x100
> #define SIFIVE_L2_DIRECCFIX_HIGH 0x104
> diff --git a/include/soc/sifive/sifive_l2_cache.h b/include/soc/sifive/sifive_l2_cache.h
> new file mode 100644
> index 0000000..04f6748
> --- /dev/null
> +++ b/include/soc/sifive/sifive_l2_cache.h
> @@ -0,0 +1,16 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * SiFive L2 Cache Controller header file
> + *
> + */
> +
> +#ifndef _ASM_RISCV_SIFIVE_L2_CACHE_H
> +#define _ASM_RISCV_SIFIVE_L2_CACHE_H
> +
> +extern int register_sifive_l2_error_notifier(struct notifier_block *nb);
> +extern int unregister_sifive_l2_error_notifier(struct notifier_block *nb);
> +
> +#define SIFIVE_L2_ERR_TYPE_CE 0
> +#define SIFIVE_L2_ERR_TYPE_UE 1
> +
> +#endif /* _ASM_RISCV_SIFIVE_L2_CACHE_H */
> --
> 2.7.4
>
LGTM.
Reviewed-by: Anup Patel <anup@brainfault.org>
Regards,
Anup
^ permalink raw reply [flat|nested] 5+ messages in thread* Re: [PATCH] riscv: move sifive_l2_cache.h to include/soc
2020-01-08 6:09 [PATCH] riscv: move sifive_l2_cache.h to include/soc Yash Shah
2020-01-08 8:17 ` Anup Patel
@ 2020-01-11 1:04 ` Paul Walmsley
2020-01-11 1:47 ` Paul Walmsley
1 sibling, 1 reply; 5+ messages in thread
From: Paul Walmsley @ 2020-01-11 1:04 UTC (permalink / raw)
To: Yash Shah
Cc: aou, james.morse, linux-kernel, rrichter, tony.luck, bp, palmer,
linux-riscv, mchehab, linux-edac
On Tue, 7 Jan 2020, Yash Shah wrote:
> The commit 9209fb51896f ("riscv: move sifive_l2_cache.c to drivers/soc")
> moves the sifive L2 cache driver to driver/soc. It did not move the
> header file along with the driver. Therefore this patch moves the header
> file to driver/soc
>
> Signed-off-by: Yash Shah <yash.shah@sifive.com>
Thanks, queued for v5.5-rc.
- Paul
^ permalink raw reply [flat|nested] 5+ messages in thread* Re: [PATCH] riscv: move sifive_l2_cache.h to include/soc
2020-01-11 1:04 ` Paul Walmsley
@ 2020-01-11 1:47 ` Paul Walmsley
2020-01-11 3:57 ` Yash Shah
0 siblings, 1 reply; 5+ messages in thread
From: Paul Walmsley @ 2020-01-11 1:47 UTC (permalink / raw)
To: Yash Shah
Cc: aou, james.morse, linux-kernel, rrichter, tony.luck, bp, palmer,
linux-riscv, mchehab, linux-edac
On Fri, 10 Jan 2020, Paul Walmsley wrote:
> On Tue, 7 Jan 2020, Yash Shah wrote:
>
> > The commit 9209fb51896f ("riscv: move sifive_l2_cache.c to drivers/soc")
> > moves the sifive L2 cache driver to driver/soc. It did not move the
> > header file along with the driver. Therefore this patch moves the header
> > file to driver/soc
> >
> > Signed-off-by: Yash Shah <yash.shah@sifive.com>
>
> Thanks, queued for v5.5-rc.
By the way, I fixed the include guard also. The queued patch follows.
- Paul
From: Yash Shah <yash.shah@sifive.com>
Date: Tue, 7 Jan 2020 22:09:06 -0800
Subject: [PATCH] riscv: move sifive_l2_cache.h to include/soc
The commit 9209fb51896f ("riscv: move sifive_l2_cache.c to drivers/soc")
moves the sifive L2 cache driver to driver/soc. It did not move the
header file along with the driver. Therefore this patch moves the header
file to driver/soc
Signed-off-by: Yash Shah <yash.shah@sifive.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
[paul.walmsley@sifive.com: updated to fix the include guard]
Fixes: 9209fb51896f ("riscv: move sifive_l2_cache.c to drivers/soc")
Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
---
drivers/edac/sifive_edac.c | 2 +-
drivers/soc/sifive/sifive_l2_cache.c | 2 +-
.../include/asm => include/soc/sifive}/sifive_l2_cache.h | 6 +++---
3 files changed, 5 insertions(+), 5 deletions(-)
rename {arch/riscv/include/asm => include/soc/sifive}/sifive_l2_cache.h (72%)
diff --git a/drivers/edac/sifive_edac.c b/drivers/edac/sifive_edac.c
index 413cdb4a591d..c0cc72a3b2be 100644
--- a/drivers/edac/sifive_edac.c
+++ b/drivers/edac/sifive_edac.c
@@ -10,7 +10,7 @@
#include <linux/edac.h>
#include <linux/platform_device.h>
#include "edac_module.h"
-#include <asm/sifive_l2_cache.h>
+#include <soc/sifive/sifive_l2_cache.h>
#define DRVNAME "sifive_edac"
diff --git a/drivers/soc/sifive/sifive_l2_cache.c b/drivers/soc/sifive/sifive_l2_cache.c
index a9ffff3277c7..a5069394cd61 100644
--- a/drivers/soc/sifive/sifive_l2_cache.c
+++ b/drivers/soc/sifive/sifive_l2_cache.c
@@ -9,7 +9,7 @@
#include <linux/interrupt.h>
#include <linux/of_irq.h>
#include <linux/of_address.h>
-#include <asm/sifive_l2_cache.h>
+#include <soc/sifive/sifive_l2_cache.h>
#define SIFIVE_L2_DIRECCFIX_LOW 0x100
#define SIFIVE_L2_DIRECCFIX_HIGH 0x104
diff --git a/arch/riscv/include/asm/sifive_l2_cache.h b/include/soc/sifive/sifive_l2_cache.h
similarity index 72%
rename from arch/riscv/include/asm/sifive_l2_cache.h
rename to include/soc/sifive/sifive_l2_cache.h
index 04f6748fc50b..92ade10ed67e 100644
--- a/arch/riscv/include/asm/sifive_l2_cache.h
+++ b/include/soc/sifive/sifive_l2_cache.h
@@ -4,8 +4,8 @@
*
*/
-#ifndef _ASM_RISCV_SIFIVE_L2_CACHE_H
-#define _ASM_RISCV_SIFIVE_L2_CACHE_H
+#ifndef __SOC_SIFIVE_L2_CACHE_H
+#define __SOC_SIFIVE_L2_CACHE_H
extern int register_sifive_l2_error_notifier(struct notifier_block *nb);
extern int unregister_sifive_l2_error_notifier(struct notifier_block *nb);
@@ -13,4 +13,4 @@ extern int unregister_sifive_l2_error_notifier(struct notifier_block *nb);
#define SIFIVE_L2_ERR_TYPE_CE 0
#define SIFIVE_L2_ERR_TYPE_UE 1
-#endif /* _ASM_RISCV_SIFIVE_L2_CACHE_H */
+#endif /* __SOC_SIFIVE_L2_CACHE_H */
--
2.25.0.rc2
^ permalink raw reply related [flat|nested] 5+ messages in thread* RE: [PATCH] riscv: move sifive_l2_cache.h to include/soc
2020-01-11 1:47 ` Paul Walmsley
@ 2020-01-11 3:57 ` Yash Shah
0 siblings, 0 replies; 5+ messages in thread
From: Yash Shah @ 2020-01-11 3:57 UTC (permalink / raw)
To: Paul Walmsley ( Sifive)
Cc: aou, james.morse, linux-kernel, rrichter, tony.luck, bp, palmer,
linux-riscv, mchehab, linux-edac
> -----Original Message-----
> From: Paul Walmsley <paul.walmsley@sifive.com>
> Sent: 11 January 2020 07:17
> To: Yash Shah <yash.shah@sifive.com>
> Cc: palmer@dabbelt.com; aou@eecs.berkeley.edu; bp@alien8.de;
> mchehab@kernel.org; tony.luck@intel.com; james.morse@arm.com;
> rrichter@marvell.com; linux-riscv@lists.infradead.org; linux-
> kernel@vger.kernel.org; linux-edac@vger.kernel.org
> Subject: Re: [PATCH] riscv: move sifive_l2_cache.h to include/soc
>
> On Fri, 10 Jan 2020, Paul Walmsley wrote:
>
> > On Tue, 7 Jan 2020, Yash Shah wrote:
> >
> > > The commit 9209fb51896f ("riscv: move sifive_l2_cache.c to
> > > drivers/soc") moves the sifive L2 cache driver to driver/soc. It did
> > > not move the header file along with the driver. Therefore this patch
> > > moves the header file to driver/soc
> > >
> > > Signed-off-by: Yash Shah <yash.shah@sifive.com>
> >
> > Thanks, queued for v5.5-rc.
>
> By the way, I fixed the include guard also. The queued patch follows.
Thanks, somehow I had overseen that.
- Yash
>
>
> - Paul
>
> From: Yash Shah <yash.shah@sifive.com>
> Date: Tue, 7 Jan 2020 22:09:06 -0800
> Subject: [PATCH] riscv: move sifive_l2_cache.h to include/soc
>
> The commit 9209fb51896f ("riscv: move sifive_l2_cache.c to drivers/soc")
> moves the sifive L2 cache driver to driver/soc. It did not move the header file
> along with the driver. Therefore this patch moves the header file to
> driver/soc
>
> Signed-off-by: Yash Shah <yash.shah@sifive.com>
> Reviewed-by: Anup Patel <anup@brainfault.org>
> [paul.walmsley@sifive.com: updated to fix the include guard]
> Fixes: 9209fb51896f ("riscv: move sifive_l2_cache.c to drivers/soc")
> Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
> ---
> drivers/edac/sifive_edac.c | 2 +-
> drivers/soc/sifive/sifive_l2_cache.c | 2 +-
> .../include/asm => include/soc/sifive}/sifive_l2_cache.h | 6 +++---
> 3 files changed, 5 insertions(+), 5 deletions(-) rename
> {arch/riscv/include/asm => include/soc/sifive}/sifive_l2_cache.h (72%)
>
> diff --git a/drivers/edac/sifive_edac.c b/drivers/edac/sifive_edac.c index
> 413cdb4a591d..c0cc72a3b2be 100644
> --- a/drivers/edac/sifive_edac.c
> +++ b/drivers/edac/sifive_edac.c
> @@ -10,7 +10,7 @@
> #include <linux/edac.h>
> #include <linux/platform_device.h>
> #include "edac_module.h"
> -#include <asm/sifive_l2_cache.h>
> +#include <soc/sifive/sifive_l2_cache.h>
>
> #define DRVNAME "sifive_edac"
>
> diff --git a/drivers/soc/sifive/sifive_l2_cache.c
> b/drivers/soc/sifive/sifive_l2_cache.c
> index a9ffff3277c7..a5069394cd61 100644
> --- a/drivers/soc/sifive/sifive_l2_cache.c
> +++ b/drivers/soc/sifive/sifive_l2_cache.c
> @@ -9,7 +9,7 @@
> #include <linux/interrupt.h>
> #include <linux/of_irq.h>
> #include <linux/of_address.h>
> -#include <asm/sifive_l2_cache.h>
> +#include <soc/sifive/sifive_l2_cache.h>
>
> #define SIFIVE_L2_DIRECCFIX_LOW 0x100
> #define SIFIVE_L2_DIRECCFIX_HIGH 0x104
> diff --git a/arch/riscv/include/asm/sifive_l2_cache.h
> b/include/soc/sifive/sifive_l2_cache.h
> similarity index 72%
> rename from arch/riscv/include/asm/sifive_l2_cache.h
> rename to include/soc/sifive/sifive_l2_cache.h
> index 04f6748fc50b..92ade10ed67e 100644
> --- a/arch/riscv/include/asm/sifive_l2_cache.h
> +++ b/include/soc/sifive/sifive_l2_cache.h
> @@ -4,8 +4,8 @@
> *
> */
>
> -#ifndef _ASM_RISCV_SIFIVE_L2_CACHE_H
> -#define _ASM_RISCV_SIFIVE_L2_CACHE_H
> +#ifndef __SOC_SIFIVE_L2_CACHE_H
> +#define __SOC_SIFIVE_L2_CACHE_H
>
> extern int register_sifive_l2_error_notifier(struct notifier_block *nb); extern
> int unregister_sifive_l2_error_notifier(struct notifier_block *nb); @@ -13,4
> +13,4 @@ extern int unregister_sifive_l2_error_notifier(struct notifier_block
> *nb); #define SIFIVE_L2_ERR_TYPE_CE 0 #define SIFIVE_L2_ERR_TYPE_UE 1
>
> -#endif /* _ASM_RISCV_SIFIVE_L2_CACHE_H */
> +#endif /* __SOC_SIFIVE_L2_CACHE_H */
> --
> 2.25.0.rc2
>
>
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2020-01-11 3:57 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
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2020-01-08 6:09 [PATCH] riscv: move sifive_l2_cache.h to include/soc Yash Shah
2020-01-08 8:17 ` Anup Patel
2020-01-11 1:04 ` Paul Walmsley
2020-01-11 1:47 ` Paul Walmsley
2020-01-11 3:57 ` Yash Shah
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