[GIT PULL] RISC-V updates for v5.5-rc6

[Paul Walmsley <paul.walmsley@sifive.com>]

Linus,

The following changes since commit c79f46a282390e0f5b306007bf7b11a46d529538:

  Linux 5.5-rc5 (2020-01-05 14:23:27 -0800)

are available in the Git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux.git tags/riscv/for-v5.5-rc6

for you to fetch changes up to dc6fcba72f0435b7884f2e92fd634bb9f78a2c60:

  riscv: Fixup obvious bug for fp-regs reset (2020-01-12 10:12:44 -0800)

----------------------------------------------------------------
RISC-V updates for v5.5-rc6

Two fixes for RISC-V:

- Clear FP registers during boot when FP support is present, rather than
  when they aren't present

- Move the header files associated with the SiFive L2 cache controller
  to drivers/soc (where the code was recently moved)

----------------------------------------------------------------
Guo Ren (1):
      riscv: Fixup obvious bug for fp-regs reset

Yash Shah (1):
      riscv: move sifive_l2_cache.h to include/soc

 arch/riscv/kernel/head.S                                         | 2 +-
 drivers/edac/sifive_edac.c                                       | 2 +-
 drivers/soc/sifive/sifive_l2_cache.c                             | 2 +-
 {arch/riscv/include/asm => include/soc/sifive}/sifive_l2_cache.h | 6 +++---
 4 files changed, 6 insertions(+), 6 deletions(-)
 rename {arch/riscv/include/asm => include/soc/sifive}/sifive_l2_cache.h (72%)

Kernel object size difference:
   text	   data	    bss	    dec	    hex	filename
6896663	2329920	 313920	9540503	 919397	vmlinux.rv64.orig
6896663	2329920	 313920	9540503	 919397	vmlinux.rv64.patched
6656922	1939060	 257576	8853558	 871836	vmlinux.rv32.orig
6656922	1939060	 257576	8853558	 871836	vmlinux.rv32.patched
1171746	 353372	 130024	1655142	 194166	vmlinux.nommu_virt.orig
1171746	 353372	 130024	1655142	 194166	vmlinux.nommu_virt.patched