From mboxrd@z Thu Jan  1 00:00:00 1970
From: mick@ics.forth.gr (Nick Kossifidis)
Date: Fri, 09 Nov 2018 04:36:19 +0200
Subject: [RFC 0/2] Add RISC-V cpu topology
In-Reply-To: <20181108164827.GB10953@e107155-lin>
References: <1541113468-22097-1-git-send-email-atish.patra@wdc.com>
 <866dedbc78ab4fa0e3b040697e112106@mailhost.ics.forth.gr>
 <20181106141331.GA28458@e107155-lin>
 <969fc2a5198984e0dfe8c3f585dc65f9@mailhost.ics.forth.gr>
 <20181106162051.w7fyweuxrl7ujzuz@lakrids.cambridge.arm.com>
 <abcae019e6ae749b17ecb0c721fd3177@mailhost.ics.forth.gr>
 <20181107122803.GA8433@e107155-lin>
 <d04779705c47b59b94300365e805dbd3@mailhost.ics.forth.gr>
 <20181108164827.GB10953@e107155-lin>
Message-ID: <b44d94e4a5575e2ce49344b50956bf8e@mailhost.ics.forth.gr>
To: linux-riscv@lists.infradead.org
List-Id: linux-riscv.lists.infradead.org

???? 2018-11-08 18:48, Sudeep Holla ??????:
> On Thu, Nov 08, 2018 at 04:52:30PM +0200, Nick Kossifidis wrote:
>> ???? 2018-11-07 14:28, Sudeep Holla ??????:
>> >
>> > I agree, but we have kernel code using it(arm64/kernel/topology.c). It's
>> > too late to remove it. But we can always keep to optional if we move the
>> > ARM64 binding as generic to start with and mandate it for only ARM64.
>> >
>> 
>> That's my point as well, if we are going to define something to be 
>> used
>> by everybody and in this case, at least for RISC-V, there is no need 
>> to
>> carry this from the ARM64 binding.
> 
> Sure, whatever you don't need in RISC-V you can see if they can be made
> optional. I don't think that should be a problem.
> 
>> It shouldn't be that hard to fix this
>> in the future for ARM64 as well, we may give the new mapping another 
>> name,
>> maybe cpu-map2 or cpu-topology to slowly move to the new one.
> 
> No, we have it and we will continue to support it. It's not broken to
> fix on ARM64. Why do you think that it's broken on ARM64 ?
> 

I never said it's broken, I just assumed that if this binding becomes 
common
across archs you'd probably like to switch to it, so it should either be
backwards compatible with what you have (or as you said "keep them 
optional")
or take steps for the transition. I'm ok either way, It's not such a 
serious
thing to have the <thread> nodes supported or keep the distinction 
between
"cores", "clusters" or whatever, I'm sorry if it looked that way. I'm 
just
saying that I'd like to have something cleaner for RISC-V and/or a 
binding
that's common for all, we can support both and be backwards compatible, 
or we
can keep it as is and mandate the <thread> nodes only for ARM64 as you
suggested.

>> Changing the
>> dts files shouldn't be this hard, we can provide a script for it. We 
>> can
>> even contain some compatibility code that also understands <thread> 
>> nodes
>> and e.g. merges them together on a core node.
>> 
> 
> Sure, hang on this idea of scripting, we can make a better use of it.
> Details later further in the mail.
> 
> [...]
> 
>> > > The same also happens with the generic numa binding on
>> > > Documentation/devicetree/bindings/numa.txt
>> > > which says we should add the nuna-node-id on each of the cpu nodes.
>> > >
>> >
>> > Yes, but again what's the problem ?
>> >
>> 
>> There is no problem with the above bindings, the problem is that we 
>> have
>> to put them on each cpu node which is messy. We could instead put them
>> (optionally) on the various groupings used on cpu-map. This would 
>> allow
>> cpu-map to be more specific of what is shared across the members of 
>> each
>> group (core/cluster/whatever).
>> 
> 
> I think Mark has already explain why/how generic bindings are useful.
> If you still have concerns, take it up separately and see how you can
> build *perfect* bindings for RISC-V to avoid any legacy baggage.
> 
> We have reasons why we can't assume information about cache or power
> domain topology from CPU topology. I have summarised them already and
> we are not discussing.

But that's what you do on arch/arm/kernel/topology.c, you assume
information on power domain and cache topology based on the CPU topology
when you define the scheduling domain topology levels.

PowerPC also does the same on arch/powerpc/kernel/smp.c and basically if
you track the usage of struct sched_domain_topology_level you'll see 
that
every arch that uses it to instruct the scheduler about the scheduling
domains, does it based on its CPU topology, which I think we both agree
is wrong.

> There may not be perfect bindings but there are
> already supported and nothing is broken here to fix. DT bindings are
> *not* same as code to fix it with a patch to the bindings themselves.
> Once agreed and merged, they need to be treated like user ABI.
> 

The only use of the devicetree spec bindings for caches if I'm not
mistaken are used on your cacheinfo driver for exporting them to 
userspace
through sysfs (thank you for cleaning this up btw). Even if we have the
cache topology  using the generic bindings, we are not doing anything 
with
that information but export it to userspace.

As for the power domain bindings, we have drivers/base/power/domain.c 
that
handles the generic bindings and it's being used by some drivers to put
devices to power domains (something used by the pm code), but from a 
quick
search it's not used for cpu nodes and I didn't see this info being used
for providing hints to the scheduler either. Even with the generic power
domain bindings in place, for CPU idle states, on ARM we have another
binding that's basically the same with the addition of 
"wakeup-latency-us".

For having different capacity there is no generic binding but I guess we
could use ARM's.

Of the generic bindings that relate to the scheduler's behavior, only 
the
numa binding is used as expected and only by ARM64, powerpc and sparc 
use
their own stuff.

So there may be nothing broken regarding the generic / already existing
bindings, but their support needs fixing. The way they are now we can't
use them on RISC-V for configuring the scheduler and supporting SMT and
MC properly + I'm not in favor of using CPU topology blindly as the
other archs do.

>> As I wrote on my answer to Mark previously, the bindings for infering
>> the cache topology, numa topology, power domain topology etc are 
>> already
>> there, they are in the devicet tree spec and provide very specific
>> informations we can use. Much "stronger" hints of what's going on at
>> the hw level. The cpu-map doesn't provide such information, it just
>> provides a view of how the various harts/threads are "packed" on the 
>> chip,
>> not what they share inside each level of "packing". It's useful 
>> because
>> it saves people from having to define a bunch of cache nodes and 
>> describe
>> the cache hierarchy on the device tree using the standard spec.
>> 
> 
> Ah, here comes. If you want to save people's time or whatever, you can 
> use
> your scripting magic you have mentioned above to define those bunch of 
> nodes
> you want to avoid.
> 

I mentioned the script as a transitioning method, but you are right, it 
goes
both ways.

>> So since cpu-map is there for convenience let's make it more 
>> convenient !
>> What I'm saying is that cpu-map could be a more compact way of using 
>> the
>> existing bindings for adding properties on groups of harts instead of
>> putting them on each hart individually. It will simplify the 
>> representation
>> and may also optimize the implementation a bit (we may get the 
>> information
>> we need faster). I don't see any other reason for using cpu-map on 
>> RISC-V
>> or for making it global across archs.
>> 
> 
> Sure, I don't have strong opinions there. Just stop mentioning that 
> this
> is the only solution and all existing ones are broken. They are not and
> needs to be supported until they are explicitly deprecated, becomes
> obsolete and finally removed.
> 
> [...]
> 

But I never said that's "the only solution and everything else is 
broken" !
I'm just proposing an extension to cpu-map since Mark suggested that 
it's
possible. My goal is to try and consolidate cpu-map with what Atish 
proposed
for RISC-V (so that we can use the same code) and point out some issues
on how we use and define the CPU topology.

>> >
>> > Why are you so keen on optimising the representation ?
>> > If you are worried about large systems, generate one instead of
>> > handcrafted.
>> >
>> 
>> I don't see a reason not to try to optimize it, since we are talking
>> about a binding to be used by RISC-V and potentially everybody, I 
>> think
>> it makes sens to improve upon what we already have.
>> 
> 
> Sure, you can always unless you stop treating existing ones are broken.
> I have already told DT bindings are not *normal code*. You can just
> replace existing ones with new optimised ones. You can only add the new
> (*optimised*) ones to the existing ones. You *need* to understand that
> concept first, otherwise there's not point in this endless discussion
> IMO.
> 
> I will stop here as I will have to repeat whatever I have already
> mentioned to comment on your arguments below.
> 
> In summary, I am not against improving the bindings if you think it's
> possible, but I don't see how it's more beneficially especially if we
> are going to support existing ones also. Mark has already given all the
> details.
> 

ACK, thanks a lot for your time and the discussion so far, I really
appreciate it.

Regards,
Nick

From mboxrd@z Thu Jan  1 00:00:00 1970
Return-Path: <SRS0=6doD=NU=lists.infradead.org=linux-riscv-bounces+infradead-linux-riscv=archiver.kernel.org@kernel.org>
X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on
	aws-us-west-2-korg-lkml-1.web.codeaurora.org
X-Spam-Level: 
X-Spam-Status: No, score=-2.5 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED,
	DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_PASS,
	URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0
Received: from mail.kernel.org (mail.kernel.org [198.145.29.99])
	by smtp.lore.kernel.org (Postfix) with ESMTP id 27CAEC43441
	for <infradead-linux-riscv@archiver.kernel.org>; Fri,  9 Nov 2018 02:38:35 +0000 (UTC)
Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133])
	(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))
	(No client certificate requested)
	by mail.kernel.org (Postfix) with ESMTPS id E33EE20840
	for <infradead-linux-riscv@archiver.kernel.org>; Fri,  9 Nov 2018 02:38:34 +0000 (UTC)
Authentication-Results: mail.kernel.org;
	dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="grjIb9EE";
	dkim=fail reason="signature verification failed" (2048-bit key) header.d=infradead.org header.i=@infradead.org header.b="BasDCyW0"
DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org E33EE20840
Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=ics.forth.gr
Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-riscv-bounces+infradead-linux-riscv=archiver.kernel.org@lists.infradead.org
DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed;
	d=lists.infradead.org; s=bombadil.20170209; h=Sender:Content-Type:
	Content-Transfer-Encoding:Cc:List-Subscribe:List-Help:List-Post:List-Archive:
	List-Unsubscribe:List-Id:Message-ID:References:In-Reply-To:Subject:To:From:
	Date:MIME-Version:Reply-To:Content-ID:Content-Description:Resent-Date:
	Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner;
	 bh=Mh6Rzmx3z19EHgCFIE/2yGXMaMxdVinll3kfGnA+IXs=; b=grjIb9EE9m+Byij2q/CKWavSB
	6NwLWQXPRkcPuJev4LR++O0k7Kmpgv+DeIyFg3eptFJN3KbXDB81s+uh0vDlWleqBsOJQD6tbg1mw
	plTmaeQdMApWwkjIDJH7dK+FXWV5XxcXhDXszXqd4ZG/X0Hwfh27A0wdfPqEdIUJvvcC/p55gXqN2
	rFaDeaRBrej3pwQ4IV1XH/+efCRNICLEiMh32N5VptpOc5l0Qr46przVn4IViByOXExfRBDda94eK
	JMBYe7FnwaJsrJyHHbUrnkcrbj92YD8wdhNhEiyaHLApCtKU/apLyoxoLe4n0hfLZZBA1QA//hOdt
	+lCLxgJdg==;
Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org)
	by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux))
	id 1gKwgr-0007Dh-SQ; Fri, 09 Nov 2018 02:38:33 +0000
Received: from casper.infradead.org ([2001:8b0:10b:1236::1])
 by bombadil.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux))
 id 1gKwgq-0007Db-Li
 for linux-riscv@bombadil.infradead.org; Fri, 09 Nov 2018 02:38:32 +0000
DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed;
 d=infradead.org; s=casper.20170209; h=Message-ID:References:In-Reply-To:
 Subject:Cc:To:From:Date:Content-Transfer-Encoding:Content-Type:MIME-Version:
 Sender:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From:
 Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Id:List-Help:
 List-Unsubscribe:List-Subscribe:List-Post:List-Owner:List-Archive;
 bh=faoR7Z4zRGgw2dGvOC9vRjUxbL4bCEDo0iIhRkm3k94=; b=BasDCyW05LM5tRLkg6PrGn7jPQ
 yL2AUdDDOMLumOzTcNkbvzyXjyAK4PADG1gf+Ui4+EoZ3jO1v/GuN0DEI+EglNUZMoE1K07hnysf+
 97tmCNv9F8lzWoiQywyWW6/RRtPWbKOA1A9wkdKvyg5FQFsP+PAabrUN7uQpE8Ode7HY8T1Z8DwRr
 Tf55KoOHMOxB81eOspfqswwiz6s3llSlQllxMJzAKESnIU0pqa26YZepglzrBN1+T0y2T1c1JFOWy
 iaEiAXjpoBQvLRY4ZaEdcLd2K37ng+UVK8+rsMnC2+Q00X9Va+DNNJdN79xD1B3UexkUrPh6kxpnH
 UfrVoceA==;
Received: from mailgate-4.ics.forth.gr ([139.91.1.7])
 by casper.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux))
 id 1gKwgn-0005ct-6O
 for linux-riscv@lists.infradead.org; Fri, 09 Nov 2018 02:38:31 +0000
Received: from av1.ics.forth.gr (av3in.ics.forth.gr. [139.91.1.77])
 by mailgate-4.ics.forth.gr (8.14.5/ICS-FORTH/V10-1.9-GATE-OUT) with ESMTP id
 wA92aNJr016280; Fri, 9 Nov 2018 04:36:25 +0200 (EET)
X-AuditID: 8b5b9d4d-903ff70000000e62-8d-5be4f2a5c8a7
Received: from enigma.ics.forth.gr (enigma.ics.forth.gr [139.91.1.35])
 by av1.ics.forth.gr (SMTP Outbound / FORTH / ICS) with SMTP id
 91.2C.03682.5A2F4EB5; Fri,  9 Nov 2018 04:36:22 +0200 (EET)
Received: from webmail.ics.forth.gr (localhost [127.0.0.1])
 by enigma.ics.forth.gr (8.15.1//ICS-FORTH/V10.5.0C-EXTNULL-SSL-SASL) with
 ESMTP id wA92aJwa012603; Fri, 9 Nov 2018 04:36:19 +0200
X-ICS-AUTH-INFO: Authenticated user:  at ics.forth.gr
MIME-Version: 1.0
Date: Fri, 09 Nov 2018 04:36:19 +0200
From: Nick Kossifidis <mick@ics.forth.gr>
To: Sudeep Holla <sudeep.holla@arm.com>
Subject: Re: [RFC 0/2] Add RISC-V cpu topology
Organization: FORTH
In-Reply-To: <20181108164827.GB10953@e107155-lin>
References: <1541113468-22097-1-git-send-email-atish.patra@wdc.com>
 <866dedbc78ab4fa0e3b040697e112106@mailhost.ics.forth.gr>
 <20181106141331.GA28458@e107155-lin>
 <969fc2a5198984e0dfe8c3f585dc65f9@mailhost.ics.forth.gr>
 <20181106162051.w7fyweuxrl7ujzuz@lakrids.cambridge.arm.com>
 <abcae019e6ae749b17ecb0c721fd3177@mailhost.ics.forth.gr>
 <20181107122803.GA8433@e107155-lin>
 <d04779705c47b59b94300365e805dbd3@mailhost.ics.forth.gr>
 <20181108164827.GB10953@e107155-lin>
Message-ID: <b44d94e4a5575e2ce49344b50956bf8e@mailhost.ics.forth.gr>
X-Sender: mick@mailhost.ics.forth.gr
User-Agent: Roundcube Webmail/1.1.2
X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrMIsWRmVeSWpSXmKPExsXSHc2orLvs05Nog7Zn6hbblqxmtWj58I7V
 YtGK7ywWre3fmCzmHznHanF6wiImi8u75rBZbPvcwmax9PpFJovmd+fYLTZPWMBq0br3CLvF
 8lM7WCw2b5rKbPF8ZS+bA7/HntOzmD3WzFvD6DH19xkWj4ebLjF5bF6h5bFpVSebx7tz59g9
 Ni+p97jUfJ3d4/MmOY/2A91MAdxRXDYpqTmZZalF+nYJXBmbX99mKvjsUvG3jaOBsdOsi5GT
 Q0LARKLt62zmLkYuDiGBw4wS3z83sEI4Bxklrs6/zApRZSoxe28nI4jNKyAocXLmExYQm1nA
 QmLqlf2MELa8RPNWkEmcHCwCqhIHX09hA7HZBDQl5l86CFYvIqAuseTsFkaQBcwC85glpu/Z
 ArZAWEBPomnDTTCbX0BY4tPdi0A2BwengKHEgYPmEAc9ZJZ4/WcfE8QRLhK9p7cwQhynIvHh
 9wN2EFtUQFnixYnprBMYhWYhuXUWkltnIbl1ASPzKkaBxDJjvczkYr20/KKSDL30ok2M4Kic
 67uD8dwC+0OMAhyMSjy8KxqeRAuxJpYVV+YeYpTgYFYS4bXcBxTiTUmsrEotyo8vKs1JLT7E
 KM3BoiTOe/hFeJCQQHpiSWp2ampBahFMlomDU6qBUavx/DsJhjyVso1Nec+fZrG/mury7cJm
 lR0H351UmGL/Z/LN9oexF1jShQp6sx3NW95qmxwscDoq77kogGWp2iGB0Jj5MwWqTPvrEll3
 xsnezJo285j8pLNV1wMWnKxdXHWcUWRZZd4aE7569+ZJTq2Ra7j/Tz197NYjdfsXlW1mSwsX
 znY8p8RSnJFoqMVcVJwIAOq4b5PGAgAA
X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 
X-CRM114-CacheID: sfid-20181109_023829_466348_D126EB65 
X-CRM114-Status: GOOD (  62.45  )
X-BeenThere: linux-riscv@lists.infradead.org
X-Mailman-Version: 2.1.21
Precedence: list
List-Id: <linux-riscv.lists.infradead.org>
List-Unsubscribe: <http://lists.infradead.org/mailman/options/linux-riscv>,
 <mailto:linux-riscv-request@lists.infradead.org?subject=unsubscribe>
List-Archive: <http://lists.infradead.org/pipermail/linux-riscv/>
List-Post: <mailto:linux-riscv@lists.infradead.org>
List-Help: <mailto:linux-riscv-request@lists.infradead.org?subject=help>
List-Subscribe: <http://lists.infradead.org/mailman/listinfo/linux-riscv>,
 <mailto:linux-riscv-request@lists.infradead.org?subject=subscribe>
Cc: Mark Rutland <mark.rutland@arm.com>, devicetree@vger.kernel.org,
 Damien.LeMoal@wdc.com, alankao@andestech.com, hch@infradead.org,
 anup@brainfault.org, palmer@sifive.com, linux-kernel@vger.kernel.org,
 zong@andestech.com, Atish Patra <atish.patra@wdc.com>, robh+dt@kernel.org,
 Nick Kossifidis <mick@ics.forth.gr>, linux-riscv@lists.infradead.org,
 tglx@linutronix.de
Content-Transfer-Encoding: base64
Content-Type: text/plain; charset="utf-8"; Format="flowed"
Sender: "linux-riscv" <linux-riscv-bounces@lists.infradead.org>
Errors-To: linux-riscv-bounces+infradead-linux-riscv=archiver.kernel.org@lists.infradead.org
Message-ID: <20181109023619.GHt6bFIdYLUMPxsDVTOK8GuaGZEsTIOEfRG86dbsRsI@z>

zqPPhM65z4IgMjAxOC0xMS0wOCAxODo0OCwgU3VkZWVwIEhvbGxhIM6tzrPPgc6xz4jOtToKPiBP
biBUaHUsIE5vdiAwOCwgMjAxOCBhdCAwNDo1MjozMFBNICswMjAwLCBOaWNrIEtvc3NpZmlkaXMg
d3JvdGU6Cj4+IM6jz4TOuc+CIDIwMTgtMTEtMDcgMTQ6MjgsIFN1ZGVlcCBIb2xsYSDOrc6zz4HO
sc+IzrU6Cj4+ID4KPj4gPiBJIGFncmVlLCBidXQgd2UgaGF2ZSBrZXJuZWwgY29kZSB1c2luZyBp
dChhcm02NC9rZXJuZWwvdG9wb2xvZ3kuYykuIEl0J3MKPj4gPiB0b28gbGF0ZSB0byByZW1vdmUg
aXQuIEJ1dCB3ZSBjYW4gYWx3YXlzIGtlZXAgdG8gb3B0aW9uYWwgaWYgd2UgbW92ZSB0aGUKPj4g
PiBBUk02NCBiaW5kaW5nIGFzIGdlbmVyaWMgdG8gc3RhcnQgd2l0aCBhbmQgbWFuZGF0ZSBpdCBm
b3Igb25seSBBUk02NC4KPj4gPgo+PiAKPj4gVGhhdCdzIG15IHBvaW50IGFzIHdlbGwsIGlmIHdl
IGFyZSBnb2luZyB0byBkZWZpbmUgc29tZXRoaW5nIHRvIGJlIAo+PiB1c2VkCj4+IGJ5IGV2ZXJ5
Ym9keSBhbmQgaW4gdGhpcyBjYXNlLCBhdCBsZWFzdCBmb3IgUklTQy1WLCB0aGVyZSBpcyBubyBu
ZWVkIAo+PiB0bwo+PiBjYXJyeSB0aGlzIGZyb20gdGhlIEFSTTY0IGJpbmRpbmcuCj4gCj4gU3Vy
ZSwgd2hhdGV2ZXIgeW91IGRvbid0IG5lZWQgaW4gUklTQy1WIHlvdSBjYW4gc2VlIGlmIHRoZXkg
Y2FuIGJlIG1hZGUKPiBvcHRpb25hbC4gSSBkb24ndCB0aGluayB0aGF0IHNob3VsZCBiZSBhIHBy
b2JsZW0uCj4gCj4+IEl0IHNob3VsZG4ndCBiZSB0aGF0IGhhcmQgdG8gZml4IHRoaXMKPj4gaW4g
dGhlIGZ1dHVyZSBmb3IgQVJNNjQgYXMgd2VsbCwgd2UgbWF5IGdpdmUgdGhlIG5ldyBtYXBwaW5n
IGFub3RoZXIgCj4+IG5hbWUsCj4+IG1heWJlIGNwdS1tYXAyIG9yIGNwdS10b3BvbG9neSB0byBz
bG93bHkgbW92ZSB0byB0aGUgbmV3IG9uZS4KPiAKPiBObywgd2UgaGF2ZSBpdCBhbmQgd2Ugd2ls
bCBjb250aW51ZSB0byBzdXBwb3J0IGl0LiBJdCdzIG5vdCBicm9rZW4gdG8KPiBmaXggb24gQVJN
NjQuIFdoeSBkbyB5b3UgdGhpbmsgdGhhdCBpdCdzIGJyb2tlbiBvbiBBUk02NCA/Cj4gCgpJIG5l
dmVyIHNhaWQgaXQncyBicm9rZW4sIEkganVzdCBhc3N1bWVkIHRoYXQgaWYgdGhpcyBiaW5kaW5n
IGJlY29tZXMgCmNvbW1vbgphY3Jvc3MgYXJjaHMgeW91J2QgcHJvYmFibHkgbGlrZSB0byBzd2l0
Y2ggdG8gaXQsIHNvIGl0IHNob3VsZCBlaXRoZXIgYmUKYmFja3dhcmRzIGNvbXBhdGlibGUgd2l0
aCB3aGF0IHlvdSBoYXZlIChvciBhcyB5b3Ugc2FpZCAia2VlcCB0aGVtIApvcHRpb25hbCIpCm9y
IHRha2Ugc3RlcHMgZm9yIHRoZSB0cmFuc2l0aW9uLiBJJ20gb2sgZWl0aGVyIHdheSwgSXQncyBu
b3Qgc3VjaCBhIApzZXJpb3VzCnRoaW5nIHRvIGhhdmUgdGhlIDx0aHJlYWQ+IG5vZGVzIHN1cHBv
cnRlZCBvciBrZWVwIHRoZSBkaXN0aW5jdGlvbiAKYmV0d2VlbgoiY29yZXMiLCAiY2x1c3RlcnMi
IG9yIHdoYXRldmVyLCBJJ20gc29ycnkgaWYgaXQgbG9va2VkIHRoYXQgd2F5LiBJJ20gCmp1c3QK
c2F5aW5nIHRoYXQgSSdkIGxpa2UgdG8gaGF2ZSBzb21ldGhpbmcgY2xlYW5lciBmb3IgUklTQy1W
IGFuZC9vciBhIApiaW5kaW5nCnRoYXQncyBjb21tb24gZm9yIGFsbCwgd2UgY2FuIHN1cHBvcnQg
Ym90aCBhbmQgYmUgYmFja3dhcmRzIGNvbXBhdGlibGUsIApvciB3ZQpjYW4ga2VlcCBpdCBhcyBp
cyBhbmQgbWFuZGF0ZSB0aGUgPHRocmVhZD4gbm9kZXMgb25seSBmb3IgQVJNNjQgYXMgeW91CnN1
Z2dlc3RlZC4KCj4+IENoYW5naW5nIHRoZQo+PiBkdHMgZmlsZXMgc2hvdWxkbid0IGJlIHRoaXMg
aGFyZCwgd2UgY2FuIHByb3ZpZGUgYSBzY3JpcHQgZm9yIGl0LiBXZSAKPj4gY2FuCj4+IGV2ZW4g
Y29udGFpbiBzb21lIGNvbXBhdGliaWxpdHkgY29kZSB0aGF0IGFsc28gdW5kZXJzdGFuZHMgPHRo
cmVhZD4gCj4+IG5vZGVzCj4+IGFuZCBlLmcuIG1lcmdlcyB0aGVtIHRvZ2V0aGVyIG9uIGEgY29y
ZSBub2RlLgo+PiAKPiAKPiBTdXJlLCBoYW5nIG9uIHRoaXMgaWRlYSBvZiBzY3JpcHRpbmcsIHdl
IGNhbiBtYWtlIGEgYmV0dGVyIHVzZSBvZiBpdC4KPiBEZXRhaWxzIGxhdGVyIGZ1cnRoZXIgaW4g
dGhlIG1haWwuCj4gCj4gWy4uLl0KPiAKPj4gPiA+IFRoZSBzYW1lIGFsc28gaGFwcGVucyB3aXRo
IHRoZSBnZW5lcmljIG51bWEgYmluZGluZyBvbgo+PiA+ID4gRG9jdW1lbnRhdGlvbi9kZXZpY2V0
cmVlL2JpbmRpbmdzL251bWEudHh0Cj4+ID4gPiB3aGljaCBzYXlzIHdlIHNob3VsZCBhZGQgdGhl
IG51bmEtbm9kZS1pZCBvbiBlYWNoIG9mIHRoZSBjcHUgbm9kZXMuCj4+ID4gPgo+PiA+Cj4+ID4g
WWVzLCBidXQgYWdhaW4gd2hhdCdzIHRoZSBwcm9ibGVtID8KPj4gPgo+PiAKPj4gVGhlcmUgaXMg
bm8gcHJvYmxlbSB3aXRoIHRoZSBhYm92ZSBiaW5kaW5ncywgdGhlIHByb2JsZW0gaXMgdGhhdCB3
ZSAKPj4gaGF2ZQo+PiB0byBwdXQgdGhlbSBvbiBlYWNoIGNwdSBub2RlIHdoaWNoIGlzIG1lc3N5
LiBXZSBjb3VsZCBpbnN0ZWFkIHB1dCB0aGVtCj4+IChvcHRpb25hbGx5KSBvbiB0aGUgdmFyaW91
cyBncm91cGluZ3MgdXNlZCBvbiBjcHUtbWFwLiBUaGlzIHdvdWxkIAo+PiBhbGxvdwo+PiBjcHUt
bWFwIHRvIGJlIG1vcmUgc3BlY2lmaWMgb2Ygd2hhdCBpcyBzaGFyZWQgYWNyb3NzIHRoZSBtZW1i
ZXJzIG9mIAo+PiBlYWNoCj4+IGdyb3VwIChjb3JlL2NsdXN0ZXIvd2hhdGV2ZXIpLgo+PiAKPiAK
PiBJIHRoaW5rIE1hcmsgaGFzIGFscmVhZHkgZXhwbGFpbiB3aHkvaG93IGdlbmVyaWMgYmluZGlu
Z3MgYXJlIHVzZWZ1bC4KPiBJZiB5b3Ugc3RpbGwgaGF2ZSBjb25jZXJucywgdGFrZSBpdCB1cCBz
ZXBhcmF0ZWx5IGFuZCBzZWUgaG93IHlvdSBjYW4KPiBidWlsZCAqcGVyZmVjdCogYmluZGluZ3Mg
Zm9yIFJJU0MtViB0byBhdm9pZCBhbnkgbGVnYWN5IGJhZ2dhZ2UuCj4gCj4gV2UgaGF2ZSByZWFz
b25zIHdoeSB3ZSBjYW4ndCBhc3N1bWUgaW5mb3JtYXRpb24gYWJvdXQgY2FjaGUgb3IgcG93ZXIK
PiBkb21haW4gdG9wb2xvZ3kgZnJvbSBDUFUgdG9wb2xvZ3kuIEkgaGF2ZSBzdW1tYXJpc2VkIHRo
ZW0gYWxyZWFkeSBhbmQKPiB3ZSBhcmUgbm90IGRpc2N1c3NpbmcuCgpCdXQgdGhhdCdzIHdoYXQg
eW91IGRvIG9uIGFyY2gvYXJtL2tlcm5lbC90b3BvbG9neS5jLCB5b3UgYXNzdW1lCmluZm9ybWF0
aW9uIG9uIHBvd2VyIGRvbWFpbiBhbmQgY2FjaGUgdG9wb2xvZ3kgYmFzZWQgb24gdGhlIENQVSB0
b3BvbG9neQp3aGVuIHlvdSBkZWZpbmUgdGhlIHNjaGVkdWxpbmcgZG9tYWluIHRvcG9sb2d5IGxl
dmVscy4KClBvd2VyUEMgYWxzbyBkb2VzIHRoZSBzYW1lIG9uIGFyY2gvcG93ZXJwYy9rZXJuZWwv
c21wLmMgYW5kIGJhc2ljYWxseSBpZgp5b3UgdHJhY2sgdGhlIHVzYWdlIG9mIHN0cnVjdCBzY2hl
ZF9kb21haW5fdG9wb2xvZ3lfbGV2ZWwgeW91J2xsIHNlZSAKdGhhdApldmVyeSBhcmNoIHRoYXQg
dXNlcyBpdCB0byBpbnN0cnVjdCB0aGUgc2NoZWR1bGVyIGFib3V0IHRoZSBzY2hlZHVsaW5nCmRv
bWFpbnMsIGRvZXMgaXQgYmFzZWQgb24gaXRzIENQVSB0b3BvbG9neSwgd2hpY2ggSSB0aGluayB3
ZSBib3RoIGFncmVlCmlzIHdyb25nLgoKPiBUaGVyZSBtYXkgbm90IGJlIHBlcmZlY3QgYmluZGlu
Z3MgYnV0IHRoZXJlIGFyZQo+IGFscmVhZHkgc3VwcG9ydGVkIGFuZCBub3RoaW5nIGlzIGJyb2tl
biBoZXJlIHRvIGZpeC4gRFQgYmluZGluZ3MgYXJlCj4gKm5vdCogc2FtZSBhcyBjb2RlIHRvIGZp
eCBpdCB3aXRoIGEgcGF0Y2ggdG8gdGhlIGJpbmRpbmdzIHRoZW1zZWx2ZXMuCj4gT25jZSBhZ3Jl
ZWQgYW5kIG1lcmdlZCwgdGhleSBuZWVkIHRvIGJlIHRyZWF0ZWQgbGlrZSB1c2VyIEFCSS4KPiAK
ClRoZSBvbmx5IHVzZSBvZiB0aGUgZGV2aWNldHJlZSBzcGVjIGJpbmRpbmdzIGZvciBjYWNoZXMg
aWYgSSdtIG5vdAptaXN0YWtlbiBhcmUgdXNlZCBvbiB5b3VyIGNhY2hlaW5mbyBkcml2ZXIgZm9y
IGV4cG9ydGluZyB0aGVtIHRvIAp1c2Vyc3BhY2UKdGhyb3VnaCBzeXNmcyAodGhhbmsgeW91IGZv
ciBjbGVhbmluZyB0aGlzIHVwIGJ0dykuIEV2ZW4gaWYgd2UgaGF2ZSB0aGUKY2FjaGUgdG9wb2xv
Z3kgIHVzaW5nIHRoZSBnZW5lcmljIGJpbmRpbmdzLCB3ZSBhcmUgbm90IGRvaW5nIGFueXRoaW5n
IAp3aXRoCnRoYXQgaW5mb3JtYXRpb24gYnV0IGV4cG9ydCBpdCB0byB1c2Vyc3BhY2UuCgpBcyBm
b3IgdGhlIHBvd2VyIGRvbWFpbiBiaW5kaW5ncywgd2UgaGF2ZSBkcml2ZXJzL2Jhc2UvcG93ZXIv
ZG9tYWluLmMgCnRoYXQKaGFuZGxlcyB0aGUgZ2VuZXJpYyBiaW5kaW5ncyBhbmQgaXQncyBiZWlu
ZyB1c2VkIGJ5IHNvbWUgZHJpdmVycyB0byBwdXQKZGV2aWNlcyB0byBwb3dlciBkb21haW5zIChz
b21ldGhpbmcgdXNlZCBieSB0aGUgcG0gY29kZSksIGJ1dCBmcm9tIGEgCnF1aWNrCnNlYXJjaCBp
dCdzIG5vdCB1c2VkIGZvciBjcHUgbm9kZXMgYW5kIEkgZGlkbid0IHNlZSB0aGlzIGluZm8gYmVp
bmcgdXNlZApmb3IgcHJvdmlkaW5nIGhpbnRzIHRvIHRoZSBzY2hlZHVsZXIgZWl0aGVyLiBFdmVu
IHdpdGggdGhlIGdlbmVyaWMgcG93ZXIKZG9tYWluIGJpbmRpbmdzIGluIHBsYWNlLCBmb3IgQ1BV
IGlkbGUgc3RhdGVzLCBvbiBBUk0gd2UgaGF2ZSBhbm90aGVyCmJpbmRpbmcgdGhhdCdzIGJhc2lj
YWxseSB0aGUgc2FtZSB3aXRoIHRoZSBhZGRpdGlvbiBvZiAKIndha2V1cC1sYXRlbmN5LXVzIi4K
CkZvciBoYXZpbmcgZGlmZmVyZW50IGNhcGFjaXR5IHRoZXJlIGlzIG5vIGdlbmVyaWMgYmluZGlu
ZyBidXQgSSBndWVzcyB3ZQpjb3VsZCB1c2UgQVJNJ3MuCgpPZiB0aGUgZ2VuZXJpYyBiaW5kaW5n
cyB0aGF0IHJlbGF0ZSB0byB0aGUgc2NoZWR1bGVyJ3MgYmVoYXZpb3IsIG9ubHkgCnRoZQpudW1h
IGJpbmRpbmcgaXMgdXNlZCBhcyBleHBlY3RlZCBhbmQgb25seSBieSBBUk02NCwgcG93ZXJwYyBh
bmQgc3BhcmMgCnVzZQp0aGVpciBvd24gc3R1ZmYuCgpTbyB0aGVyZSBtYXkgYmUgbm90aGluZyBi
cm9rZW4gcmVnYXJkaW5nIHRoZSBnZW5lcmljIC8gYWxyZWFkeSBleGlzdGluZwpiaW5kaW5ncywg
YnV0IHRoZWlyIHN1cHBvcnQgbmVlZHMgZml4aW5nLiBUaGUgd2F5IHRoZXkgYXJlIG5vdyB3ZSBj
YW4ndAp1c2UgdGhlbSBvbiBSSVNDLVYgZm9yIGNvbmZpZ3VyaW5nIHRoZSBzY2hlZHVsZXIgYW5k
IHN1cHBvcnRpbmcgU01UIGFuZApNQyBwcm9wZXJseSArIEknbSBub3QgaW4gZmF2b3Igb2YgdXNp
bmcgQ1BVIHRvcG9sb2d5IGJsaW5kbHkgYXMgdGhlCm90aGVyIGFyY2hzIGRvLgoKPj4gQXMgSSB3
cm90ZSBvbiBteSBhbnN3ZXIgdG8gTWFyayBwcmV2aW91c2x5LCB0aGUgYmluZGluZ3MgZm9yIGlu
ZmVyaW5nCj4+IHRoZSBjYWNoZSB0b3BvbG9neSwgbnVtYSB0b3BvbG9neSwgcG93ZXIgZG9tYWlu
IHRvcG9sb2d5IGV0YyBhcmUgCj4+IGFscmVhZHkKPj4gdGhlcmUsIHRoZXkgYXJlIGluIHRoZSBk
ZXZpY2V0IHRyZWUgc3BlYyBhbmQgcHJvdmlkZSB2ZXJ5IHNwZWNpZmljCj4+IGluZm9ybWF0aW9u
cyB3ZSBjYW4gdXNlLiBNdWNoICJzdHJvbmdlciIgaGludHMgb2Ygd2hhdCdzIGdvaW5nIG9uIGF0
Cj4+IHRoZSBodyBsZXZlbC4gVGhlIGNwdS1tYXAgZG9lc24ndCBwcm92aWRlIHN1Y2ggaW5mb3Jt
YXRpb24sIGl0IGp1c3QKPj4gcHJvdmlkZXMgYSB2aWV3IG9mIGhvdyB0aGUgdmFyaW91cyBoYXJ0
cy90aHJlYWRzIGFyZSAicGFja2VkIiBvbiB0aGUgCj4+IGNoaXAsCj4+IG5vdCB3aGF0IHRoZXkg
c2hhcmUgaW5zaWRlIGVhY2ggbGV2ZWwgb2YgInBhY2tpbmciLiBJdCdzIHVzZWZ1bCAKPj4gYmVj
YXVzZQo+PiBpdCBzYXZlcyBwZW9wbGUgZnJvbSBoYXZpbmcgdG8gZGVmaW5lIGEgYnVuY2ggb2Yg
Y2FjaGUgbm9kZXMgYW5kIAo+PiBkZXNjcmliZQo+PiB0aGUgY2FjaGUgaGllcmFyY2h5IG9uIHRo
ZSBkZXZpY2UgdHJlZSB1c2luZyB0aGUgc3RhbmRhcmQgc3BlYy4KPj4gCj4gCj4gQWgsIGhlcmUg
Y29tZXMuIElmIHlvdSB3YW50IHRvIHNhdmUgcGVvcGxlJ3MgdGltZSBvciB3aGF0ZXZlciwgeW91
IGNhbiAKPiB1c2UKPiB5b3VyIHNjcmlwdGluZyBtYWdpYyB5b3UgaGF2ZSBtZW50aW9uZWQgYWJv
dmUgdG8gZGVmaW5lIHRob3NlIGJ1bmNoIG9mIAo+IG5vZGVzCj4geW91IHdhbnQgdG8gYXZvaWQu
Cj4gCgpJIG1lbnRpb25lZCB0aGUgc2NyaXB0IGFzIGEgdHJhbnNpdGlvbmluZyBtZXRob2QsIGJ1
dCB5b3UgYXJlIHJpZ2h0LCBpdCAKZ29lcwpib3RoIHdheXMuCgo+PiBTbyBzaW5jZSBjcHUtbWFw
IGlzIHRoZXJlIGZvciBjb252ZW5pZW5jZSBsZXQncyBtYWtlIGl0IG1vcmUgCj4+IGNvbnZlbmll
bnQgIQo+PiBXaGF0IEknbSBzYXlpbmcgaXMgdGhhdCBjcHUtbWFwIGNvdWxkIGJlIGEgbW9yZSBj
b21wYWN0IHdheSBvZiB1c2luZyAKPj4gdGhlCj4+IGV4aXN0aW5nIGJpbmRpbmdzIGZvciBhZGRp
bmcgcHJvcGVydGllcyBvbiBncm91cHMgb2YgaGFydHMgaW5zdGVhZCBvZgo+PiBwdXR0aW5nIHRo
ZW0gb24gZWFjaCBoYXJ0IGluZGl2aWR1YWxseS4gSXQgd2lsbCBzaW1wbGlmeSB0aGUgCj4+IHJl
cHJlc2VudGF0aW9uCj4+IGFuZCBtYXkgYWxzbyBvcHRpbWl6ZSB0aGUgaW1wbGVtZW50YXRpb24g
YSBiaXQgKHdlIG1heSBnZXQgdGhlIAo+PiBpbmZvcm1hdGlvbgo+PiB3ZSBuZWVkIGZhc3Rlciku
IEkgZG9uJ3Qgc2VlIGFueSBvdGhlciByZWFzb24gZm9yIHVzaW5nIGNwdS1tYXAgb24gCj4+IFJJ
U0MtVgo+PiBvciBmb3IgbWFraW5nIGl0IGdsb2JhbCBhY3Jvc3MgYXJjaHMuCj4+IAo+IAo+IFN1
cmUsIEkgZG9uJ3QgaGF2ZSBzdHJvbmcgb3BpbmlvbnMgdGhlcmUuIEp1c3Qgc3RvcCBtZW50aW9u
aW5nIHRoYXQgCj4gdGhpcwo+IGlzIHRoZSBvbmx5IHNvbHV0aW9uIGFuZCBhbGwgZXhpc3Rpbmcg
b25lcyBhcmUgYnJva2VuLiBUaGV5IGFyZSBub3QgYW5kCj4gbmVlZHMgdG8gYmUgc3VwcG9ydGVk
IHVudGlsIHRoZXkgYXJlIGV4cGxpY2l0bHkgZGVwcmVjYXRlZCwgYmVjb21lcwo+IG9ic29sZXRl
IGFuZCBmaW5hbGx5IHJlbW92ZWQuCj4gCj4gWy4uLl0KPiAKCkJ1dCBJIG5ldmVyIHNhaWQgdGhh
dCdzICJ0aGUgb25seSBzb2x1dGlvbiBhbmQgZXZlcnl0aGluZyBlbHNlIGlzIApicm9rZW4iICEK
SSdtIGp1c3QgcHJvcG9zaW5nIGFuIGV4dGVuc2lvbiB0byBjcHUtbWFwIHNpbmNlIE1hcmsgc3Vn
Z2VzdGVkIHRoYXQgCml0J3MKcG9zc2libGUuIE15IGdvYWwgaXMgdG8gdHJ5IGFuZCBjb25zb2xp
ZGF0ZSBjcHUtbWFwIHdpdGggd2hhdCBBdGlzaCAKcHJvcG9zZWQKZm9yIFJJU0MtViAoc28gdGhh
dCB3ZSBjYW4gdXNlIHRoZSBzYW1lIGNvZGUpIGFuZCBwb2ludCBvdXQgc29tZSBpc3N1ZXMKb24g
aG93IHdlIHVzZSBhbmQgZGVmaW5lIHRoZSBDUFUgdG9wb2xvZ3kuCgo+PiA+Cj4+ID4gV2h5IGFy
ZSB5b3Ugc28ga2VlbiBvbiBvcHRpbWlzaW5nIHRoZSByZXByZXNlbnRhdGlvbiA/Cj4+ID4gSWYg
eW91IGFyZSB3b3JyaWVkIGFib3V0IGxhcmdlIHN5c3RlbXMsIGdlbmVyYXRlIG9uZSBpbnN0ZWFk
IG9mCj4+ID4gaGFuZGNyYWZ0ZWQuCj4+ID4KPj4gCj4+IEkgZG9uJ3Qgc2VlIGEgcmVhc29uIG5v
dCB0byB0cnkgdG8gb3B0aW1pemUgaXQsIHNpbmNlIHdlIGFyZSB0YWxraW5nCj4+IGFib3V0IGEg
YmluZGluZyB0byBiZSB1c2VkIGJ5IFJJU0MtViBhbmQgcG90ZW50aWFsbHkgZXZlcnlib2R5LCBJ
IAo+PiB0aGluawo+PiBpdCBtYWtlcyBzZW5zIHRvIGltcHJvdmUgdXBvbiB3aGF0IHdlIGFscmVh
ZHkgaGF2ZS4KPj4gCj4gCj4gU3VyZSwgeW91IGNhbiBhbHdheXMgdW5sZXNzIHlvdSBzdG9wIHRy
ZWF0aW5nIGV4aXN0aW5nIG9uZXMgYXJlIGJyb2tlbi4KPiBJIGhhdmUgYWxyZWFkeSB0b2xkIERU
IGJpbmRpbmdzIGFyZSBub3QgKm5vcm1hbCBjb2RlKi4gWW91IGNhbiBqdXN0Cj4gcmVwbGFjZSBl
eGlzdGluZyBvbmVzIHdpdGggbmV3IG9wdGltaXNlZCBvbmVzLiBZb3UgY2FuIG9ubHkgYWRkIHRo
ZSBuZXcKPiAoKm9wdGltaXNlZCopIG9uZXMgdG8gdGhlIGV4aXN0aW5nIG9uZXMuIFlvdSAqbmVl
ZCogdG8gdW5kZXJzdGFuZCB0aGF0Cj4gY29uY2VwdCBmaXJzdCwgb3RoZXJ3aXNlIHRoZXJlJ3Mg
bm90IHBvaW50IGluIHRoaXMgZW5kbGVzcyBkaXNjdXNzaW9uCj4gSU1PLgo+IAo+IEkgd2lsbCBz
dG9wIGhlcmUgYXMgSSB3aWxsIGhhdmUgdG8gcmVwZWF0IHdoYXRldmVyIEkgaGF2ZSBhbHJlYWR5
Cj4gbWVudGlvbmVkIHRvIGNvbW1lbnQgb24geW91ciBhcmd1bWVudHMgYmVsb3cuCj4gCj4gSW4g
c3VtbWFyeSwgSSBhbSBub3QgYWdhaW5zdCBpbXByb3ZpbmcgdGhlIGJpbmRpbmdzIGlmIHlvdSB0
aGluayBpdCdzCj4gcG9zc2libGUsIGJ1dCBJIGRvbid0IHNlZSBob3cgaXQncyBtb3JlIGJlbmVm
aWNpYWxseSBlc3BlY2lhbGx5IGlmIHdlCj4gYXJlIGdvaW5nIHRvIHN1cHBvcnQgZXhpc3Rpbmcg
b25lcyBhbHNvLiBNYXJrIGhhcyBhbHJlYWR5IGdpdmVuIGFsbCB0aGUKPiBkZXRhaWxzLgo+IAoK
QUNLLCB0aGFua3MgYSBsb3QgZm9yIHlvdXIgdGltZSBhbmQgdGhlIGRpc2N1c3Npb24gc28gZmFy
LCBJIHJlYWxseQphcHByZWNpYXRlIGl0LgoKUmVnYXJkcywKTmljawoKCl9fX19fX19fX19fX19f
X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fCmxpbnV4LXJpc2N2IG1haWxpbmcgbGlz
dApsaW51eC1yaXNjdkBsaXN0cy5pbmZyYWRlYWQub3JnCmh0dHA6Ly9saXN0cy5pbmZyYWRlYWQu
b3JnL21haWxtYW4vbGlzdGluZm8vbGludXgtcmlzY3YK