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[114.34.229.221]) by smtp.gmail.com with ESMTPSA id j70sm12876254pfd.208.2020.06.28.20.19.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 28 Jun 2020 20:19:23 -0700 (PDT) From: Zong Li To: palmer@dabbelt.com, paul.walmsley@sifive.com, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [RFC PATCH 2/6] riscv: dts: sifive: Add DT support for PMU Date: Mon, 29 Jun 2020 11:19:11 +0800 Message-Id: X-Mailer: git-send-email 2.27.0 In-Reply-To: References: MIME-Version: 1.0 X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Zong Li Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Add performance monitor unit DT node in SiFive Fu540 soc-specific DT file. This pmu node passes the dtbs_check verification. Signed-off-by: Zong Li --- arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi index 7db861053483..824351fe2a57 100644 --- a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi +++ b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi @@ -283,4 +283,17 @@ gpio: gpio@10060000 { status = "disabled"; }; }; + pmu { + compatible = "riscv,pmu"; + riscv,width-base-cntr = <64>; + riscv,width-event-cntr = <40>; + riscv,n-event-cntr = <2>; + riscv,hw-event-map = <0x0 0x0 + 0x1 0x1 + 0x3 0x0202 + 0x4 0x4000 + 0x5 0x2001>; + riscv,hw-cache-event-map = <0x010201 0x0102 + 0x010204 0x0802>; + }; }; -- 2.27.0 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv