From: <Conor.Dooley@microchip.com>
To: <sboyd@kernel.org>
Cc: <palmer@dabbelt.com>, <robh+dt@kernel.org>,
<Daire.McNamara@microchip.com>, <paul.walmsley@sifive.com>,
<aou@eecs.berkeley.edu>, <linux-clk@vger.kernel.org>,
<devicetree@vger.kernel.org>, <p.zabel@pengutronix.de>,
<linux-kernel@vger.kernel.org>, <linux-riscv@lists.infradead.org>,
<krzysztof.kozlowski+dt@linaro.org>, <mturquette@baylibre.com>
Subject: Re: [PATCH v2 00/12] PolarFire SoC reset controller & clock cleanups
Date: Wed, 20 Jul 2022 13:46:25 +0000 [thread overview]
Message-ID: <ee72b966-433d-ae9e-4544-44ad1fd1abad@microchip.com> (raw)
In-Reply-To: <20220704121558.2088698-1-conor.dooley@microchip.com>
On 04/07/2022 13:15, Conor Dooley wrote:
> Hey all,
> I know I have not sat on the RFC I sent about the aux. bus parts
> for too long, but figured I'd just send the whole thing anyway to all
> lists etc.
Hey Stephen,
Any comments on the clk/auxdev side of this series?
Thanks,
Conor.
>
> Kinda two things happening in this series, but I sent it together to
> ensure the second part would apply correctly.
>
> The first is the reset controller that I promised after discovering the
> issue triggered by CONFIG_PM & the phy not coming up correctly. I have
> now removed all the messing with resets from clock enable/disable
> functions & now use the aux bus to set up a reset controller driver.
> Since I needed something to test it, I hooked up the reset for the
> Cadence MACB on PolarFire SoC. This has been split into a second series
> for v2:
> https://lore.kernel.org/all/20220704114511.1892332-1-conor.dooley@microchip.com/
>
> The second part adds rate control for the MSS PLL clock, followed by
> some simplifications to the driver & conversions of some custom structs
> to the corresponding structs in the framework.
>
> Thanks,
> Conor.
>
> Changes since v1:
> - split off the net patches
> - clk: actually pass the spinlock to the converted dividers & gates
> - reset: added a spinlock around RMW access to registers
> - reset: switched to BIT(i) macros
> - reset: used local copies of some variables as pointed out by Philipp
> - reset: dropped the success printout
>
> Conor Dooley (12):
> dt-bindings: clk: microchip: mpfs: add reset controller support
> clk: microchip: mpfs: add reset controller
> reset: add polarfire soc reset support
> MAINTAINERS: add polarfire soc reset controller
> riscv: dts: microchip: add mpfs specific macb reset support
> clk: microchip: mpfs: add module_authors entries
> clk: microchip: mpfs: add MSS pll's set & round rate
> clk: microchip: mpfs: move id & offset out of clock structs
> clk: microchip: mpfs: simplify control reg access
> clk: microchip: mpfs: delete 2 line mpfs_clk_register_foo()
> clk: microchip: mpfs: convert cfg_clk to clk_divider
> clk: microchip: mpfs: convert periph_clk to clk_gate
>
> .../bindings/clock/microchip,mpfs.yaml | 17 +-
> MAINTAINERS | 1 +
> arch/riscv/boot/dts/microchip/mpfs.dtsi | 7 +-
> drivers/clk/microchip/Kconfig | 1 +
> drivers/clk/microchip/clk-mpfs.c | 379 +++++++++---------
> drivers/reset/Kconfig | 7 +
> drivers/reset/Makefile | 2 +-
> drivers/reset/reset-mpfs.c | 157 ++++++++
> include/soc/microchip/mpfs.h | 8 +
> 9 files changed, 386 insertions(+), 193 deletions(-)
> create mode 100644 drivers/reset/reset-mpfs.c
>
>
> base-commit: b13baccc3850ca8b8cccbf8ed9912dbaa0fdf7f3
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next prev parent reply other threads:[~2022-07-20 13:47 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-07-04 12:15 [PATCH v2 00/12] PolarFire SoC reset controller & clock cleanups Conor Dooley
2022-07-04 12:15 ` [PATCH v2 01/12] dt-bindings: clk: microchip: mpfs: add reset controller support Conor Dooley
2022-07-04 12:15 ` [PATCH v2 02/12] clk: microchip: mpfs: add reset controller Conor Dooley
2022-07-04 12:15 ` [PATCH v2 03/12] reset: add polarfire soc reset support Conor Dooley
2022-07-18 11:34 ` Conor.Dooley
2022-07-18 15:42 ` Philipp Zabel
2022-07-18 15:44 ` Conor.Dooley
2022-07-04 12:15 ` [PATCH v2 04/12] MAINTAINERS: add polarfire soc reset controller Conor Dooley
2022-07-04 12:15 ` [PATCH v2 05/12] riscv: dts: microchip: add mpfs specific macb reset support Conor Dooley
2022-07-04 12:15 ` [PATCH v2 06/12] clk: microchip: mpfs: add module_authors entries Conor Dooley
2022-07-04 12:15 ` [PATCH v2 07/12] clk: microchip: mpfs: add MSS pll's set & round rate Conor Dooley
2022-07-04 12:15 ` [PATCH v2 08/12] clk: microchip: mpfs: move id & offset out of clock structs Conor Dooley
2022-07-04 12:15 ` [PATCH v2 09/12] clk: microchip: mpfs: simplify control reg access Conor Dooley
2022-07-04 12:15 ` [PATCH v2 10/12] clk: microchip: mpfs: delete 2 line mpfs_clk_register_foo() Conor Dooley
2022-07-04 12:15 ` [PATCH v2 11/12] clk: microchip: mpfs: convert cfg_clk to clk_divider Conor Dooley
2022-07-04 12:15 ` [PATCH v2 12/12] clk: microchip: mpfs: convert periph_clk to clk_gate Conor Dooley
2022-07-20 13:46 ` Conor.Dooley [this message]
2022-08-09 23:05 ` [PATCH v2 00/12] PolarFire SoC reset controller & clock cleanups Conor.Dooley
2022-08-10 18:56 ` Nathan Chancellor
2022-08-10 19:20 ` Conor.Dooley
2022-08-10 19:32 ` Nathan Chancellor
2022-08-10 19:43 ` Conor.Dooley
2022-08-11 13:13 ` Conor.Dooley
2022-08-14 11:41 ` Conor.Dooley
2022-08-17 12:17 ` Conor.Dooley
2022-08-17 16:18 ` Nathan Chancellor
2022-08-10 11:50 ` Daire.McNamara
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