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X-IronPort-AV: E=Sophos;i="5.56,327,1539619200"; d="scan'208";a="101007005" Received: from h199-255-45-14.hgst.com (HELO uls-op-cesaep01.wdc.com) ([199.255.45.14]) by ob1.hgst.iphmx.com with ESMTP; 08 Dec 2018 07:36:50 +0800 Received: from uls-op-cesaip02.wdc.com ([10.248.3.37]) by uls-op-cesaep01.wdc.com with ESMTP; 07 Dec 2018 15:18:47 -0800 Received: from gj0bt32.ad.shared (HELO [10.86.57.164]) ([10.86.57.164]) by uls-op-cesaip02.wdc.com with ESMTP; 07 Dec 2018 15:36:50 -0800 Subject: Re: [PATCH 2/4] RISC-V: Support per-hart timebase-frequency To: Palmer Dabbelt References: From: Atish Patra Message-ID: Date: Fri, 7 Dec 2018 15:36:49 -0800 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.13; rv:60.0) Gecko/20100101 Thunderbird/60.3.0 MIME-Version: 1.0 In-Reply-To: Content-Language: en-US X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20181207_153702_911101_99DF3CBE X-CRM114-Status: GOOD ( 20.74 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "mark.rutland@arm.com" , "devicetree@vger.kernel.org" , Damien Le Moal , "aou@eecs.berkeley.edu" , "dmitriy@oss-tech.org" , "anup@brainfault.org" , "daniel.lezcano@linaro.org" , "linux-kernel@vger.kernel.org" , "robh+dt@kernel.org" , "linux-riscv@lists.infradead.org" , "tglx@linutronix.de" Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-riscv" Errors-To: linux-riscv-bounces+infradead-linux-riscv=archiver.kernel.org@lists.infradead.org On 12/7/18 8:42 AM, Palmer Dabbelt wrote: > On Mon, 03 Dec 2018 12:57:29 PST (-0800), atish.patra@wdc.com wrote: >> Follow the updated DT specs and read the timebase-frequency >> from the boot cpu. Keep the old DT reading as well for backward >> compatibility. This patch is rework of old patch from Palmer. >> >> Signed-off-by: Atish Patra >> --- >> arch/riscv/kernel/time.c | 9 +-------- >> drivers/clocksource/riscv_timer.c | 22 ++++++++++++++++++++++ >> 2 files changed, 23 insertions(+), 8 deletions(-) >> >> diff --git a/arch/riscv/kernel/time.c b/arch/riscv/kernel/time.c >> index 1911c8f6..225fe743 100644 >> --- a/arch/riscv/kernel/time.c >> +++ b/arch/riscv/kernel/time.c >> @@ -20,14 +20,7 @@ unsigned long riscv_timebase; >> >> void __init time_init(void) >> { >> - struct device_node *cpu; >> - u32 prop; >> - >> - cpu = of_find_node_by_path("/cpus"); >> - if (!cpu || of_property_read_u32(cpu, "timebase-frequency", &prop)) >> - panic(KERN_WARNING "RISC-V system with no 'timebase-frequency' in DTS\n"); >> - riscv_timebase = prop; >> + timer_probe(); >> >> lpj_fine = riscv_timebase / HZ; >> - timer_probe(); >> } >> diff --git a/drivers/clocksource/riscv_timer.c b/drivers/clocksource/riscv_timer.c >> index 084e97dc..96af7058 100644 >> --- a/drivers/clocksource/riscv_timer.c >> +++ b/drivers/clocksource/riscv_timer.c >> @@ -83,6 +83,26 @@ void riscv_timer_interrupt(void) >> evdev->event_handler(evdev); >> } >> >> +static long __init riscv_timebase_frequency(struct device_node *node) >> +{ >> + u32 timebase; >> + >> + if (!of_property_read_u32(node, "timebase-frequency", &timebase)) >> + return timebase; >> + >> + /* >> + * As per the DT specification, timebase-frequency should be present >> + * under individual cpu node. Unfortunately, there are already available >> + * HiFive Unleashed devices where the timebase-frequency entry is under >> + * CPUs. check under parent "cpus" node to cover those devices. >> + */ >> + if (!of_property_read_u32(node->parent, "timebase-frequency", >> + &timebase)) >> + return timebase; >> + >> + panic("RISC-V system with no 'timebase-frequency' in DTS\n"); >> +} >> + >> static int __init riscv_timer_init_dt(struct device_node *n) >> { >> int cpuid, hartid, error; >> @@ -94,6 +114,8 @@ static int __init riscv_timer_init_dt(struct device_node *n) >> if (cpuid != smp_processor_id()) >> return 0; >> >> + /* This should be called only for boot cpu */ >> + riscv_timebase = riscv_timebase_frequency(n); >> cs = per_cpu_ptr(&riscv_clocksource, cpuid); >> clocksource_register_hz(cs, riscv_timebase); > > We need to check to make sure the timebase-frequency of each hart is the same. > This is mandated by the RISC-V ISA specification but should be checked in the > code. > Fair enough. I will add a timebase-frequency verification function that will be executed for every cpu instead of boot cpu. If any cpu's timebase-frequency doesn't match with boot cpu, should we just WARN? or Do we need panic given that DT is not following something that is mandated by ISA ? Regards, Atish _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv