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Fri, 13 Dec 2019 18:13:23 -0800 (PST) Date: Fri, 13 Dec 2019 18:13:23 -0800 (PST) X-Google-Original-Date: Fri, 13 Dec 2019 18:13:20 PST (-0800) From: Palmer Dabbelt X-Google-Original-From: Palmer Dabbelt Subject: Re: [PATCH 1/2] riscv: dts: Add DT support for SiFive L2 cache controller To: yash.shah@sifive.com In-Reply-To: <1575890706-36162-2-git-send-email-yash.shah@sifive.com> References: <1575890706-36162-2-git-send-email-yash.shah@sifive.com> <1575890706-36162-1-git-send-email-yash.shah@sifive.com> Message-ID: Mime-Version: 1.0 (MHng) Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191213_181325_877993_AC0F544A X-CRM114-Status: GOOD ( 13.25 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.rutland@arm.com, devicetree@vger.kernel.org, aou@eecs.berkeley.edu, Atish Patra , Greg KH , linux-kernel@vger.kernel.org, alexios.zavras@intel.com, yash.shah@sifive.com, robh+dt@kernel.org, Paul Walmsley , tglx@linutronix.de, bmeng.cn@gmail.com, linux-riscv@lists.infradead.org, allison@lohutok.net Sender: "linux-riscv" Errors-To: linux-riscv-bounces+infradead-linux-riscv=archiver.kernel.org@lists.infradead.org On Mon, 09 Dec 2019 03:25:05 PST (-0800), yash.shah@sifive.com wrote: > Add the L2 cache controller DT node in SiFive FU540 soc-specific DT file > > Signed-off-by: Yash Shah > --- > arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 26 ++++++++++++++++++++++++++ > 1 file changed, 26 insertions(+) > > diff --git a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi > index afa43c7..812db02 100644 > --- a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi > +++ b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi > @@ -19,6 +19,16 @@ > chosen { > }; > > + reserved-memory { > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + > + l2_lim: lim@0x8000000 { > + reg = <0x0 0x8000000 0x0 0x2000000>; > + }; > + }; > + > cpus { > #address-cells = <1>; > #size-cells = <0>; > @@ -54,6 +64,7 @@ > reg = <1>; > riscv,isa = "rv64imafdc"; > tlb-split; > + next-level-cache = <&l2cache>; > cpu1_intc: interrupt-controller { > #interrupt-cells = <1>; > compatible = "riscv,cpu-intc"; > @@ -77,6 +88,7 @@ > reg = <2>; > riscv,isa = "rv64imafdc"; > tlb-split; > + next-level-cache = <&l2cache>; > cpu2_intc: interrupt-controller { > #interrupt-cells = <1>; > compatible = "riscv,cpu-intc"; > @@ -100,6 +112,7 @@ > reg = <3>; > riscv,isa = "rv64imafdc"; > tlb-split; > + next-level-cache = <&l2cache>; > cpu3_intc: interrupt-controller { > #interrupt-cells = <1>; > compatible = "riscv,cpu-intc"; > @@ -123,6 +136,7 @@ > reg = <4>; > riscv,isa = "rv64imafdc"; > tlb-split; > + next-level-cache = <&l2cache>; > cpu4_intc: interrupt-controller { > #interrupt-cells = <1>; > compatible = "riscv,cpu-intc"; > @@ -246,6 +260,18 @@ > #pwm-cells = <3>; > status = "disabled"; > }; > + l2cache: cache-controller@2010000 { > + compatible = "sifive,fu540-c000-ccache", "cache"; > + cache-block-size = <64>; > + cache-level = <2>; > + cache-sets = <1024>; > + cache-size = <2097152>; > + cache-unified; > + interrupt-parent = <&plic0>; > + interrupts = <1 2 3>; > + reg = <0x0 0x2010000 0x0 0x1000>; > + memory-region = <&l2_lim>; > + }; > > }; > }; Reviewed-by: Palmer Dabbelt