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From: Palmer Dabbelt <palmerdabbelt@google.com>
To: Anup Patel <Anup.Patel@wdc.com>
Cc: Alistair Francis <Alistair.Francis@wdc.com>,
	aou@eecs.berkeley.edu, kvm@vger.kernel.org, rkrcmar@redhat.com,
	anup@brainfault.org, Anup Patel <Anup.Patel@wdc.com>,
	Damien Le Moal <Damien.LeMoal@wdc.com>,
	linux-kernel@vger.kernel.org, Atish Patra <Atish.Patra@wdc.com>,
	graf@amazon.com, kvm-riscv@lists.infradead.org,
	Paul Walmsley <paul.walmsley@sifive.com>,
	pbonzini@redhat.com, linux-riscv@lists.infradead.org,
	Christoph Hellwig <hch@lst.de>
Subject: Re: [PATCH v10 03/19] RISC-V: Add hypervisor extension related CSR defines
Date: Thu, 16 Jan 2020 11:51:42 -0800 (PST)
Message-ID: <mhng-1c0b8288-1b2b-4172-b224-5277a9d3fcaa@palmerdabbelt-glaptop> (raw)
In-Reply-To: <20191223113443.68969-4-anup.patel@wdc.com>

On Mon, 23 Dec 2019 03:35:33 PST (-0800), Anup Patel wrote:
> This patch extends asm/csr.h by adding RISC-V hypervisor extension
> related defines.
>
> Signed-off-by: Anup Patel <anup.patel@wdc.com>
> Acked-by: Paolo Bonzini <pbonzini@redhat.com>
> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
> Reviewed-by: Alexander Graf <graf@amazon.com>
> ---
>  arch/riscv/include/asm/csr.h | 78 ++++++++++++++++++++++++++++++++++--
>  1 file changed, 75 insertions(+), 3 deletions(-)
>
> diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h
> index 0a62d2d68455..afb6733475c2 100644
> --- a/arch/riscv/include/asm/csr.h
> +++ b/arch/riscv/include/asm/csr.h
> @@ -30,6 +30,8 @@
>  #define SR_XS_CLEAN	_AC(0x00010000, UL)
>  #define SR_XS_DIRTY	_AC(0x00018000, UL)
>  
> +#define SR_MXR		_AC(0x00080000, UL)
> +
>  #ifndef CONFIG_64BIT
>  #define SR_SD		_AC(0x80000000, UL) /* FS/XS dirty */
>  #else
> @@ -51,26 +53,74 @@
>  #define CAUSE_IRQ_FLAG		(_AC(1, UL) << (__riscv_xlen - 1))
>  
>  /* Interrupt causes (minus the high bit) */
> -#define IRQ_U_SOFT		0
>  #define IRQ_S_SOFT		1
> +#define IRQ_VS_SOFT		2

Again: please don't mix up cleanups with the KVM port.  It's reasonable to
remove the N extension cruft as it's still in draft and we probably won't
implement it in Linux, but that shouldn't be mixed up with the KVM
implementation.

>  #define IRQ_M_SOFT		3
> -#define IRQ_U_TIMER		4
>  #define IRQ_S_TIMER		5
> +#define IRQ_VS_TIMER		6
>  #define IRQ_M_TIMER		7
> -#define IRQ_U_EXT		8
>  #define IRQ_S_EXT		9
> +#define IRQ_VS_EXT		10
>  #define IRQ_M_EXT		11
>  
>  /* Exception causes */
>  #define EXC_INST_MISALIGNED	0
>  #define EXC_INST_ACCESS		1
> +#define EXC_INST_ILLEGAL	2
>  #define EXC_BREAKPOINT		3
>  #define EXC_LOAD_ACCESS		5
>  #define EXC_STORE_ACCESS	7
>  #define EXC_SYSCALL		8
> +#define EXC_HYPERVISOR_SYSCALL	9
> +#define EXC_SUPERVISOR_SYSCALL	10
>  #define EXC_INST_PAGE_FAULT	12
>  #define EXC_LOAD_PAGE_FAULT	13
>  #define EXC_STORE_PAGE_FAULT	15
> +#define EXC_INST_GUEST_PAGE_FAULT	20
> +#define EXC_LOAD_GUEST_PAGE_FAULT	21
> +#define EXC_STORE_GUEST_PAGE_FAULT	23
> +
> +/* HSTATUS flags */
> +#define HSTATUS_VTSR		_AC(0x00400000, UL)
> +#define HSTATUS_VTVM		_AC(0x00100000, UL)
> +#define HSTATUS_SP2V		_AC(0x00000200, UL)
> +#define HSTATUS_SP2P		_AC(0x00000100, UL)
> +#define HSTATUS_SPV		_AC(0x00000080, UL)
> +#define HSTATUS_SPRV		_AC(0x00000001, UL)
> +
> +/* HGATP flags */
> +#define HGATP_MODE_OFF		_AC(0, UL)
> +#define HGATP_MODE_SV32X4	_AC(1, UL)
> +#define HGATP_MODE_SV39X4	_AC(8, UL)
> +#define HGATP_MODE_SV48X4	_AC(9, UL)
> +
> +#define HGATP32_MODE_SHIFT	31
> +#define HGATP32_VMID_SHIFT	22
> +#define HGATP32_VMID_MASK	_AC(0x1FC00000, UL)
> +#define HGATP32_PPN		_AC(0x003FFFFF, UL)
> +
> +#define HGATP64_MODE_SHIFT	60
> +#define HGATP64_VMID_SHIFT	44
> +#define HGATP64_VMID_MASK	_AC(0x03FFF00000000000, UL)
> +#define HGATP64_PPN		_AC(0x00000FFFFFFFFFFF, UL)
> +
> +#ifdef CONFIG_64BIT
> +#define HGATP_PPN		HGATP64_PPN
> +#define HGATP_VMID_SHIFT	HGATP64_VMID_SHIFT
> +#define HGATP_VMID_MASK		HGATP64_VMID_MASK
> +#define HGATP_MODE		(HGATP_MODE_SV39X4 << HGATP64_MODE_SHIFT)
> +#else
> +#define HGATP_PPN		HGATP32_PPN
> +#define HGATP_VMID_SHIFT	HGATP32_VMID_SHIFT
> +#define HGATP_VMID_MASK		HGATP32_VMID_MASK
> +#define HGATP_MODE		(HGATP_MODE_SV32X4 << HGATP32_MODE_SHIFT)
> +#endif
> +
> +/* VSIP & HIP relation */
> +#define VSIP_TO_HIP_SHIFT	(IRQ_VS_SOFT - IRQ_S_SOFT)
> +#define VSIP_VALID_MASK		((_AC(1, UL) << IRQ_S_SOFT) | \
> +				 (_AC(1, UL) << IRQ_S_TIMER) | \
> +				 (_AC(1, UL) << IRQ_S_EXT))
>  
>  /* symbolic CSR names: */
>  #define CSR_CYCLE		0xc00
> @@ -91,6 +141,28 @@
>  #define CSR_SIP			0x144
>  #define CSR_SATP		0x180
>  
> +#define CSR_VSSTATUS		0x200
> +#define CSR_VSIE		0x204
> +#define CSR_VSTVEC		0x205
> +#define CSR_VSSCRATCH		0x240
> +#define CSR_VSEPC		0x241
> +#define CSR_VSCAUSE		0x242
> +#define CSR_VSTVAL		0x243
> +#define CSR_VSIP		0x244
> +#define CSR_VSATP		0x280
> +
> +#define CSR_HSTATUS		0x600
> +#define CSR_HEDELEG		0x602
> +#define CSR_HIDELEG		0x603
> +#define CSR_HIE			0x604
> +#define CSR_HTIMEDELTA		0x605
> +#define CSR_HTIMEDELTAH		0x615
> +#define CSR_HCOUNTERNEN		0x606
> +#define CSR_HTVAL		0x643
> +#define CSR_HIP			0x644
> +#define CSR_HTINST		0x64a
> +#define CSR_HGATP		0x680
> +
>  #define CSR_MSTATUS		0x300
>  #define CSR_MISA		0x301
>  #define CSR_MIE			0x304
> -- 
> 2.17.1


  parent reply index

Thread overview: 28+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-12-23 11:35 [PATCH v10 00/19] KVM RISC-V Support Anup Patel
2019-12-23 11:35 ` [PATCH v10 01/19] RISC-V: Export riscv_cpuid_to_hartid_mask() API Anup Patel
2019-12-23 11:35 ` [PATCH v10 02/19] RISC-V: Add bitmap reprensenting ISA features common across CPUs Anup Patel
2019-12-23 11:35 ` [PATCH v10 03/19] RISC-V: Add hypervisor extension related CSR defines Anup Patel
2019-12-23 11:35 ` [PATCH v10 04/19] RISC-V: Add initial skeletal KVM support Anup Patel
2019-12-23 11:35 ` [PATCH v10 05/19] RISC-V: KVM: Implement VCPU create, init and destroy functions Anup Patel
2019-12-23 11:36 ` [PATCH v10 06/19] RISC-V: KVM: Implement VCPU interrupts and requests handling Anup Patel
2019-12-23 11:36 ` [PATCH v10 07/19] RISC-V: KVM: Implement KVM_GET_ONE_REG/KVM_SET_ONE_REG ioctls Anup Patel
2019-12-23 11:36 ` [PATCH v10 08/19] RISC-V: KVM: Implement VCPU world-switch Anup Patel
2019-12-23 11:36 ` [PATCH v10 09/19] RISC-V: KVM: Handle MMIO exits for VCPU Anup Patel
2019-12-23 11:36 ` [PATCH v10 10/19] RISC-V: KVM: Handle WFI " Anup Patel
2019-12-23 11:36 ` [PATCH v10 11/19] RISC-V: KVM: Implement VMID allocator Anup Patel
2019-12-23 11:36 ` [PATCH v10 12/19] RISC-V: KVM: Implement stage2 page table programming Anup Patel
2019-12-23 11:37 ` [PATCH v10 13/19] RISC-V: KVM: Implement MMU notifiers Anup Patel
2019-12-23 11:37 ` [PATCH v10 14/19] RISC-V: KVM: Add timer functionality Anup Patel
2019-12-23 11:37 ` [PATCH v10 15/19] RISC-V: KVM: FP lazy save/restore Anup Patel
2019-12-23 11:37 ` [PATCH v10 16/19] RISC-V: KVM: Implement ONE REG interface for FP registers Anup Patel
2019-12-23 11:37 ` [PATCH v10 17/19] RISC-V: KVM: Add SBI v0.1 support Anup Patel
2019-12-23 11:37 ` [PATCH v10 18/19] RISC-V: KVM: Document RISC-V specific parts of KVM API Anup Patel
2019-12-23 11:37 ` [PATCH v10 19/19] RISC-V: KVM: Add MAINTAINERS entry Anup Patel
2020-01-16  1:45 ` [PATCH v10 00/19] KVM RISC-V Support Palmer Dabbelt
2020-01-16 16:51 ` [PATCH v10 01/19] RISC-V: Export riscv_cpuid_to_hartid_mask() API Palmer Dabbelt
2020-01-16 19:51 ` [PATCH v10 02/19] RISC-V: Add bitmap reprensenting ISA features common across CPUs Palmer Dabbelt
2020-01-17  6:45   ` Anup Patel
2020-01-16 19:51 ` Palmer Dabbelt [this message]
2020-01-17  7:14   ` [PATCH v10 03/19] RISC-V: Add hypervisor extension related CSR defines Anup Patel
2020-01-16 23:37 ` [PATCH v10 04/19] RISC-V: Add initial skeletal KVM support Palmer Dabbelt
2020-01-17  7:11   ` Anup Patel

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