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[76.210.143.223]) by smtp.gmail.com with ESMTPSA id y9sm6217184pfo.135.2020.04.03.08.17.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Apr 2020 08:17:04 -0700 (PDT) Date: Fri, 03 Apr 2020 08:17:04 -0700 (PDT) X-Google-Original-Date: Fri, 03 Apr 2020 08:14:58 PDT (-0700) Subject: Re: [RFC PATCH 2/7] riscv: Allow to dynamically define VA_BITS In-Reply-To: <20200322110028.18279-3-alex@ghiti.fr> From: Palmer Dabbelt To: alex@ghiti.fr Message-ID: Mime-Version: 1.0 (MHng) Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200403_081706_137265_6255032D X-CRM114-Status: GOOD ( 16.38 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex@ghiti.fr, anup@brainfault.org, linux-kernel@vger.kernel.org, zong.li@sifive.com, Paul Walmsley , linux-riscv@lists.infradead.org, Christoph Hellwig Sender: "linux-riscv" Errors-To: linux-riscv-bounces+infradead-linux-riscv=archiver.kernel.org@lists.infradead.org On Sun, 22 Mar 2020 04:00:23 PDT (-0700), alex@ghiti.fr wrote: > With 4-level page table folding at runtime, we don't know at compile time > the size of the virtual address space so we must set VA_BITS dynamically > so that sparsemem reserves the right amount of memory for struct pages. > > Signed-off-by: Alexandre Ghiti > --- > arch/riscv/Kconfig | 10 ---------- > arch/riscv/include/asm/pgtable.h | 10 +++++++++- > arch/riscv/include/asm/sparsemem.h | 2 +- > 3 files changed, 10 insertions(+), 12 deletions(-) > > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig > index f5f3d474504d..8e4b1cbcf2c2 100644 > --- a/arch/riscv/Kconfig > +++ b/arch/riscv/Kconfig > @@ -99,16 +99,6 @@ config ZONE_DMA32 > bool > default y if 64BIT > > -config VA_BITS > - int > - default 32 if 32BIT > - default 39 if 64BIT > - > -config PA_BITS > - int > - default 34 if 32BIT > - default 56 if 64BIT > - > config PAGE_OFFSET > hex > default 0xC0000000 if 32BIT && MAXPHYSMEM_2GB > diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h > index 185ffe3723ec..dce401eed1d3 100644 > --- a/arch/riscv/include/asm/pgtable.h > +++ b/arch/riscv/include/asm/pgtable.h > @@ -26,6 +26,14 @@ > #endif /* CONFIG_64BIT */ > > #ifdef CONFIG_MMU > +#ifdef CONFIG_64BIT > +#define VA_BITS 39 > +#define PA_BITS 56 > +#else > +#define VA_BITS 32 > +#define PA_BITS 34 We've moved to 32-bit physical addresses on rv32 in Linux. The mismatch was causing too many issues in generic code. > +#endif > + > /* Number of entries in the page global directory */ > #define PTRS_PER_PGD (PAGE_SIZE / sizeof(pgd_t)) > /* Number of entries in the page table */ > @@ -108,7 +116,7 @@ extern pgd_t swapper_pg_dir[]; > * position vmemmap directly below the VMALLOC region. > */ > #define VMEMMAP_SHIFT \ > - (CONFIG_VA_BITS - PAGE_SHIFT - 1 + STRUCT_PAGE_MAX_SHIFT) > + (VA_BITS - PAGE_SHIFT - 1 + STRUCT_PAGE_MAX_SHIFT) > #define VMEMMAP_SIZE BIT(VMEMMAP_SHIFT) > #define VMEMMAP_END (VMALLOC_START - 1) > #define VMEMMAP_START (VMALLOC_START - VMEMMAP_SIZE) > diff --git a/arch/riscv/include/asm/sparsemem.h b/arch/riscv/include/asm/sparsemem.h > index 45a7018a8118..f08d72155bc8 100644 > --- a/arch/riscv/include/asm/sparsemem.h > +++ b/arch/riscv/include/asm/sparsemem.h > @@ -4,7 +4,7 @@ > #define _ASM_RISCV_SPARSEMEM_H > > #ifdef CONFIG_SPARSEMEM > -#define MAX_PHYSMEM_BITS CONFIG_PA_BITS > +#define MAX_PHYSMEM_BITS PA_BITS > #define SECTION_SIZE_BITS 27 > #endif /* CONFIG_SPARSEMEM */ Aside from the 32-bit PA issue: Reviewed-by: Palmer Dabbelt