From: Palmer Dabbelt <palmer@sifive.com>
To: atish.patra@wdc.com
Cc: mark.rutland@arm.com, devicetree@vger.kernel.org,
Damien.LeMoal@wdc.com, aou@eecs.berkeley.edu,
dmitriy@oss-tech.org, anup@brainfault.org,
daniel.lezcano@linaro.org, linux-kernel@vger.kernel.org,
atish.patra@wdc.com, robh+dt@kernel.org,
linux-riscv@lists.infradead.org, tglx@linutronix.de
Subject: Re: [PATCH 2/4] RISC-V: Support per-hart timebase-frequency
Date: Fri, 07 Dec 2018 08:42:30 -0800 (PST) [thread overview]
Message-ID: <mhng-531f9ae3-9ab2-48cb-9f1f-4e6814498753@palmer-si-x1c4> (raw)
In-Reply-To: <1543870651-16669-3-git-send-email-atish.patra@wdc.com>
On Mon, 03 Dec 2018 12:57:29 PST (-0800), atish.patra@wdc.com wrote:
> Follow the updated DT specs and read the timebase-frequency
> from the boot cpu. Keep the old DT reading as well for backward
> compatibility. This patch is rework of old patch from Palmer.
>
> Signed-off-by: Atish Patra <atish.patra@wdc.com>
> ---
> arch/riscv/kernel/time.c | 9 +--------
> drivers/clocksource/riscv_timer.c | 22 ++++++++++++++++++++++
> 2 files changed, 23 insertions(+), 8 deletions(-)
>
> diff --git a/arch/riscv/kernel/time.c b/arch/riscv/kernel/time.c
> index 1911c8f6..225fe743 100644
> --- a/arch/riscv/kernel/time.c
> +++ b/arch/riscv/kernel/time.c
> @@ -20,14 +20,7 @@ unsigned long riscv_timebase;
>
> void __init time_init(void)
> {
> - struct device_node *cpu;
> - u32 prop;
> -
> - cpu = of_find_node_by_path("/cpus");
> - if (!cpu || of_property_read_u32(cpu, "timebase-frequency", &prop))
> - panic(KERN_WARNING "RISC-V system with no 'timebase-frequency' in DTS\n");
> - riscv_timebase = prop;
> + timer_probe();
>
> lpj_fine = riscv_timebase / HZ;
> - timer_probe();
> }
> diff --git a/drivers/clocksource/riscv_timer.c b/drivers/clocksource/riscv_timer.c
> index 084e97dc..96af7058 100644
> --- a/drivers/clocksource/riscv_timer.c
> +++ b/drivers/clocksource/riscv_timer.c
> @@ -83,6 +83,26 @@ void riscv_timer_interrupt(void)
> evdev->event_handler(evdev);
> }
>
> +static long __init riscv_timebase_frequency(struct device_node *node)
> +{
> + u32 timebase;
> +
> + if (!of_property_read_u32(node, "timebase-frequency", &timebase))
> + return timebase;
> +
> + /*
> + * As per the DT specification, timebase-frequency should be present
> + * under individual cpu node. Unfortunately, there are already available
> + * HiFive Unleashed devices where the timebase-frequency entry is under
> + * CPUs. check under parent "cpus" node to cover those devices.
> + */
> + if (!of_property_read_u32(node->parent, "timebase-frequency",
> + &timebase))
> + return timebase;
> +
> + panic("RISC-V system with no 'timebase-frequency' in DTS\n");
> +}
> +
> static int __init riscv_timer_init_dt(struct device_node *n)
> {
> int cpuid, hartid, error;
> @@ -94,6 +114,8 @@ static int __init riscv_timer_init_dt(struct device_node *n)
> if (cpuid != smp_processor_id())
> return 0;
>
> + /* This should be called only for boot cpu */
> + riscv_timebase = riscv_timebase_frequency(n);
> cs = per_cpu_ptr(&riscv_clocksource, cpuid);
> clocksource_register_hz(cs, riscv_timebase);
We need to check to make sure the timebase-frequency of each hart is the same.
This is mandated by the RISC-V ISA specification but should be checked in the
code.
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next prev parent reply other threads:[~2018-12-07 16:42 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-12-03 20:57 [PATCH 0/4] Timer code cleanup Atish Patra
2018-12-03 20:57 ` [PATCH 1/4] dt-bindings: Correct RISC-V's timebase-frequency Atish Patra
2018-12-07 16:29 ` Palmer Dabbelt
2018-12-03 20:57 ` [PATCH 2/4] RISC-V: Support per-hart timebase-frequency Atish Patra
2018-12-07 16:42 ` Palmer Dabbelt [this message]
2018-12-07 23:36 ` Atish Patra
2018-12-03 20:57 ` [PATCH 3/4] RISC-V: Remove per cpu clocksource Atish Patra
2018-12-07 17:00 ` Palmer Dabbelt
2018-12-03 20:57 ` [PATCH 4/4] RISC-V: Fix non-smp kernel boot on SMP systems Atish Patra
2018-12-07 17:00 ` Palmer Dabbelt
2018-12-07 23:31 ` Atish Patra
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