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Wed, 07 Aug 2019 09:20:17 -0700 (PDT) Date: Wed, 07 Aug 2019 09:20:17 -0700 (PDT) X-Google-Original-Date: Wed, 07 Aug 2019 09:13:52 PDT (-0700) Subject: Re: [PATCH] riscv: kbuild: add virtual memory system selection In-Reply-To: <20190807151229.GA16432@infradead.org> From: Palmer Dabbelt To: Christoph Hellwig Message-ID: Mime-Version: 1.0 (MHng) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190807_092019_204697_255B908A X-CRM114-Status: GOOD ( 10.50 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Christoph Hellwig , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, alex@ghiti.fr, Paul Walmsley Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-riscv" Errors-To: linux-riscv-bounces+infradead-linux-riscv=archiver.kernel.org@lists.infradead.org On Wed, 07 Aug 2019 08:12:30 PDT (-0700), Christoph Hellwig wrote: > On Wed, Aug 07, 2019 at 09:04:40AM +0200, Alexandre Ghiti wrote: >> I took a look at how x86 deals with 5-level page table: it allows to handle >> 5-level and 4-level at runtime by folding the last page table level (cf >> Documentation/x86/x86_64/5level-paging.rst). So we might want to be able to >> do the same and deal with that at runtime. > > Yes, following the X86_5LEVEL model is the right thing. I poked around a bit with this last night, but our paging implemention is super ugly so it'd be better to clean all that up first. No idea when I'll have time to do so... _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv