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[76.210.143.223]) by smtp.gmail.com with ESMTPSA id y15sm16953995pgi.31.2021.03.09.20.39.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Mar 2021 20:39:18 -0800 (PST) Date: Tue, 09 Mar 2021 20:39:18 -0800 (PST) X-Google-Original-Date: Tue, 09 Mar 2021 20:33:49 PST (-0800) Subject: Re: [RFC patch 0/4] riscv: introduce alternative mechanism to apply errata patches In-Reply-To: <1615175897-23509-1-git-send-email-vincent.chen@sifive.com> CC: linux-riscv@lists.infradead.org, Frank.Zhao@starfivetech.com, Atish Patra , Anup Patel , guoren@kernel.org, alankao@andestech.com, Paul Walmsley , vincent.chen@sifive.com From: Palmer Dabbelt To: vincent.chen@sifive.com Message-ID: Mime-Version: 1.0 (MHng) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210310_043926_455500_9578C3A7 X-CRM114-Status: GOOD ( 32.17 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Sun, 07 Mar 2021 19:58:13 PST (-0800), vincent.chen@sifive.com wrote: > With the emergence of more and more RISC-V CPUs, the request for how to > upstream the vendor errata patch may gradually appear. In order to resolve > this issue, this patch introduces the alternative mechanism from ARM64 and > x86 to enable the kernel to patch code at runtime according to the > manufacturer information of the running CPU. The main purpose of this patch > set is to propose a framework to apply vendor's errata solutions. Based on > this framework, it can be ensured that the errata only applies to the > specified CPU cores. Other CPU cores do not be affected. Therefore, some > complicated scenarios are unsupported in this patch set, such as patching > code to the kernel module, doing relocation in patching code, and > heterogeneous CPU topology. > > In the "alternative" scheme, Users could use the macro ALTERNATIVE to apply > an errata to the existing code flow. In the macro ALTERNATIVE, users need > to specify the manufacturer information (vendor id, arch id, and implement > id) for this errata. Therefore, kernel will know this errata is suitable > for which CPU core. During the booting procedure, kernel will select the > errata required by the CPU core and then patch it. It means that the kernel > only applies the errata to the specified CPU core. In this case, the > vendor's errata does not affect each other at runtime. The above patching > procedure only occurs during the booting phase, so we only take the > overhead of the "alternative" mechanism once. > > This "alternative" mechanism is enabled by default to ensure that all > required errata will be applied. However, users can disable this feature by > the Kconfig "CONFIG_RISCV_ERRATA_ALTERNATIVE". This all generally seems OK to me, though I have a few comments in the actual patches. > > The last patch is to apply the SiFive CIP-453 errata by this "alternative" > scheme. Therefore, It can be regarded as an example. According to the > results of running this image on the QEMU virt platform, kernel does not > apply this errata at run-time because the CPU manufacturer information > does not match the specified SiFive CPU core. Therefore, this errata does > not affect any CPU core except for the specified SiFive cores. Looking at the documentation for that I also saw CIP-1200. That one seems way scarier, and also probably a better driver for building an errata framework as it has more than one caller. Is that in this chip? It's in a document just titled "Errata_FU740-C000_20210205". > > Vincent Chen (4): > riscv: Add 3 SBI wrapper functions to get cpu manufacturer information > riscv: Get CPU manufacturer information > riscv: Introduce alternative mechanism to apply errata solution > riscv: sifive: apply errata "cip-453" patch > > arch/riscv/Kconfig | 1 + > arch/riscv/Kconfig.erratas | 32 ++++++++ > arch/riscv/Kconfig.socs | 1 + > arch/riscv/Makefile | 1 + > arch/riscv/errata/Makefile | 2 + > arch/riscv/errata/alternative.c | 69 +++++++++++++++++ > arch/riscv/errata/sifive/Makefile | 2 + > arch/riscv/errata/sifive/errata.c | 56 ++++++++++++++ > arch/riscv/errata/sifive/errata_cip_453.S | 34 +++++++++ > arch/riscv/include/asm/alternative-macros.h | 110 ++++++++++++++++++++++++++++ > arch/riscv/include/asm/alternative.h | 44 +++++++++++ > arch/riscv/include/asm/asm.h | 1 + > arch/riscv/include/asm/csr.h | 3 + > arch/riscv/include/asm/errata_list.h | 9 +++ > arch/riscv/include/asm/hwcap.h | 6 ++ > arch/riscv/include/asm/processor.h | 2 + > arch/riscv/include/asm/sbi.h | 3 + > arch/riscv/include/asm/sections.h | 2 + > arch/riscv/include/asm/soc.h | 1 + > arch/riscv/include/asm/vendorid_list.h | 6 ++ > arch/riscv/kernel/cpufeature.c | 17 +++++ > arch/riscv/kernel/entry.S | 12 ++- > arch/riscv/kernel/sbi.c | 15 ++++ > arch/riscv/kernel/setup.c | 2 + > arch/riscv/kernel/smpboot.c | 4 + > arch/riscv/kernel/soc.c | 1 + > arch/riscv/kernel/vmlinux.lds.S | 14 ++++ > 27 files changed, 448 insertions(+), 2 deletions(-) > create mode 100644 arch/riscv/Kconfig.erratas > create mode 100644 arch/riscv/errata/Makefile > create mode 100644 arch/riscv/errata/alternative.c > create mode 100644 arch/riscv/errata/sifive/Makefile > create mode 100644 arch/riscv/errata/sifive/errata.c > create mode 100644 arch/riscv/errata/sifive/errata_cip_453.S > create mode 100644 arch/riscv/include/asm/alternative-macros.h > create mode 100644 arch/riscv/include/asm/alternative.h > create mode 100644 arch/riscv/include/asm/errata_list.h > create mode 100644 arch/riscv/include/asm/vendorid_list.h _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv