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Thu, 03 Jan 2019 16:36:22 -0800 (PST) Date: Thu, 03 Jan 2019 16:36:22 -0800 (PST) X-Google-Original-Date: Thu, 03 Jan 2019 16:35:55 PST (-0800) Subject: Re: [PATCH v2 1/4] dt-bindings: Correct RISC-V's timebase-frequency In-Reply-To: <5d652370-4782-23b2-9896-b9666b3cc1e7@linaro.org> From: Palmer Dabbelt To: daniel.lezcano@linaro.org Message-ID: Mime-Version: 1.0 (MHng) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190103_163625_875778_C2E82D44 X-CRM114-Status: GOOD ( 16.18 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.rutland@arm.com, devicetree@vger.kernel.org, Damien.LeMoal@wdc.com, aou@eecs.berkeley.edu, dmitriy@oss-tech.org, anup@brainfault.org, linux-kernel@vger.kernel.org, Christoph Hellwig , atish.patra@wdc.com, robh+dt@kernel.org, tglx@linutronix.de, linux-riscv@lists.infradead.org, Christoph Hellwig Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-riscv" Errors-To: linux-riscv-bounces+infradead-linux-riscv=archiver.kernel.org@lists.infradead.org On Fri, 14 Dec 2018 01:17:24 PST (-0800), daniel.lezcano@linaro.org wrote: > On 14/12/2018 00:14, Atish Patra wrote: >> From: Palmer Dabbelt >> >> In RISC-V systems, timebase-frequency is per cpu instead of one >> instance for entire SOC as there is a individual timer per each CPU. >> Fix the DT binding accordingly. > > Why not use a fixed-clock instead of this timebase property which forces > to declare a global variable to be exported from arch/riscv to > drivers/clocksource ? That makes sense to me. I've always disliked this global variable and a big part of why my original version got delayed forever is that I'd hoped to get rid of it. Given that this is all a mess anyway I'm OK breaking backwards compatibility here. Is there an example of how to do this? > In addition, please add the 'Fixes' tag > >> Signed-off-by: Palmer Dabbelt >> Signed-off-by: Christoph Hellwig >> [Atish: Update the commit text] >> Signed-off-by: Atish Patra >> Reviewed-by: Rob Herring >> --- >> Documentation/devicetree/bindings/riscv/cpus.txt | 4 +++- >> 1 file changed, 3 insertions(+), 1 deletion(-) >> >> diff --git a/Documentation/devicetree/bindings/riscv/cpus.txt b/Documentation/devicetree/bindings/riscv/cpus.txt >> index adf7b7af..b0b038d6 100644 >> --- a/Documentation/devicetree/bindings/riscv/cpus.txt >> +++ b/Documentation/devicetree/bindings/riscv/cpus.txt >> @@ -93,9 +93,9 @@ Linux is allowed to run on. >> cpus { >> #address-cells = <1>; >> #size-cells = <0>; >> - timebase-frequency = <1000000>; >> cpu@0 { >> clock-frequency = <1600000000>; >> + timebase-frequency = <1000000>; >> compatible = "sifive,rocket0", "riscv"; >> device_type = "cpu"; >> i-cache-block-size = <64>; >> @@ -113,6 +113,7 @@ Linux is allowed to run on. >> }; >> cpu@1 { >> clock-frequency = <1600000000>; >> + timebase-frequency = <1000000>; >> compatible = "sifive,rocket0", "riscv"; >> d-cache-block-size = <64>; >> d-cache-sets = <64>; >> @@ -145,6 +146,7 @@ Example: Spike ISA Simulator with 1 Hart >> This device tree matches the Spike ISA golden model as run with `spike -p1`. >> >> cpus { >> + timebase-frequency = <1000000>; >> cpu@0 { >> device_type = "cpu"; >> reg = <0x00000000>; _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv