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From: Palmer Dabbelt <palmer@sifive.com>
To: anup@brainfault.org
Cc: aou@eecs.berkeley.edu, jason@lakedaemon.net,
	marc.zyngier@arm.com, daniel.lezcano@linaro.org,
	linux-kernel@vger.kernel.org,
	Christoph Hellwig <hch@infradead.org>,
	atish.patra@wdc.com, tglx@linutronix.de,
	linux-riscv@lists.infradead.org
Subject: Re: [PATCH v3 0/6] IRQ affinity support in PLIC driver
Date: Thu, 20 Dec 2018 12:40:35 -0800 (PST)
Message-ID: <mhng-b072b061-91a6-40d3-a8a0-baf39cb7c33c@palmer-si-x1c4> (raw)
In-Reply-To: <CAAhSdy0t9H4VMSpoZy1Xt2caW_BxOfEA-x-QhnMsbzXned6AUA@mail.gmail.com>

On Mon, 17 Dec 2018 01:37:58 PST (-0800), anup@brainfault.org wrote:
> On Fri, Nov 30, 2018 at 1:32 PM Anup Patel <anup@brainfault.org> wrote:
>>
>> This patchset primarily adds IRQ affinity support in PLIC driver and
>> other improvements.
>>
>> The patchset gives mechanism for explicitly routing external interrupts to
>> particular CPUs using smp_affinity attribute of each Linux IRQs. Also, we
>> can now use IRQ balancer from kernel-space or user-space.
>>
>> The patchset is tested on QEMU virt machine. It is based on Linux-4.20-rc4
>> and can be found at riscv_plic_irq_affinity_v3 branch of:
>> https://github.com/avpatel/linux.git
>>
>> Changes since v2:
>>  - Fixed incorrect address of enable registers using sizeof(u32) in PATCH1
>>  - Retained comment about need for locking in PATCH1
>>  - Split PATCH2 into two patches
>>  - Split PATCH3 into two patches
>>  - Minor fix in commit description of PATCH4
>>
>> Changes since v1:
>>  - Removed few whitspace changes from PATCH1
>>  - Keep use of DEFINE_PER_CPU() as it is
>>
>> Anup Patel (6):
>>   irqchip: sifive-plic: Pre-compute context hart base and enable base
>>   irqchip: sifive-plic: Add struct plic_hw for global PLIC HW details
>>   irqchip: sifive-plic: More flexible plic_irq_toggle()
>>   irqchip: sifive-plic: Add warning in plic_init() if handler already
>>     present
>>   irqchip: sifive-plic: Differentiate between PLIC handler and context
>>   irqchip: sifive-plic: Implement irq_set_affinity() for SMP host
>>
>>  drivers/irqchip/irq-sifive-plic.c | 143 +++++++++++++++++++-----------
>>  1 file changed, 90 insertions(+), 53 deletions(-)
>>
>> --
>> 2.17.1
>>
>
> Any comments on this series?

I also haven't had a chance to look at these yet.

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Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-11-30  8:02 Anup Patel
2018-11-30  8:02 ` [PATCH v3 1/6] irqchip: sifive-plic: Pre-compute context hart base and enable base Anup Patel
2018-12-17 18:25   ` Christoph Hellwig
2018-12-18  8:30     ` Anup Patel
2018-11-30  8:02 ` [PATCH v3 2/6] irqchip: sifive-plic: Add struct plic_hw for global PLIC HW details Anup Patel
2018-12-17 18:24   ` Christoph Hellwig
2018-12-18  8:25     ` Anup Patel
2018-11-30  8:02 ` [PATCH v3 3/6] irqchip: sifive-plic: More flexible plic_irq_toggle() Anup Patel
2018-12-17 18:27   ` Christoph Hellwig
2018-12-18  8:50     ` Anup Patel
2018-12-19 16:28       ` Christoph Hellwig
2018-12-27  5:27         ` Anup Patel
2018-11-30  8:02 ` [PATCH v3 4/6] irqchip: sifive-plic: Add warning in plic_init() if handler already present Anup Patel
2018-12-17 18:28   ` Christoph Hellwig
2018-12-18  8:36     ` Anup Patel
2018-11-30  8:02 ` [PATCH v3 5/6] irqchip: sifive-plic: Differentiate between PLIC handler and context Anup Patel
2018-11-30  8:02 ` [PATCH v3 6/6] irqchip: sifive-plic: Implement irq_set_affinity() for SMP host Anup Patel
2018-12-17 18:32   ` Christoph Hellwig
2018-12-18 10:32     ` Anup Patel
2018-12-17  9:37 ` [PATCH v3 0/6] IRQ affinity support in PLIC driver Anup Patel
2018-12-20 20:40   ` Palmer Dabbelt [this message]

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