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[203.116.164.13]) by smtp.gmail.com with ESMTPSA id s73sm2940942pjb.15.2019.09.13.14.20.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Sep 2019 14:20:53 -0700 (PDT) Date: Fri, 13 Sep 2019 14:20:53 -0700 (PDT) X-Google-Original-Date: Fri, 13 Sep 2019 14:18:36 PDT (-0700) Subject: Re: [PATCH] riscv: dts: Add DT support for SiFive FU540 PWM driver In-Reply-To: From: Palmer Dabbelt To: yash.shah@sifive.com Message-ID: Mime-Version: 1.0 (MHng) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190913_142055_334104_C7D44C4F X-CRM114-Status: GOOD ( 13.81 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.rutland@arm.com, devicetree@vger.kernel.org, aou@eecs.berkeley.edu, linux-kernel@vger.kernel.org, Sachin Ghadi , robh+dt@kernel.org, sagar.kadam@sifive.com, Paul Walmsley , linux-riscv@lists.infradead.org, bmeng.cn@gmail.com Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-riscv" Errors-To: linux-riscv-bounces+infradead-linux-riscv=archiver.kernel.org@lists.infradead.org On Tue, 10 Sep 2019 02:52:07 PDT (-0700), yash.shah@sifive.com wrote: > Hi, > > Any comments on this patch? I don't see "sifive,pwm0" in the DT bindings documentation, and it doesn't match our standard way of doing these things (which would have at least "sifive,fu540-c000-pwm"). > > - Yash > > On Wed, Aug 21, 2019 at 2:53 PM Yash Shah wrote: >> >> Add the PWM DT node in SiFive FU540 soc-specific DT file. >> Enable the PWM nodes in HiFive Unleashed board-specific DT file. >> >> Signed-off-by: Yash Shah >> --- >> arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 19 +++++++++++++++++++ >> arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts | 8 ++++++++ >> 2 files changed, 27 insertions(+) >> >> diff --git a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi >> index 42b5ec2..bb422db 100644 >> --- a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi >> +++ b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi >> @@ -230,6 +230,25 @@ >> #size-cells = <0>; >> status = "disabled"; >> }; >> + pwm0: pwm@10020000 { >> + compatible = "sifive,pwm0"; >> + reg = <0x0 0x10020000 0x0 0x1000>; >> + interrupt-parent = <&plic0>; >> + interrupts = <42 43 44 45>; >> + clocks = <&prci PRCI_CLK_TLCLK>; >> + #pwm-cells = <3>; >> + status = "disabled"; >> + }; >> + pwm1: pwm@10021000 { >> + compatible = "sifive,pwm0"; >> + reg = <0x0 0x10021000 0x0 0x1000>; >> + interrupt-parent = <&plic0>; >> + interrupts = <46 47 48 49>; >> + reg-names = "control"; >> + clocks = <&prci PRCI_CLK_TLCLK>; >> + #pwm-cells = <3>; >> + status = "disabled"; >> + }; >> >> }; >> }; >> diff --git a/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts b/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts >> index 93d68cb..104d334 100644 >> --- a/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts >> +++ b/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts >> @@ -85,3 +85,11 @@ >> reg = <0>; >> }; >> }; >> + >> +&pwm0 { >> + status = "okay"; >> +}; >> + >> +&pwm1 { >> + status = "okay"; >> +}; >> -- >> 1.9.1 >> _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv