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Mon, 12 Jun 2023 08:29:49 -0700 (PDT) Date: Mon, 12 Jun 2023 08:29:49 -0700 (PDT) X-Google-Original-Date: Mon, 12 Jun 2023 08:29:45 PDT (-0700) Subject: Re: [PATCH RFC 0/2] RISC-V: T-Head vector handling In-Reply-To: CC: linux-riscv@lists.infradead.org, samuel@sholland.org, christoph.muellner@vrull.eu, heiko@sntech.de, Conor Dooley , linux-kernel@vger.kernel.org, heiko.stuebner@vrull.eu From: Palmer Dabbelt To: heiko@sntech.de, guoren@kernel.org Message-ID: Mime-Version: 1.0 (MHng) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230612_082953_401364_27AE9558 X-CRM114-Status: GOOD ( 22.00 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Tue, 14 Mar 2023 22:29:41 PDT (-0700), Palmer Dabbelt wrote: > On Tue, 28 Feb 2023 13:54:33 PST (-0800), heiko@sntech.de wrote: >> From: Heiko Stuebner >> >> As is widely known the T-Head C9xx cores used for example in the >> Allwinner D1 implement an older non-ratified variant of the vector spec. >> >> While userspace will probably have a lot more problems implementing >> support for both, on the kernel side the needed changes are actually >> somewhat small'ish and can be handled via alternatives somewhat nicely. >> >> With this patchset I could run the same userspace program (picked from >> some riscv-vector-test repository) that does some vector additions on >> both qemu and a d1-nezha board. On both platforms it ran sucessfully and >> even produced the same results. >> >> >> As can be seen in the todo list, there are 2 places where the changed >> SR_VS location still needs to be handled in the next revision >> (assembly + ALTERNATIVES + constants + probably stringify resulted in >> some grey hair so far already) >> >> >> ToDo: >> - follow along with the base vector patchset >> - handle SR_VS access in _save_context and _secondary_start_sbi >> >> >> Heiko Stuebner (2): >> RISC-V: define the elements of the VCSR vector CSR >> RISC-V: add T-Head vector errata handling >> >> arch/riscv/Kconfig.erratas | 13 +++ >> arch/riscv/errata/thead/errata.c | 32 ++++++ >> arch/riscv/include/asm/csr.h | 31 +++++- >> arch/riscv/include/asm/errata_list.h | 62 +++++++++++- >> arch/riscv/include/asm/vector.h | 139 +++++++++++++++++++++++++-- >> 5 files changed, 261 insertions(+), 16 deletions(-) > > I have no opposition to calling the T-Head vector stuff an errata > against V, the RISC-V folks have already made it quite apparent that > anything goes here. I would like to get the standard V uABI sorted out > first, though, as there's still a lot of moving pieces there. It's kind > of hard here as T-Head got thrown under the bus, but I'm not sure what > else to do about it. The V-1.0 support has been merged, so I think we're good to go. Does someone mind re-spinning this against for-next so it lines up with all the new user interfaces? _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv