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From: Palmer Dabbelt <palmer@sifive.com>
To: atish.patra@wdc.com
Cc: aou@eecs.berkeley.edu, anup@brainfault.org,
	linux-kernel@vger.kernel.org, zong@andestech.com,
	atish.patra@wdc.com, linux-riscv@lists.infradead.org
Subject: Re: [PATCH] RISC-V: Add an Image header that boot loader can parse.
Date: Mon, 29 Apr 2019 16:40:36 -0700 (PDT)	[thread overview]
Message-ID: <mhng-cab2c6b9-f623-4286-99a4-61e4b3a58761@palmer-si-x1e> (raw)
In-Reply-To: <20190423232506.857-1-atish.patra@wdc.com>

On Tue, 23 Apr 2019 16:25:06 PDT (-0700), atish.patra@wdc.com wrote:
> Currently, last stage boot loaders such as U-Boot can accept only
> uImage which is an unnecessary additional step in automating boot flows.
>
> Add a simple image header that boot loaders can parse and directly
> load kernel flat Image. The existing booting methods will continue to
> work as it is.
>
> Tested on both QEMU and HiFive Unleashed using OpenSBI + U-Boot + Linux.
>
> Signed-off-by: Atish Patra <atish.patra@wdc.com>
> ---
>  arch/riscv/include/asm/image.h | 32 ++++++++++++++++++++++++++++++++
>  arch/riscv/kernel/head.S       | 28 ++++++++++++++++++++++++++++
>  2 files changed, 60 insertions(+)
>  create mode 100644 arch/riscv/include/asm/image.h
>
> diff --git a/arch/riscv/include/asm/image.h b/arch/riscv/include/asm/image.h
> new file mode 100644
> index 000000000000..76a7e0d4068a
> --- /dev/null
> +++ b/arch/riscv/include/asm/image.h
> @@ -0,0 +1,32 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +
> +#ifndef __ASM_IMAGE_H
> +#define __ASM_IMAGE_H
> +
> +#define RISCV_IMAGE_MAGIC	"RISCV"
> +
> +#ifndef __ASSEMBLY__
> +/*
> + * struct riscv_image_header - riscv kernel image header
> + *
> + * @code0:		Executable code
> + * @code1:		Executable code
> + * @text_offset:	Image load offset
> + * @image_size:		Effective Image size
> + * @reserved:		reserved
> + * @magic:		Magic number
> + * @reserved:		reserved
> + */
> +
> +struct riscv_image_header {
> +	u32 code0;
> +	u32 code1;
> +	u64 text_offset;
> +	u64 image_size;
> +	u64 res1;
> +	u64 magic;
> +	u32 res2;
> +	u32 res3;
> +};

I don't want to invent our own file format.  Is there a reason we can't just
use something standard?  Off the top of my head I can think of ELF files and
multiboot.

> +#endif /* __ASSEMBLY__ */
> +#endif /* __ASM_IMAGE_H */
> diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S
> index fe884cd69abd..154647395601 100644
> --- a/arch/riscv/kernel/head.S
> +++ b/arch/riscv/kernel/head.S
> @@ -19,9 +19,37 @@
>  #include <asm/thread_info.h>
>  #include <asm/page.h>
>  #include <asm/csr.h>
> +#include <asm/image.h>
>
>  __INIT
>  ENTRY(_start)
> +	/*
> +	 * Image header expected by Linux boot-loaders. The image header data
> +	 * structure is described in asm/image.h.
> +	 * Do not modify it without modifying the structure and all bootloaders
> +	 * that expects this header format!!
> +	 */
> +	/* jump to start kernel */
> +	j _start_kernel
> +	/* reserved */
> +	.word 0
> +	.balign 8
> +#if __riscv_xlen == 64
> +	/* Image load offset(2MB) from start of RAM */
> +	.dword 0x200000
> +#else
> +	/* Image load offset(4MB) from start of RAM */
> +	.dword 0x400000
> +#endif
> +	/* Effective size of kernel image */
> +	.dword _end - _start
> +	.dword 0
> +	.asciz RISCV_IMAGE_MAGIC
> +	.word 0
> +	.word 0
> +
> +.global _start_kernel
> +_start_kernel:
>  	/* Mask all interrupts */
>  	csrw sie, zero

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  reply	other threads:[~2019-04-29 23:40 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-04-23 23:25 [PATCH] RISC-V: Add an Image header that boot loader can parse Atish Patra
2019-04-29 23:40 ` Palmer Dabbelt [this message]
2019-04-30  5:42   ` Atish Patra
2019-05-01 16:43     ` Karsten Merker
2019-05-01 17:02       ` Anup Patel
2019-05-01 17:32         ` Atish Patra
2019-05-01 17:00     ` Mark Rutland
2019-05-01 17:11       ` Anup Patel
2019-05-01 17:35         ` Mark Rutland
2019-05-01 19:54         ` Karsten Merker
2019-05-01 20:32           ` Karsten Merker

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