From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jonas Karlman Subject: [PATCH v2 08/14] clk: rockchip: set parent rate for DCLK_VOP clock on rk3228 Date: Wed, 08 Jan 2020 21:07:50 +0000 (UTC) Message-ID: <20200108210740.28769-9-jonas@kwiboo.se> References: <20200108210740.28769-1-jonas@kwiboo.se> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <20200108210740.28769-1-jonas@kwiboo.se> Sender: linux-kernel-owner@vger.kernel.org To: Heiko Stuebner , Sandy Huang Cc: Jonas Karlman , Kishon Vijay Abraham I , Zheng Yang , linux-rockchip@lists.infradead.org, dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org List-Id: linux-rockchip.vger.kernel.org Signed-off-by: Jonas Karlman --- drivers/clk/rockchip/clk-rk3228.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/rockchip/clk-rk3228.c b/drivers/clk/rockchip/clk-rk3228.c index d17cfb7a3ff4..25f79af22cb8 100644 --- a/drivers/clk/rockchip/clk-rk3228.c +++ b/drivers/clk/rockchip/clk-rk3228.c @@ -410,7 +410,7 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = { RK2928_CLKSEL_CON(29), 0, 3, DFLAGS), DIV(0, "sclk_vop_pre", "sclk_vop_src", 0, RK2928_CLKSEL_CON(27), 8, 8, DFLAGS), - MUX(DCLK_VOP, "dclk_vop", mux_dclk_vop_p, 0, + MUX(DCLK_VOP, "dclk_vop", mux_dclk_vop_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, RK2928_CLKSEL_CON(27), 1, 1, MFLAGS), FACTOR(0, "xin12m", "xin24m", 0, 1, 2), -- 2.17.1