From: Adrian Ratiu <adrian.ratiu@collabora.com>
To: Ezequiel Garcia <ezequiel@collabora.com>,
Philipp Zabel <p.zabel@pengutronix.de>
Cc: Fruehberger Peter <Peter.Fruehberger@de.bosch.com>,
Mauro Carvalho Chehab <mchehab@kernel.org>,
linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org,
Mark Brown <broonie@kernel.org>,
kuhanh.murugasen.krishnan@intel.com,
Daniel Vetter <daniel@ffwll.ch>,
kernel@collabora.com, linux-media@vger.kernel.org
Subject: [PATCH 02/18] media: hantro: make consistent use of decimal register notation
Date: Mon, 12 Oct 2020 23:59:41 +0300 [thread overview]
Message-ID: <20201012205957.889185-3-adrian.ratiu@collabora.com> (raw)
In-Reply-To: <20201012205957.889185-1-adrian.ratiu@collabora.com>
This header used a combination of direct hex offsets and decimal register
notation - via the G1_SWREG() macro - which is annoying when comparing with
the ref manuals which always use the equivalent of G1_SWREG(), so convert
the entire file to G1_SWREG() notation.
Signed-off-by: Adrian Ratiu <adrian.ratiu@collabora.com>
---
drivers/staging/media/hantro/hantro_g1_regs.h | 52 +++++++++----------
1 file changed, 26 insertions(+), 26 deletions(-)
diff --git a/drivers/staging/media/hantro/hantro_g1_regs.h b/drivers/staging/media/hantro/hantro_g1_regs.h
index 80ff297f6f68..073b64cbe295 100644
--- a/drivers/staging/media/hantro/hantro_g1_regs.h
+++ b/drivers/staging/media/hantro/hantro_g1_regs.h
@@ -9,10 +9,10 @@
#ifndef HANTRO_G1_REGS_H_
#define HANTRO_G1_REGS_H_
-#define G1_SWREG(nr) ((nr) * 4)
+#define G1_SWREG(nr) ((nr) * 4)
/* Decoder registers. */
-#define G1_REG_INTERRUPT 0x004
+#define G1_REG_INTERRUPT G1_SWREG(1)
/* Interrupt bits. Some are present in:
* - all core versions (">= g1")
* - g1, missing in g2, but added back starting with vc8000d ("not in g2")
@@ -41,7 +41,7 @@
#define G1_REG_INTERRUPT_DEC_BUS_INT_DIS BIT(2) /* >= vc8000d */
#define G1_REG_INTERRUPT_DEC_STRM_CORRUPTED BIT(1) /* >= vc8000d */
#define G1_REG_INTERRUPT_DEC_E BIT(0) /* >= g1 */
-#define G1_REG_CONFIG 0x008
+#define G1_REG_CONFIG G1_SWREG(2)
#define G1_REG_CONFIG_DEC_AXI_RD_ID(x) (((x) & 0xff) << 24)
#define G1_REG_CONFIG_DEC_TIMEOUT_E BIT(23)
#define G1_REG_CONFIG_DEC_STRSWAP32_E BIT(22)
@@ -60,7 +60,7 @@
#define G1_REG_CONFIG_DEC_ADV_PRE_DIS BIT(6)
#define G1_REG_CONFIG_DEC_SCMD_DIS BIT(5)
#define G1_REG_CONFIG_DEC_MAX_BURST(x) (((x) & 0x1f) << 0)
-#define G1_REG_DEC_CTRL0 0x00c
+#define G1_REG_DEC_CTRL0 G1_SWREG(3)
#define G1_REG_DEC_CTRL0_DEC_MODE(x) (((x) & 0xf) << 28)
#define G1_REG_DEC_CTRL0_RLC_MODE_E BIT(27)
#define G1_REG_DEC_CTRL0_SKIP_MODE BIT(26)
@@ -85,7 +85,7 @@
#define G1_REG_DEC_CTRL0_PICORD_COUNT_E BIT(9)
#define G1_REG_DEC_CTRL0_DEC_AHB_HLOCK_E BIT(8)
#define G1_REG_DEC_CTRL0_DEC_AXI_WR_ID(x) (((x) & 0xff) << 0)
-#define G1_REG_DEC_CTRL1 0x010
+#define G1_REG_DEC_CTRL1 G1_SWREG(4)
#define G1_REG_DEC_CTRL1_PIC_MB_WIDTH(x) (((x) & 0x1ff) << 23)
#define G1_REG_DEC_CTRL1_MB_WIDTH_OFF(x) (((x) & 0xf) << 19)
#define G1_REG_DEC_CTRL1_PIC_MB_HEIGHT_P(x) (((x) & 0xff) << 11)
@@ -96,7 +96,7 @@
#define G1_REG_DEC_CTRL1_PIC_MB_W_EXT(x) (((x) & 0x7) << 3)
#define G1_REG_DEC_CTRL1_PIC_MB_H_EXT(x) (((x) & 0x7) << 0)
#define G1_REG_DEC_CTRL1_PIC_REFER_FLAG BIT(0)
-#define G1_REG_DEC_CTRL2 0x014
+#define G1_REG_DEC_CTRL2 G1_SWREG(5)
#define G1_REG_DEC_CTRL2_STRM_START_BIT(x) (((x) & 0x3f) << 26)
#define G1_REG_DEC_CTRL2_SYNC_MARKER_E BIT(25)
#define G1_REG_DEC_CTRL2_TYPE1_QUANT_E BIT(24)
@@ -139,13 +139,13 @@
#define G1_REG_DEC_CTRL2_BOOLEAN_RANGE(x) (((x) & 0xff) << 0)
#define G1_REG_DEC_CTRL2_ALPHA_OFFSET(x) (((x) & 0x1f) << 5)
#define G1_REG_DEC_CTRL2_BETA_OFFSET(x) (((x) & 0x1f) << 0)
-#define G1_REG_DEC_CTRL3 0x018
+#define G1_REG_DEC_CTRL3 G1_SWREG(6)
#define G1_REG_DEC_CTRL3_START_CODE_E BIT(31)
#define G1_REG_DEC_CTRL3_INIT_QP(x) (((x) & 0x3f) << 25)
#define G1_REG_DEC_CTRL3_CH_8PIX_ILEAV_E BIT(24)
#define G1_REG_DEC_CTRL3_STREAM_LEN_EXT(x) (((x) & 0xff) << 24)
#define G1_REG_DEC_CTRL3_STREAM_LEN(x) (((x) & 0xffffff) << 0)
-#define G1_REG_DEC_CTRL4 0x01c
+#define G1_REG_DEC_CTRL4 G1_SWREG(7)
#define G1_REG_DEC_CTRL4_CABAC_E BIT(31)
#define G1_REG_DEC_CTRL4_BLACKWHITE_E BIT(30)
#define G1_REG_DEC_CTRL4_DIR_8X8_INFER_E BIT(29)
@@ -182,7 +182,7 @@
#define G1_REG_DEC_CTRL4_INIT_DC_MATCH0(x) (((x) & 0x7) << 9)
#define G1_REG_DEC_CTRL4_INIT_DC_MATCH1(x) (((x) & 0x7) << 6)
#define G1_REG_DEC_CTRL4_VP7_VERSION BIT(5)
-#define G1_REG_DEC_CTRL5 0x020
+#define G1_REG_DEC_CTRL5 G1_SWREG(8)
#define G1_REG_DEC_CTRL5_CONST_INTRA_E BIT(31)
#define G1_REG_DEC_CTRL5_FILT_CTRL_PRES BIT(30)
#define G1_REG_DEC_CTRL5_RDPIC_CNT_PRES BIT(29)
@@ -206,7 +206,7 @@
#define G1_REG_DEC_CTRL5_RV_BWD_SCALE(x) (((x) & 0x3fff) << 0)
#define G1_REG_DEC_CTRL5_INIT_DC_COMP0(x) (((x) & 0xffff) << 16)
#define G1_REG_DEC_CTRL5_INIT_DC_COMP1(x) (((x) & 0xffff) << 0)
-#define G1_REG_DEC_CTRL6 0x024
+#define G1_REG_DEC_CTRL6 G1_SWREG(9)
#define G1_REG_DEC_CTRL6_PPS_ID(x) (((x) & 0xff) << 24)
#define G1_REG_DEC_CTRL6_REFIDX1_ACTIVE(x) (((x) & 0x1f) << 19)
#define G1_REG_DEC_CTRL6_REFIDX0_ACTIVE(x) (((x) & 0x1f) << 14)
@@ -217,7 +217,7 @@
#define G1_REG_DEC_CTRL6_STREAM1_LEN(x) (((x) & 0xffffff) << 0)
#define G1_REG_DEC_CTRL6_PIC_SLICE_AM(x) (((x) & 0x1fff) << 0)
#define G1_REG_DEC_CTRL6_COEFFS_PART_AM(x) (((x) & 0xf) << 24)
-#define G1_REG_FWD_PIC(i) (0x028 + ((i) * 0x4))
+#define G1_REG_FWD_PIC(i) (G1_SWREG(10) + ((i) * 0x4))
#define G1_REG_FWD_PIC_PINIT_RLIST_F5(x) (((x) & 0x1f) << 25)
#define G1_REG_FWD_PIC_PINIT_RLIST_F4(x) (((x) & 0x1f) << 20)
#define G1_REG_FWD_PIC_PINIT_RLIST_F3(x) (((x) & 0x1f) << 15)
@@ -230,7 +230,7 @@
#define G1_REG_FWD_PIC1_SEGMENT_BASE(x) ((x) << 0)
#define G1_REG_FWD_PIC1_SEGMENT_UPD_E BIT(1)
#define G1_REG_FWD_PIC1_SEGMENT_E BIT(0)
-#define G1_REG_DEC_CTRL7 0x02c
+#define G1_REG_DEC_CTRL7 G1_SWREG(11)
#define G1_REG_DEC_CTRL7_PINIT_RLIST_F15(x) (((x) & 0x1f) << 25)
#define G1_REG_DEC_CTRL7_PINIT_RLIST_F14(x) (((x) & 0x1f) << 20)
#define G1_REG_DEC_CTRL7_PINIT_RLIST_F13(x) (((x) & 0x1f) << 15)
@@ -245,12 +245,12 @@
#define G1_REG_DEC_CTRL7_DCT5_START_BIT(x) (((x) & 0x3f) << 12)
#define G1_REG_DEC_CTRL7_DCT6_START_BIT(x) (((x) & 0x3f) << 6)
#define G1_REG_DEC_CTRL7_DCT7_START_BIT(x) (((x) & 0x3f) << 0)
-#define G1_REG_ADDR_STR 0x030
-#define G1_REG_ADDR_DST 0x034
-#define G1_REG_ADDR_REF(i) (0x038 + ((i) * 0x4))
+#define G1_REG_ADDR_STR G1_SWREG(12)
+#define G1_REG_ADDR_DST G1_SWREG(13)
+#define G1_REG_ADDR_REF(i) (G1_SWREG(14) + ((i) * 0x4))
#define G1_REG_ADDR_REF_FIELD_E BIT(1)
#define G1_REG_ADDR_REF_TOPC_E BIT(0)
-#define G1_REG_REF_PIC(i) (0x078 + ((i) * 0x4))
+#define G1_REG_REF_PIC(i) (G1_SWREG(30) + ((i) * 0x4))
#define G1_REG_REF_PIC_FILT_TYPE_E BIT(31)
#define G1_REG_REF_PIC_FILT_SHARPNESS(x) (((x) & 0x7) << 28)
#define G1_REG_REF_PIC_MB_ADJ_0(x) (((x) & 0x7f) << 21)
@@ -267,11 +267,11 @@
#define G1_REG_REF_PIC_QUANT_DELTA_1(x) (((x) & 0x1f) << 22)
#define G1_REG_REF_PIC_QUANT_0(x) (((x) & 0x7ff) << 11)
#define G1_REG_REF_PIC_QUANT_1(x) (((x) & 0x7ff) << 0)
-#define G1_REG_LT_REF 0x098
-#define G1_REG_VALID_REF 0x09c
-#define G1_REG_ADDR_QTABLE 0x0a0
-#define G1_REG_ADDR_DIR_MV 0x0a4
-#define G1_REG_BD_REF_PIC(i) (0x0a8 + ((i) * 0x4))
+#define G1_REG_LT_REF G1_SWREG(38)
+#define G1_REG_VALID_REF G1_SWREG(39)
+#define G1_REG_ADDR_QTABLE G1_SWREG(40)
+#define G1_REG_ADDR_DIR_MV G1_SWREG(41)
+#define G1_REG_BD_REF_PIC(i) (G1_SWREG(42) + ((i) * 0x4))
#define G1_REG_BD_REF_PIC_BINIT_RLIST_B2(x) (((x) & 0x1f) << 25)
#define G1_REG_BD_REF_PIC_BINIT_RLIST_F2(x) (((x) & 0x1f) << 20)
#define G1_REG_BD_REF_PIC_BINIT_RLIST_B1(x) (((x) & 0x1f) << 15)
@@ -288,7 +288,7 @@
#define G1_REG_BD_REF_PIC_QUANT_DELTA_3(x) (((x) & 0x1f) << 22)
#define G1_REG_BD_REF_PIC_QUANT_2(x) (((x) & 0x7ff) << 11)
#define G1_REG_BD_REF_PIC_QUANT_3(x) (((x) & 0x7ff) << 0)
-#define G1_REG_BD_P_REF_PIC 0x0bc
+#define G1_REG_BD_P_REF_PIC G1_SWREG(47)
#define G1_REG_BD_P_REF_PIC_QUANT_DELTA_4(x) (((x) & 0x1f) << 27)
#define G1_REG_BD_P_REF_PIC_PINIT_RLIST_F3(x) (((x) & 0x1f) << 25)
#define G1_REG_BD_P_REF_PIC_PINIT_RLIST_F2(x) (((x) & 0x1f) << 20)
@@ -296,21 +296,21 @@
#define G1_REG_BD_P_REF_PIC_PINIT_RLIST_F0(x) (((x) & 0x1f) << 10)
#define G1_REG_BD_P_REF_PIC_BINIT_RLIST_B15(x) (((x) & 0x1f) << 5)
#define G1_REG_BD_P_REF_PIC_BINIT_RLIST_F15(x) (((x) & 0x1f) << 0)
-#define G1_REG_ERR_CONC 0x0c0
+#define G1_REG_ERR_CONC G1_SWREG(48)
#define G1_REG_ERR_CONC_STARTMB_X(x) (((x) & 0x1ff) << 23)
#define G1_REG_ERR_CONC_STARTMB_Y(x) (((x) & 0xff) << 15)
-#define G1_REG_PRED_FLT 0x0c4
+#define G1_REG_PRED_FLT G1_SWREG(49)
#define G1_REG_PRED_FLT_PRED_BC_TAP_0_0(x) (((x) & 0x3ff) << 22)
#define G1_REG_PRED_FLT_PRED_BC_TAP_0_1(x) (((x) & 0x3ff) << 12)
#define G1_REG_PRED_FLT_PRED_BC_TAP_0_2(x) (((x) & 0x3ff) << 2)
-#define G1_REG_REF_BUF_CTRL 0x0cc
+#define G1_REG_REF_BUF_CTRL G1_SWREG(51)
#define G1_REG_REF_BUF_CTRL_REFBU_E BIT(31)
#define G1_REG_REF_BUF_CTRL_REFBU_THR(x) (((x) & 0xfff) << 19)
#define G1_REG_REF_BUF_CTRL_REFBU_PICID(x) (((x) & 0x1f) << 14)
#define G1_REG_REF_BUF_CTRL_REFBU_EVAL_E BIT(13)
#define G1_REG_REF_BUF_CTRL_REFBU_FPARMOD_E BIT(12)
#define G1_REG_REF_BUF_CTRL_REFBU_Y_OFFSET(x) (((x) & 0x1ff) << 0)
-#define G1_REG_REF_BUF_CTRL2 0x0dc
+#define G1_REG_REF_BUF_CTRL2 G1_SWREG(55)
#define G1_REG_REF_BUF_CTRL2_REFBU2_BUF_E BIT(31)
#define G1_REG_REF_BUF_CTRL2_REFBU2_THR(x) (((x) & 0xfff) << 19)
#define G1_REG_REF_BUF_CTRL2_REFBU2_PICID(x) (((x) & 0x1f) << 14)
--
2.28.0
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next prev parent reply other threads:[~2020-10-12 21:20 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-10-12 20:59 [PATCH 00/18] Add Hantro regmap and VC8000 h264 decode support Adrian Ratiu
2020-10-12 20:59 ` [PATCH 01/18] media: hantro: document all int reg bits up to vc8000 Adrian Ratiu
2020-10-12 20:59 ` Adrian Ratiu [this message]
2020-10-12 20:59 ` [PATCH 03/18] media: hantro: make G1_REG_SOFT_RESET Rockchip specific Adrian Ratiu
2020-10-12 20:59 ` [PATCH 04/18] media: hantro: add reset controller support Adrian Ratiu
2020-10-13 8:11 ` Philipp Zabel
2020-10-12 20:59 ` [PATCH 05/18] media: hantro: prepare clocks before variant inits are run Adrian Ratiu
2020-10-12 20:59 ` [PATCH 06/18] media: hantro: imx8mq: simplify ctrlblk reset logic Adrian Ratiu
2020-10-12 20:59 ` [PATCH 07/18] regmap: mmio: add config option to allow relaxed MMIO accesses Adrian Ratiu
2020-10-13 10:26 ` Mark Brown
2020-10-14 11:51 ` Adrian Ratiu
2020-10-14 12:12 ` Mark Brown
2020-10-14 13:00 ` Adrian Ratiu
2020-10-12 20:59 ` [PATCH 08/18] media: hantro: add initial MMIO regmap infrastructure Adrian Ratiu
2020-10-12 20:59 ` [PATCH 09/18] media: hantro: default regmap to relaxed MMIO Adrian Ratiu
2020-10-12 20:59 ` [PATCH 10/18] media: hantro: convert G1 h264 decoder to regmap fields Adrian Ratiu
2020-10-12 20:59 ` [PATCH 11/18] media: hantro: convert G1 postproc to regmap Adrian Ratiu
2020-10-12 20:59 ` [PATCH 12/18] media: hantro: add VC8000D h264 decoding Adrian Ratiu
2020-10-12 20:59 ` [PATCH 13/18] media: hantro: add VC8000D postproc support Adrian Ratiu
2020-10-12 20:59 ` [PATCH 14/18] media: hantro: make PP enablement logic a bit smarter Adrian Ratiu
2020-10-12 20:59 ` [PATCH 15/18] media: hantro: add user-selectable, platform-selectable H264 High10 Adrian Ratiu
2020-10-12 20:59 ` [PATCH 16/18] media: hantro: rename h264_dec as it's not G1 specific anymore Adrian Ratiu
2020-10-12 20:59 ` [PATCH 17/18] media: hantro: add dump registers debug option before decode start Adrian Ratiu
2020-10-12 20:59 ` [PATCH 18/18] media: hantro: document encoder reg fields Adrian Ratiu
2020-10-12 23:39 ` [PATCH 00/18] Add Hantro regmap and VC8000 h264 decode support Jonas Karlman
2020-10-13 6:48 ` Adrian Ratiu
2020-10-29 12:38 ` Ezequiel Garcia
2020-10-29 16:21 ` Jonas Karlman
2020-11-03 15:27 ` Ezequiel Garcia
2020-10-29 13:07 ` Ezequiel Garcia
2020-10-29 14:15 ` Robin Murphy
2020-10-29 14:48 ` Mark Brown
2020-10-29 16:27 ` Ezequiel Garcia
2020-10-29 17:59 ` Mark Brown
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