From: Elaine Zhang <zhangqing@rock-chips.com>
To: sboyd@kernel.org, heiko@sntech.de
Cc: huangtao@rock-chips.com, Elaine Zhang <zhangqing@rock-chips.com>,
linux-kernel@vger.kernel.org, kever.yang@rock-chips.com,
linux-rockchip@lists.infradead.org, tony.xie@rock-chips.com,
finley.xiao@rock-chips.com, linux-arm-kernel@lists.infradead.org,
linux-clk@vger.kernel.org, cl@rock-chips.com
Subject: [PATCH v1 1/4] dt-bindings: add bindings for rk3568 clock controller
Date: Tue, 23 Feb 2021 17:53:49 +0800 [thread overview]
Message-ID: <20210223095352.11544-2-zhangqing@rock-chips.com> (raw)
In-Reply-To: <20210223095352.11544-1-zhangqing@rock-chips.com>
Add devicetree bindings for Rockchip cru which found on
Rockchip SoCs.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
---
.../bindings/clock/rockchip,rk3568-cru.txt | 66 +++++++++++++++++++
1 file changed, 66 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/rockchip,rk3568-cru.txt
diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3568-cru.txt b/Documentation/devicetree/bindings/clock/rockchip,rk3568-cru.txt
new file mode 100644
index 000000000000..b1119aecb7c7
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/rockchip,rk3568-cru.txt
@@ -0,0 +1,66 @@
+* Rockchip RK3568 Clock and Reset Unit
+
+The RK3568 clock controller generates and supplies clock to various
+controllers within the SoC and also implements a reset controller for SoC
+peripherals.
+
+Required Properties:
+
+- compatible: PMU for CRU should be "rockchip,rk3568-pmucru"
+- compatible: CRU should be "rockchip,rk3568-cru"
+- reg: physical base address of the controller and length of memory mapped
+ region.
+- #clock-cells: should be 1.
+- #reset-cells: should be 1.
+
+Optional Properties:
+
+- rockchip,grf: phandle to the syscon managing the "general register files"
+ If missing, pll rates are not changeable, due to the missing pll lock status.
+
+Each clock is assigned an identifier and client nodes can use this identifier
+to specify the clock which they consume. All available clocks are defined as
+preprocessor macros in the dt-bindings/clock/rk3568-cru.h headers and can be
+used in device tree sources. Similar macros exist for the reset sources in
+these files.
+
+External clocks:
+
+There are several clocks that are generated outside the SoC. It is expected
+that they are defined using standard clock bindings with following
+clock-output-names:
+ - "xin24m" - crystal input - required,
+ - "xin32k" - rtc clock - optional,
+ - "i2sx_mclkin" - external I2S clock - optional,
+ - "xin_osc0_usbphyx_g" - external USBPHY clock - optional,
+ - "xin_osc0_mipidsiphyx_g" - external MIPIDSIPHY clock - optional,
+
+Example: Clock controller node:
+
+ pmucru: clock-controller@fdd00000 {
+ compatible = "rockchip,rK3568-pmucru";
+ reg = <0x0 0xfdd00000 0x0 0x1000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ cru: clock-controller@fdd20000 {
+ compatible = "rockchip,rK3568-cru";
+ reg = <0x0 0xfdd20000 0x0 0x1000>;
+ rockchip,grf = <&grf>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+Example: UART controller node that consumes the clock generated by the clock
+ controller:
+
+ uart1: serial@fe650000 {
+ compatible = "rockchip,rK3568-uart", "snps,dw-apb-uart";
+ reg = <0x0 0xfe650000 0x0 0x100>;
+ interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
+ clock-names = "baudclk", "apb_pclk";
+ };
--
2.17.1
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next prev parent reply other threads:[~2021-02-23 9:54 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-02-23 9:53 [PATCH v1 0/4] clk: rockchip: add clock controller for rk3568 Elaine Zhang
2021-02-23 9:53 ` Elaine Zhang [this message]
2021-02-23 10:50 ` [PATCH v1 1/4] dt-bindings: add bindings for rk3568 clock controller Johan Jonker
2021-02-23 10:54 ` Heiko Stübner
2021-02-23 9:53 ` [PATCH v1 2/4] clk: rockchip: add dt-binding header for rk3568 Elaine Zhang
2021-02-23 10:45 ` Heiko Stübner
2021-02-24 6:35 ` elaine.zhang
2021-02-24 7:27 ` Heiko Stübner
2021-02-23 9:53 ` [PATCH v1 3/4] clk: rockchip: support more core div setting Elaine Zhang
2021-02-23 10:22 ` Heiko Stübner
2021-02-25 2:59 ` elaine.zhang
2021-02-25 9:07 ` Heiko Stübner
2021-02-23 9:53 ` [PATCH v1 4/4] clk: rockchip: add clock controller for rk3568 Elaine Zhang
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