From: Rob Herring <robh@kernel.org>
To: Sascha Hauer <s.hauer@pengutronix.de>
Cc: dri-devel@lists.freedesktop.org,
linux-arm-kernel@lists.infradead.org,
linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org,
kernel@pengutronix.de, "Andy Yan" <andy.yan@rock-chips.com>,
"Benjamin Gaignard" <benjamin.gaignard@collabora.com>,
"Michael Riesch" <michael.riesch@wolfvision.net>,
"Sandy Huang" <hjc@rock-chips.com>,
"Heiko Stübner" <heiko@sntech.de>,
"Peter Geis" <pgwipeout@gmail.com>
Subject: Re: [PATCH 17/27] dt-bindings: display: rockchip: Add binding for VOP2
Date: Tue, 1 Feb 2022 11:22:33 -0600 [thread overview]
Message-ID: <YflsWTaUexj3u9Je@robh.at.kernel.org> (raw)
In-Reply-To: <20220126145549.617165-18-s.hauer@pengutronix.de>
On Wed, Jan 26, 2022 at 03:55:39PM +0100, Sascha Hauer wrote:
> The VOP2 is found on newer Rockchip SoCs like the rk3568 or the rk3566.
> The binding differs slightly from the existing VOP binding, so add a new
> binding file for it.
>
> Changes since v3:
> - drop redundant _vop suffix from clock names
>
> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> ---
> .../display/rockchip/rockchip-vop2.yaml | 146 ++++++++++++++++++
> 1 file changed, 146 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml
>
> diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml
> new file mode 100644
> index 000000000000..572cfb307c20
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml
> @@ -0,0 +1,146 @@
> +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/rockchip/rockchip-vop2.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Rockchip SoC display controller (VOP2)
> +
> +description:
> + VOP2 (Video Output Processor v2) is the display controller for the Rockchip
> + series of SoCs which transfers the image data from a video memory
> + buffer to an external LCD interface.
> +
> +maintainers:
> + - Sandy Huang <hjc@rock-chips.com>
> + - Heiko Stuebner <heiko@sntech.de>
> +
> +properties:
> + compatible:
> + enum:
> + - rockchip,rk3566-vop
> + - rockchip,rk3568-vop
> +
> + reg:
> + minItems: 1
> + items:
> + - description:
> + Must contain one entry corresponding to the base address and length
> + of the register space.
> + - description:
> + Can optionally contain a second entry corresponding to
> + the CRTC gamma LUT address.
> +
> + interrupts:
> + maxItems: 1
> + description:
> + The VOP interrupt is shared by several interrupt sources, such as
> + frame start (VSYNC), line flag and other status interrupts.
> +
> + clocks:
> + items:
> + - description: Clock for ddr buffer transfer.
> + - description: Clock for the ahb bus to R/W the phy regs.
> + - description: Pixel clock for video port 0.
> + - description: Pixel clock for video port 1.
> + - description: Pixel clock for video port 2.
> +
> + clock-names:
> + items:
> + - const: aclk
> + - const: hclk
> + - const: dclk_vp0
> + - const: dclk_vp1
> + - const: dclk_vp2
> +
> + rockchip,grf:
> + $ref: /schemas/types.yaml#/definitions/phandle
> + description:
> + Phandle to GRF regs used for misc control
> +
> + ports:
> + $ref: /schemas/graph.yaml#/properties/ports
> +
> + properties:
> + port@0:
> + $ref: /schemas/graph.yaml#/properties/port
> + description:
> + Output endpoint of VP0
> +
> + port@1:
> + $ref: /schemas/graph.yaml#/properties/port
> + description:
> + Output endpoint of VP1
> +
> + port@2:
> + $ref: /schemas/graph.yaml#/properties/port
> + description:
> + Output endpoint of VP2
> +
> + assigned-clocks: true
> +
> + assigned-clock-rates: true
> +
> + assigned-clock-parents: true
You can drop these. They are implicitly allowed with 'clocks'.
> +
> + iommus:
> + maxItems: 1
> +
> + power-domains:
> + maxItems: 1
> +
> +required:
> + - compatible
> + - reg
> + - interrupts
> + - clocks
> + - clock-names
> + - ports
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/rk3568-cru.h>
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> + #include <dt-bindings/power/rk3568-power.h>
> + bus {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + vop: vop@fe040000 {
> + compatible = "rockchip,rk3568-vop";
> + reg = <0x0 0xfe040000 0x0 0x3000>, <0x0 0xfe044000 0x0 0x1000>;
> + interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cru ACLK_VOP>,
> + <&cru HCLK_VOP>,
> + <&cru DCLK_VOP0>,
> + <&cru DCLK_VOP1>,
> + <&cru DCLK_VOP2>;
> + clock-names = "aclk_vop",
> + "hclk_vop",
> + "dclk_vp0",
> + "dclk_vp1",
> + "dclk_vp2";
> + power-domains = <&power RK3568_PD_VO>;
> + iommus = <&vop_mmu>;
> + vop_out: ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + vp0: port@0 {
> + reg = <0>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> + vp1: port@1 {
> + reg = <1>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> + vp2: port@2 {
> + reg = <2>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> + };
> + };
> + };
> --
> 2.30.2
>
>
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next prev parent reply other threads:[~2022-02-01 17:24 UTC|newest]
Thread overview: 56+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-01-26 14:55 [PATCH v4 00/27] drm/rockchip: RK356x VOP2 support Sascha Hauer
2022-01-26 14:55 ` [PATCH 01/27] drm/encoder: Add of_graph port to struct drm_encoder Sascha Hauer
2022-01-26 15:04 ` Aw: " Frank Wunderlich
2022-01-26 14:55 ` [PATCH 02/27] drm/rockchip: dw_hdmi: Do not leave clock enabled in error case Sascha Hauer
2022-01-26 14:55 ` [PATCH 03/27] drm/rockchip: dw_hdmi: rename vpll clock to reference clock Sascha Hauer
2022-01-26 14:55 ` [PATCH 04/27] drm/rockchip: dw_hdmi: add rk3568 support Sascha Hauer
2022-01-26 14:55 ` [PATCH 05/27] drm/rockchip: dw_hdmi: add regulator support Sascha Hauer
2022-01-26 14:55 ` [PATCH 06/27] drm/rockchip: dw_hdmi: Add support for hclk Sascha Hauer
2022-01-26 14:55 ` [PATCH 07/27] drm/rockchip: dw_hdmi: Use auto-generated tables Sascha Hauer
2022-01-26 15:54 ` Doug Anderson
2022-01-27 11:20 ` Sascha Hauer
2022-01-26 14:55 ` [PATCH 08/27] drm/rockchip: dw_hdmi: drop mode_valid hook Sascha Hauer
2022-01-26 14:55 ` [PATCH 09/27] drm/rockchip: dw_hdmi: Set cur_ctr to 0 always Sascha Hauer
2022-01-26 15:42 ` Doug Anderson
2022-01-27 11:06 ` Sascha Hauer
2022-01-26 14:55 ` [PATCH 10/27] drm/rockchip: dw_hdmi: add default 594Mhz clk for 4K@60hz Sascha Hauer
2022-01-26 14:55 ` [PATCH 11/27] clk: rockchip: rk3568: Add more PLL rates Sascha Hauer
2022-01-26 14:55 ` [PATCH 12/27] dt-bindings: display: rockchip: dw-hdmi: Add compatible for rk3568 HDMI Sascha Hauer
2022-01-26 14:55 ` [PATCH 13/27] dt-bindings: display: rockchip: dw-hdmi: Make unwedge pinctrl optional Sascha Hauer
2022-02-09 3:29 ` Rob Herring
2022-01-26 14:55 ` [PATCH 14/27] dt-bindings: display: rockchip: dw-hdmi: use "ref" as clock name Sascha Hauer
2022-02-09 3:30 ` Rob Herring
2022-01-26 14:55 ` [PATCH 15/27] dt-bindings: display: rockchip: dw-hdmi: Add regulator support Sascha Hauer
2022-02-09 3:30 ` Rob Herring
2022-01-26 14:55 ` [PATCH 16/27] dt-bindings: display: rockchip: dw-hdmi: Add additional clock Sascha Hauer
2022-02-09 3:31 ` Rob Herring
2022-01-26 14:55 ` [PATCH 17/27] dt-bindings: display: rockchip: Add binding for VOP2 Sascha Hauer
2022-01-26 22:10 ` Rob Herring
2022-02-01 17:22 ` Rob Herring [this message]
2022-01-26 14:55 ` [PATCH 18/27] arm64: dts: rockchip: rk3399: reorder hmdi clocks Sascha Hauer
2022-01-26 14:55 ` [PATCH 19/27] arm64: dts: rockchip: rk3399: rename HDMI ref clock to 'ref' Sascha Hauer
2022-01-26 14:55 ` [PATCH 20/27] arm64: dts: rockchip: rk356x: Add VOP2 nodes Sascha Hauer
2022-02-09 3:32 ` Rob Herring
2022-01-26 14:55 ` [PATCH 21/27] arm64: dts: rockchip: rk356x: Add HDMI nodes Sascha Hauer
2022-01-26 16:04 ` Peter Geis
2022-01-26 17:56 ` Robin Murphy
2022-01-26 18:44 ` Peter Geis
2022-01-26 19:24 ` Robin Murphy
2022-01-26 20:00 ` Peter Geis
2022-01-26 14:55 ` [PATCH 22/27] arm64: dts: rockchip: rk3568-evb: Enable VOP2 and hdmi Sascha Hauer
2022-01-26 14:55 ` [PATCH 23/27] arm64: dts: rockchip: enable vop2 and hdmi tx on quartz64a Sascha Hauer
2022-01-26 14:55 ` [PATCH 24/27] clk: rk3568: drop CLK_SET_RATE_PARENT from dclk_vop* Sascha Hauer
2022-01-29 17:48 ` Heiko Stübner
2022-01-31 8:10 ` Sascha Hauer
2022-02-08 11:41 ` Heiko Stübner
2022-01-26 14:55 ` [PATCH 25/27] clk: rk3568: Add CLK_SET_RATE_PARENT to the HDMI reference clock Sascha Hauer
2022-01-26 14:55 ` [PATCH 26/27] drm/rockchip: Make VOP driver optional Sascha Hauer
2022-01-26 14:55 ` [PATCH 27/27] drm: rockchip: Add VOP2 driver Sascha Hauer
2022-01-26 17:10 ` Aw: " Frank Wunderlich
2022-01-27 9:17 ` Piotr Oniszczuk
2022-01-27 11:00 ` Sascha Hauer
2022-01-27 14:43 ` Piotr Oniszczuk
[not found] ` <9d23b94a-c8db-6588-fadf-97ea5e748f8a@pscan.uk>
2022-01-28 9:19 ` MiPi DSI interface for RK3566 ? Sascha Hauer
2022-01-27 14:16 ` [PATCH v4 00/27] drm/rockchip: RK356x VOP2 support Michael Riesch
2022-02-08 11:57 ` (subset) " Heiko Stuebner
2022-02-08 13:21 ` Heiko Stuebner
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