Linux-rt-users archive on
 help / color / Atom feed
From: Thomas Gleixner <>
To: Kar Hin Ong <>, Bjorn Helgaas <>
Cc: linux-rt-users <>,
	LKML <>,
	"x86\" <>,
	"linux-pci\" <>,
	"H. Peter Anvin" <>,
	Dave Hansen <>,
	Julia Cartwright <>,
	Keng Soon Cheah <>,
	Gratian Crisan <>,
	Peter Zijlstra <>
Subject: RE: RE: Re: "oneshot" interrupt causes another interrupt to be fired erroneously in Haswell system
Date: Thu, 16 Jan 2020 11:01:52 +0100
Message-ID: <> (raw)
In-Reply-To: <>

Kar Hin Ong <> writes:
>> I don't have access to the document you mentioned, but I know that chipsets
>> have a knob to control that behaviour. Just checked a few chipset docs and they
>> contain the same sentence, but then in the next paragraph they say:
>>  "If the I/OxAPIC entry is masked (via the mask bit in the corresponding
>>   Redirection Table Entry), then the corresponding PCI Express
>>   interrupt(s) is forwarded to the legacy ICH, provided the Disable PCI
>>   INTx Routing to ICH bit is clear, Section, QPIPINTRC: Intel
>>   QuickPath Interconnect Protocol Interrupt Control."
>> That control bit is 0 after reset, so the legacy forwarding works.
> Intel support engineer do provide similar advice to us as a workaround
> to the CPU behaviour.  They said we could enable the "Don'tRouteToPCH"
> bit in the BIOS to block the interrupt from propagating to PCH.  This
> bit is located at "Coherent Interface Protocol Interrupt Control
> (cipintrc)" register of "Virtualization" device (Bus 0, Device 5,
> Function 0, Offset 0x14C).
> With the help of our BIOS engineer, after setting this bit in BIOS
> does prevent the interrupt forwarding.
> However, Intel told us that this workaround is not validated, i.e. the
> side effect of setting this bit is unknown.

What? That's ridiculous.

That bit is documented in various chipset documents and that legacy
rerouting is really just there to support OSes which do not support
multiple IO-APICs properly.

If setting this bit has unknown side effects then someone at Intel
should have a close look and fix their documentation.

Can the Intel people on Cc please take care of this?

As we have already quirks in drivers/pci/quirks.c which handle the same
issue on older chipsets, we really should add one for these kind of
systems to avoid fiddling with the BIOS (which you can, but most people



      reply index

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-10-31  3:53 Kar Hin Ong
2019-10-31 23:05 ` Bjorn Helgaas
2019-11-01  7:46   ` Kar Hin Ong
2019-11-04 23:41   ` Thomas Gleixner
2019-11-07  9:38     ` Kar Hin Ong
2019-11-21 11:22       ` Kar Hin Ong
2020-01-15 23:05       ` Thomas Gleixner
2020-01-16  7:32         ` Kar Hin Ong
2020-01-16 10:01           ` Thomas Gleixner [this message]

Reply instructions:

You may reply publically to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \ \ \ \ \ \ \ \ \ \ \ \ \ \ \

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link

Linux-rt-users archive on

Archives are clonable:
	git clone --mirror linux-rt-users/git/0.git

	# If you have public-inbox 1.1+ installed, you may
	# initialize and index your mirror using the following commands:
	public-inbox-init -V2 linux-rt-users linux-rt-users/ \
	public-inbox-index linux-rt-users

Example config snippet for mirrors

Newsgroup available over NNTP:

AGPL code for this site: git clone