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From: Kar Hin Ong <kar.hin.ong@ni.com>
To: Thomas Gleixner <tglx@linutronix.de>, Bjorn Helgaas <helgaas@kernel.org>
Cc: linux-rt-users <linux-rt-users@vger.kernel.org>,
	LKML <linux-kernel@vger.kernel.org>,
	"linux-x86_64@vger.kernel.org" <linux-x86_64@vger.kernel.org>,
	"linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>,
	"H. Peter Anvin" <hpa@zytor.com>,
	Dave Hansen <dave.hansen@linux.intel.com>,
	Julia Cartwright <julia.cartwright@ni.com>,
	Keng Soon Cheah <keng.soon.cheah@ni.com>
Subject: RE: Re: "oneshot" interrupt causes another interrupt to be fired erroneously in Haswell system
Date: Thu, 7 Nov 2019 09:38:41 +0000
Message-ID: <MN2PR04MB625594021250E0FB92EC955DC3780@MN2PR04MB6255.namprd04.prod.outlook.com> (raw)
In-Reply-To: <alpine.DEB.2.21.1911050017410.17054@nanos.tec.linutronix.de>

> On Thu, 31 Oct 2019, Bjorn Helgaas wrote:
> > On Thu, Oct 31, 2019 at 03:53:50AM +0000, Kar Hin Ong wrote:
> > > I've an Intel Haswell system running Linux kernel v4.14 with
> > > preempt_rt patch. The system contain 2 IOAPICs: IOAPIC 1 is on the
> > > PCH where IOAPIC 2 is on the CPU.
> > >
> > > I observed that whenever a PCI device is firing interrupt (INTx) to
> > > Pin 20 of IOAPIC 2 (GSI 44); the kernel will receives 2 interrupts:
> > >    1. Interrupt from Pin 20 of IOAPIC 2  -> Expected
> > >    2. Interrupt from Pin 19 of IOAPIC 1  -> UNEXPECTED, erroneously
> > >       triggered
> > >
> > > The unexpected interrupt is unhandled eventually. When this scenario
> > > happen more than 99,000 times, kernel disables the interrupt line
> > > (Pin 19 of IOAPIC 1) and causing device that has requested it become
> > > malfunction.
> > >
> > > I managed to also reproduced this issue on RHEL 8 and Ubuntu 19-04
> > > (without preempt_rt patch) after added "threadirqs" to the kernel
> > > command line.
> > >
> > > After digging further, I noticed that the said issue is happened
> > > whenever an interrupt pin on IOAPIC 2 is masked:
> > >  - Masking Pin 20 of IOAPIC 2 triggers Pin 19 of IOAPIC 1
> > >  - Masking Pin 22 of IOAPIC 2 triggers Pin 18 of IOAPIC 1
> 
> This is pretty much the same problem which we had analyzed and worked around
> years ago.
> 
> > > From Intel Xeon Processor E5/E7 v3 Product Family External Design
> > > Specification (EDS), Volume One: Architecture, section 13.1 (Legacy
> > > PCI Interrupt Handling), it mention: "If the I/OxAPIC entry is
> > > masked (via the 'mask' bit in the corresponding Redirection Table
> > > Entry), then the corresponding PCI Express interrupt(s) is forwarded
> > > to the legacy PCH"
> 
> Oh well. Really useful behaviour - NOT!
> 
> > > I would like to understand if my interpretation is make sense. If
> > > yes, should the "oneshot" algorithm need to be updated to support
> > > Haswell system?
> 
> No. You cannot change the oneshot algorithm.
> 
> The workarounds for this are enabled by PCI quirls and either
> CONFIG_X86_REROUTE_FOR_BROKEN_BOOT_IRQS=y or 'ioapicreroute' on the
> command line.
> 
> It might be wortha try to add the PCI ID of that box to the quirk list, i.e. the PCI ID
> matches in drivers/pci/quirks.c which belong to the
> function: quirk_reroute_to_boot_interrupts_intel().

Do you mean adding the PCI ID of the device that actually fires interrupt? It can be any PCI card though (example: external ETH controller, data acquisition module, etc).
Or you mean to add the ID of all PCIe root ports that routed to IOAPIC 2?

Based on Haswell specification, seems like every entry on IOAPIC 2 will experience this problem.
If to reroute every entry on IOAPIC 2 to IOAPIC 1, probably we should just disable IOAPIC 2 instead?


      reply index

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-10-31  3:53 Kar Hin Ong
2019-10-31 23:05 ` Bjorn Helgaas
2019-11-01  7:46   ` Kar Hin Ong
2019-11-04 23:41   ` Thomas Gleixner
2019-11-07  9:38     ` Kar Hin Ong [this message]

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