* [PATCH v3 01/10] mfd: mt6397: clean up code
2019-05-03 9:31 [PATCH v3 00/10] Add Support for MediaTek PMIC MT6358 Hsin-Hsiung Wang
@ 2019-05-03 9:31 ` Hsin-Hsiung Wang
2019-05-03 9:31 ` [PATCH v3 02/10] mfd: mt6397: extract irq related code from core driver Hsin-Hsiung Wang
` (8 subsequent siblings)
9 siblings, 0 replies; 22+ messages in thread
From: Hsin-Hsiung Wang @ 2019-05-03 9:31 UTC (permalink / raw)
To: Lee Jones, Rob Herring, Mark Brown, Matthias Brugger
Cc: Liam Girdwood, Mark Rutland, Eddie Huang, Sean Wang,
Alessandro Zummo, Alexandre Belloni, Hsin-Hsiung Wang,
devicetree, linux-arm-kernel, linux-mediatek, linux-kernel,
linux-rtc, srv_heupstream
refine some variable name for more readable
Acked-for-MFD-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>
---
drivers/mfd/mt6397-core.c | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/mfd/mt6397-core.c b/drivers/mfd/mt6397-core.c
index ab24e176ef44..c9393bc86743 100644
--- a/drivers/mfd/mt6397-core.c
+++ b/drivers/mfd/mt6397-core.c
@@ -18,17 +18,17 @@
#include <linux/of_irq.h>
#include <linux/regmap.h>
#include <linux/mfd/core.h>
-#include <linux/mfd/mt6397/core.h>
#include <linux/mfd/mt6323/core.h>
-#include <linux/mfd/mt6397/registers.h>
+#include <linux/mfd/mt6397/core.h>
#include <linux/mfd/mt6323/registers.h>
+#include <linux/mfd/mt6397/registers.h>
#define MT6397_RTC_BASE 0xe000
#define MT6397_RTC_SIZE 0x3e
-#define MT6323_CID_CODE 0x23
-#define MT6391_CID_CODE 0x91
-#define MT6397_CID_CODE 0x97
+#define MT6323_CHIP_ID 0x23
+#define MT6391_CHIP_ID 0x91
+#define MT6397_CHIP_ID 0x97
static const struct resource mt6397_rtc_resources[] = {
{
@@ -298,7 +298,7 @@ static int mt6397_probe(struct platform_device *pdev)
return pmic->irq;
switch (id & 0xff) {
- case MT6323_CID_CODE:
+ case MT6323_CHIP_ID:
pmic->int_con[0] = MT6323_INT_CON0;
pmic->int_con[1] = MT6323_INT_CON1;
pmic->int_status[0] = MT6323_INT_STATUS0;
@@ -312,8 +312,8 @@ static int mt6397_probe(struct platform_device *pdev)
0, pmic->irq_domain);
break;
- case MT6397_CID_CODE:
- case MT6391_CID_CODE:
+ case MT6391_CHIP_ID:
+ case MT6397_CHIP_ID:
pmic->int_con[0] = MT6397_INT_CON0;
pmic->int_con[1] = MT6397_INT_CON1;
pmic->int_status[0] = MT6397_INT_STATUS0;
--
2.18.0
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH v3 02/10] mfd: mt6397: extract irq related code from core driver
2019-05-03 9:31 [PATCH v3 00/10] Add Support for MediaTek PMIC MT6358 Hsin-Hsiung Wang
2019-05-03 9:31 ` [PATCH v3 01/10] mfd: mt6397: clean up code Hsin-Hsiung Wang
@ 2019-05-03 9:31 ` Hsin-Hsiung Wang
2019-05-07 5:11 ` Nicolas Boichat
2019-05-03 9:31 ` [PATCH v3 03/10] mfd: mt6397: modify suspend/resume behavior Hsin-Hsiung Wang
` (7 subsequent siblings)
9 siblings, 1 reply; 22+ messages in thread
From: Hsin-Hsiung Wang @ 2019-05-03 9:31 UTC (permalink / raw)
To: Lee Jones, Rob Herring, Mark Brown, Matthias Brugger
Cc: Liam Girdwood, Mark Rutland, Eddie Huang, Sean Wang,
Alessandro Zummo, Alexandre Belloni, Hsin-Hsiung Wang,
devicetree, linux-arm-kernel, linux-mediatek, linux-kernel,
linux-rtc, srv_heupstream
In order to support different types of irq design, we decide to add
separate irq drivers for different design and keep mt6397 mfd core
simple and reusable to all generations of PMICs so far.
Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>
---
drivers/mfd/Makefile | 3 +-
drivers/mfd/mt6397-core.c | 146 --------------------------
drivers/mfd/mt6397-irq.c | 181 ++++++++++++++++++++++++++++++++
include/linux/mfd/mt6397/core.h | 9 ++
4 files changed, 192 insertions(+), 147 deletions(-)
create mode 100644 drivers/mfd/mt6397-irq.c
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index b4569ed7f3f3..ab1e228b5a2f 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -234,7 +234,8 @@ obj-$(CONFIG_INTEL_SOC_PMIC) += intel-soc-pmic.o
obj-$(CONFIG_INTEL_SOC_PMIC_BXTWC) += intel_soc_pmic_bxtwc.o
obj-$(CONFIG_INTEL_SOC_PMIC_CHTWC) += intel_soc_pmic_chtwc.o
obj-$(CONFIG_INTEL_SOC_PMIC_CHTDC_TI) += intel_soc_pmic_chtdc_ti.o
-obj-$(CONFIG_MFD_MT6397) += mt6397-core.o
+mt6397-objs := mt6397-core.o mt6397-irq.o
+obj-$(CONFIG_MFD_MT6397) += mt6397.o
obj-$(CONFIG_MFD_ALTERA_A10SR) += altera-a10sr.o
obj-$(CONFIG_MFD_STPMIC1) += stpmic1.o
diff --git a/drivers/mfd/mt6397-core.c b/drivers/mfd/mt6397-core.c
index c9393bc86743..c80f0449fe7e 100644
--- a/drivers/mfd/mt6397-core.c
+++ b/drivers/mfd/mt6397-core.c
@@ -26,10 +26,6 @@
#define MT6397_RTC_BASE 0xe000
#define MT6397_RTC_SIZE 0x3e
-#define MT6323_CHIP_ID 0x23
-#define MT6391_CHIP_ID 0x91
-#define MT6397_CHIP_ID 0x97
-
static const struct resource mt6397_rtc_resources[] = {
{
.start = MT6397_RTC_BASE,
@@ -94,148 +90,6 @@ static const struct mfd_cell mt6397_devs[] = {
}
};
-static void mt6397_irq_lock(struct irq_data *data)
-{
- struct mt6397_chip *mt6397 = irq_data_get_irq_chip_data(data);
-
- mutex_lock(&mt6397->irqlock);
-}
-
-static void mt6397_irq_sync_unlock(struct irq_data *data)
-{
- struct mt6397_chip *mt6397 = irq_data_get_irq_chip_data(data);
-
- regmap_write(mt6397->regmap, mt6397->int_con[0],
- mt6397->irq_masks_cur[0]);
- regmap_write(mt6397->regmap, mt6397->int_con[1],
- mt6397->irq_masks_cur[1]);
-
- mutex_unlock(&mt6397->irqlock);
-}
-
-static void mt6397_irq_disable(struct irq_data *data)
-{
- struct mt6397_chip *mt6397 = irq_data_get_irq_chip_data(data);
- int shift = data->hwirq & 0xf;
- int reg = data->hwirq >> 4;
-
- mt6397->irq_masks_cur[reg] &= ~BIT(shift);
-}
-
-static void mt6397_irq_enable(struct irq_data *data)
-{
- struct mt6397_chip *mt6397 = irq_data_get_irq_chip_data(data);
- int shift = data->hwirq & 0xf;
- int reg = data->hwirq >> 4;
-
- mt6397->irq_masks_cur[reg] |= BIT(shift);
-}
-
-#ifdef CONFIG_PM_SLEEP
-static int mt6397_irq_set_wake(struct irq_data *irq_data, unsigned int on)
-{
- struct mt6397_chip *mt6397 = irq_data_get_irq_chip_data(irq_data);
- int shift = irq_data->hwirq & 0xf;
- int reg = irq_data->hwirq >> 4;
-
- if (on)
- mt6397->wake_mask[reg] |= BIT(shift);
- else
- mt6397->wake_mask[reg] &= ~BIT(shift);
-
- return 0;
-}
-#else
-#define mt6397_irq_set_wake NULL
-#endif
-
-static struct irq_chip mt6397_irq_chip = {
- .name = "mt6397-irq",
- .irq_bus_lock = mt6397_irq_lock,
- .irq_bus_sync_unlock = mt6397_irq_sync_unlock,
- .irq_enable = mt6397_irq_enable,
- .irq_disable = mt6397_irq_disable,
- .irq_set_wake = mt6397_irq_set_wake,
-};
-
-static void mt6397_irq_handle_reg(struct mt6397_chip *mt6397, int reg,
- int irqbase)
-{
- unsigned int status;
- int i, irq, ret;
-
- ret = regmap_read(mt6397->regmap, reg, &status);
- if (ret) {
- dev_err(mt6397->dev, "Failed to read irq status: %d\n", ret);
- return;
- }
-
- for (i = 0; i < 16; i++) {
- if (status & BIT(i)) {
- irq = irq_find_mapping(mt6397->irq_domain, irqbase + i);
- if (irq)
- handle_nested_irq(irq);
- }
- }
-
- regmap_write(mt6397->regmap, reg, status);
-}
-
-static irqreturn_t mt6397_irq_thread(int irq, void *data)
-{
- struct mt6397_chip *mt6397 = data;
-
- mt6397_irq_handle_reg(mt6397, mt6397->int_status[0], 0);
- mt6397_irq_handle_reg(mt6397, mt6397->int_status[1], 16);
-
- return IRQ_HANDLED;
-}
-
-static int mt6397_irq_domain_map(struct irq_domain *d, unsigned int irq,
- irq_hw_number_t hw)
-{
- struct mt6397_chip *mt6397 = d->host_data;
-
- irq_set_chip_data(irq, mt6397);
- irq_set_chip_and_handler(irq, &mt6397_irq_chip, handle_level_irq);
- irq_set_nested_thread(irq, 1);
- irq_set_noprobe(irq);
-
- return 0;
-}
-
-static const struct irq_domain_ops mt6397_irq_domain_ops = {
- .map = mt6397_irq_domain_map,
-};
-
-static int mt6397_irq_init(struct mt6397_chip *mt6397)
-{
- int ret;
-
- mutex_init(&mt6397->irqlock);
-
- /* Mask all interrupt sources */
- regmap_write(mt6397->regmap, mt6397->int_con[0], 0x0);
- regmap_write(mt6397->regmap, mt6397->int_con[1], 0x0);
-
- mt6397->irq_domain = irq_domain_add_linear(mt6397->dev->of_node,
- MT6397_IRQ_NR, &mt6397_irq_domain_ops, mt6397);
- if (!mt6397->irq_domain) {
- dev_err(mt6397->dev, "could not create irq domain\n");
- return -ENOMEM;
- }
-
- ret = devm_request_threaded_irq(mt6397->dev, mt6397->irq, NULL,
- mt6397_irq_thread, IRQF_ONESHOT, "mt6397-pmic", mt6397);
- if (ret) {
- dev_err(mt6397->dev, "failed to register irq=%d; err: %d\n",
- mt6397->irq, ret);
- return ret;
- }
-
- return 0;
-}
-
#ifdef CONFIG_PM_SLEEP
static int mt6397_irq_suspend(struct device *dev)
{
diff --git a/drivers/mfd/mt6397-irq.c b/drivers/mfd/mt6397-irq.c
new file mode 100644
index 000000000000..b2d3ce1f3115
--- /dev/null
+++ b/drivers/mfd/mt6397-irq.c
@@ -0,0 +1,181 @@
+// SPDX-License-Identifier: GPL-2.0
+//
+// Copyright (c) 2019 MediaTek Inc.
+
+#include <linux/interrupt.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/of_irq.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/mfd/mt6323/core.h>
+#include <linux/mfd/mt6323/registers.h>
+#include <linux/mfd/mt6397/core.h>
+#include <linux/mfd/mt6397/registers.h>
+
+static void mt6397_irq_lock(struct irq_data *data)
+{
+ struct mt6397_chip *mt6397 = irq_data_get_irq_chip_data(data);
+
+ mutex_lock(&mt6397->irqlock);
+}
+
+static void mt6397_irq_sync_unlock(struct irq_data *data)
+{
+ struct mt6397_chip *mt6397 = irq_data_get_irq_chip_data(data);
+
+ regmap_write(mt6397->regmap, mt6397->int_con[0],
+ mt6397->irq_masks_cur[0]);
+ regmap_write(mt6397->regmap, mt6397->int_con[1],
+ mt6397->irq_masks_cur[1]);
+
+ mutex_unlock(&mt6397->irqlock);
+}
+
+static void mt6397_irq_disable(struct irq_data *data)
+{
+ struct mt6397_chip *mt6397 = irq_data_get_irq_chip_data(data);
+ int shift = data->hwirq & 0xf;
+ int reg = data->hwirq >> 4;
+
+ mt6397->irq_masks_cur[reg] &= ~BIT(shift);
+}
+
+static void mt6397_irq_enable(struct irq_data *data)
+{
+ struct mt6397_chip *mt6397 = irq_data_get_irq_chip_data(data);
+ int shift = data->hwirq & 0xf;
+ int reg = data->hwirq >> 4;
+
+ mt6397->irq_masks_cur[reg] |= BIT(shift);
+}
+
+#ifdef CONFIG_PM_SLEEP
+static int mt6397_irq_set_wake(struct irq_data *irq_data, unsigned int on)
+{
+ struct mt6397_chip *mt6397 = irq_data_get_irq_chip_data(irq_data);
+ int shift = irq_data->hwirq & 0xf;
+ int reg = irq_data->hwirq >> 4;
+
+ if (on)
+ mt6397->wake_mask[reg] |= BIT(shift);
+ else
+ mt6397->wake_mask[reg] &= ~BIT(shift);
+
+ return 0;
+}
+#else
+#define mt6397_irq_set_wake NULL
+#endif
+
+static struct irq_chip mt6397_irq_chip = {
+ .name = "mt6397-irq",
+ .irq_bus_lock = mt6397_irq_lock,
+ .irq_bus_sync_unlock = mt6397_irq_sync_unlock,
+ .irq_enable = mt6397_irq_enable,
+ .irq_disable = mt6397_irq_disable,
+ .irq_set_wake = mt6397_irq_set_wake,
+};
+
+static void mt6397_irq_handle_reg(struct mt6397_chip *mt6397, int reg,
+ int irqbase)
+{
+ unsigned int status;
+ int i, irq, ret;
+
+ ret = regmap_read(mt6397->regmap, reg, &status);
+ if (ret) {
+ dev_err(mt6397->dev, "Failed to read irq status: %d\n", ret);
+ return;
+ }
+
+ for (i = 0; i < 16; i++) {
+ if (status & BIT(i)) {
+ irq = irq_find_mapping(mt6397->irq_domain, irqbase + i);
+ if (irq)
+ handle_nested_irq(irq);
+ }
+ }
+
+ regmap_write(mt6397->regmap, reg, status);
+}
+
+static irqreturn_t mt6397_irq_thread(int irq, void *data)
+{
+ struct mt6397_chip *mt6397 = data;
+
+ mt6397_irq_handle_reg(mt6397, mt6397->int_status[0], 0);
+ mt6397_irq_handle_reg(mt6397, mt6397->int_status[1], 16);
+
+ return IRQ_HANDLED;
+}
+
+static int mt6397_irq_domain_map(struct irq_domain *d, unsigned int irq,
+ irq_hw_number_t hw)
+{
+ struct mt6397_chip *mt6397 = d->host_data;
+
+ irq_set_chip_data(irq, mt6397);
+ irq_set_chip_and_handler(irq, &mt6397_irq_chip, handle_level_irq);
+ irq_set_nested_thread(irq, 1);
+ irq_set_noprobe(irq);
+
+ return 0;
+}
+
+static const struct irq_domain_ops mt6397_irq_domain_ops = {
+ .map = mt6397_irq_domain_map,
+};
+
+int mt6397_irq_init(struct mt6397_chip *chip)
+{
+ int ret;
+
+ mutex_init(&chip->irqlock);
+
+ switch (chip->chip_id) {
+ case MT6323_CHIP_ID:
+ chip->int_con[0] = MT6323_INT_CON0;
+ chip->int_con[1] = MT6323_INT_CON1;
+ chip->int_status[0] = MT6323_INT_STATUS0;
+ chip->int_status[1] = MT6323_INT_STATUS1;
+ break;
+
+ case MT6391_CHIP_ID:
+ case MT6397_CHIP_ID:
+ chip->int_con[0] = MT6397_INT_CON0;
+ chip->int_con[1] = MT6397_INT_CON1;
+ chip->int_status[0] = MT6397_INT_STATUS0;
+ chip->int_status[1] = MT6397_INT_STATUS1;
+ break;
+
+ default:
+ dev_err(chip->dev, "unsupported chip: 0x%x\n", chip->chip_id);
+ return -ENODEV;
+ }
+
+ /* Mask all interrupt sources */
+ regmap_write(chip->regmap, chip->int_con[0], 0x0);
+ regmap_write(chip->regmap, chip->int_con[1], 0x0);
+
+ chip->irq_domain = irq_domain_add_linear(chip->dev->of_node,
+ MT6397_IRQ_NR,
+ &mt6397_irq_domain_ops,
+ chip);
+ if (!chip->irq_domain) {
+ dev_err(chip->dev, "could not create irq domain\n");
+ return -ENOMEM;
+ }
+
+ ret = devm_request_threaded_irq(chip->dev, chip->irq, NULL,
+ mt6397_irq_thread, IRQF_ONESHOT,
+ "mt6397-pmic", chip);
+ if (ret) {
+ dev_err(chip->dev, "failed to register irq=%d; err: %d\n",
+ chip->irq, ret);
+ return ret;
+ }
+
+ return 0;
+}
diff --git a/include/linux/mfd/mt6397/core.h b/include/linux/mfd/mt6397/core.h
index d678f526e498..93f9f5235575 100644
--- a/include/linux/mfd/mt6397/core.h
+++ b/include/linux/mfd/mt6397/core.h
@@ -15,6 +15,12 @@
#ifndef __MFD_MT6397_CORE_H__
#define __MFD_MT6397_CORE_H__
+enum chip_id {
+ MT6323_CHIP_ID = 0x23,
+ MT6391_CHIP_ID = 0x91,
+ MT6397_CHIP_ID = 0x97,
+};
+
enum mt6397_irq_numbers {
MT6397_IRQ_SPKL_AB = 0,
MT6397_IRQ_SPKR_AB,
@@ -62,6 +68,9 @@ struct mt6397_chip {
u16 irq_masks_cache[2];
u16 int_con[2];
u16 int_status[2];
+ u16 chip_id;
};
+int mt6397_irq_init(struct mt6397_chip *chip);
+
#endif /* __MFD_MT6397_CORE_H__ */
--
2.18.0
^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [PATCH v3 02/10] mfd: mt6397: extract irq related code from core driver
2019-05-03 9:31 ` [PATCH v3 02/10] mfd: mt6397: extract irq related code from core driver Hsin-Hsiung Wang
@ 2019-05-07 5:11 ` Nicolas Boichat
2019-05-07 5:16 ` Nicolas Boichat
0 siblings, 1 reply; 22+ messages in thread
From: Nicolas Boichat @ 2019-05-07 5:11 UTC (permalink / raw)
To: Hsin-Hsiung Wang
Cc: Lee Jones, Rob Herring, Mark Brown, Matthias Brugger,
Mark Rutland, Alessandro Zummo, Alexandre Belloni,
srv_heupstream, devicetree, Sean Wang, Liam Girdwood, lkml,
moderated list:ARM/Mediatek SoC support, linux-arm Mailing List,
Eddie Huang, linux-rtc, Claire Chang
On Fri, May 3, 2019 at 6:33 PM Hsin-Hsiung Wang
<hsin-hsiung.wang@mediatek.com> wrote:
>
> In order to support different types of irq design, we decide to add
> separate irq drivers for different design and keep mt6397 mfd core
> simple and reusable to all generations of PMICs so far.
>
> Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>
> ---
> drivers/mfd/Makefile | 3 +-
> drivers/mfd/mt6397-core.c | 146 --------------------------
> drivers/mfd/mt6397-irq.c | 181 ++++++++++++++++++++++++++++++++
> include/linux/mfd/mt6397/core.h | 9 ++
> 4 files changed, 192 insertions(+), 147 deletions(-)
> create mode 100644 drivers/mfd/mt6397-irq.c
>
> diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
> index b4569ed7f3f3..ab1e228b5a2f 100644
> --- a/drivers/mfd/Makefile
> +++ b/drivers/mfd/Makefile
> @@ -234,7 +234,8 @@ obj-$(CONFIG_INTEL_SOC_PMIC) += intel-soc-pmic.o
> obj-$(CONFIG_INTEL_SOC_PMIC_BXTWC) += intel_soc_pmic_bxtwc.o
> obj-$(CONFIG_INTEL_SOC_PMIC_CHTWC) += intel_soc_pmic_chtwc.o
> obj-$(CONFIG_INTEL_SOC_PMIC_CHTDC_TI) += intel_soc_pmic_chtdc_ti.o
> -obj-$(CONFIG_MFD_MT6397) += mt6397-core.o
> +mt6397-objs := mt6397-core.o mt6397-irq.o
> +obj-$(CONFIG_MFD_MT6397) += mt6397.o
>
> obj-$(CONFIG_MFD_ALTERA_A10SR) += altera-a10sr.o
> obj-$(CONFIG_MFD_STPMIC1) += stpmic1.o
> diff --git a/drivers/mfd/mt6397-core.c b/drivers/mfd/mt6397-core.c
> index c9393bc86743..c80f0449fe7e 100644
> --- a/drivers/mfd/mt6397-core.c
> +++ b/drivers/mfd/mt6397-core.c
> @@ -26,10 +26,6 @@
> #define MT6397_RTC_BASE 0xe000
> #define MT6397_RTC_SIZE 0x3e
>
> -#define MT6323_CHIP_ID 0x23
> -#define MT6391_CHIP_ID 0x91
> -#define MT6397_CHIP_ID 0x97
> -
> static const struct resource mt6397_rtc_resources[] = {
> {
> .start = MT6397_RTC_BASE,
> @@ -94,148 +90,6 @@ static const struct mfd_cell mt6397_devs[] = {
> }
> };
>
> -static void mt6397_irq_lock(struct irq_data *data)
> -{
> - struct mt6397_chip *mt6397 = irq_data_get_irq_chip_data(data);
> -
> - mutex_lock(&mt6397->irqlock);
> -}
> -
> -static void mt6397_irq_sync_unlock(struct irq_data *data)
> -{
> - struct mt6397_chip *mt6397 = irq_data_get_irq_chip_data(data);
> -
> - regmap_write(mt6397->regmap, mt6397->int_con[0],
> - mt6397->irq_masks_cur[0]);
> - regmap_write(mt6397->regmap, mt6397->int_con[1],
> - mt6397->irq_masks_cur[1]);
> -
> - mutex_unlock(&mt6397->irqlock);
> -}
> -
> -static void mt6397_irq_disable(struct irq_data *data)
> -{
> - struct mt6397_chip *mt6397 = irq_data_get_irq_chip_data(data);
> - int shift = data->hwirq & 0xf;
> - int reg = data->hwirq >> 4;
> -
> - mt6397->irq_masks_cur[reg] &= ~BIT(shift);
> -}
> -
> -static void mt6397_irq_enable(struct irq_data *data)
> -{
> - struct mt6397_chip *mt6397 = irq_data_get_irq_chip_data(data);
> - int shift = data->hwirq & 0xf;
> - int reg = data->hwirq >> 4;
> -
> - mt6397->irq_masks_cur[reg] |= BIT(shift);
> -}
> -
> -#ifdef CONFIG_PM_SLEEP
> -static int mt6397_irq_set_wake(struct irq_data *irq_data, unsigned int on)
> -{
> - struct mt6397_chip *mt6397 = irq_data_get_irq_chip_data(irq_data);
> - int shift = irq_data->hwirq & 0xf;
> - int reg = irq_data->hwirq >> 4;
> -
> - if (on)
> - mt6397->wake_mask[reg] |= BIT(shift);
> - else
> - mt6397->wake_mask[reg] &= ~BIT(shift);
> -
> - return 0;
> -}
> -#else
> -#define mt6397_irq_set_wake NULL
> -#endif
> -
> -static struct irq_chip mt6397_irq_chip = {
> - .name = "mt6397-irq",
> - .irq_bus_lock = mt6397_irq_lock,
> - .irq_bus_sync_unlock = mt6397_irq_sync_unlock,
> - .irq_enable = mt6397_irq_enable,
> - .irq_disable = mt6397_irq_disable,
> - .irq_set_wake = mt6397_irq_set_wake,
> -};
> -
> -static void mt6397_irq_handle_reg(struct mt6397_chip *mt6397, int reg,
> - int irqbase)
> -{
> - unsigned int status;
> - int i, irq, ret;
> -
> - ret = regmap_read(mt6397->regmap, reg, &status);
> - if (ret) {
> - dev_err(mt6397->dev, "Failed to read irq status: %d\n", ret);
> - return;
> - }
> -
> - for (i = 0; i < 16; i++) {
> - if (status & BIT(i)) {
> - irq = irq_find_mapping(mt6397->irq_domain, irqbase + i);
> - if (irq)
> - handle_nested_irq(irq);
> - }
> - }
> -
> - regmap_write(mt6397->regmap, reg, status);
> -}
> -
> -static irqreturn_t mt6397_irq_thread(int irq, void *data)
> -{
> - struct mt6397_chip *mt6397 = data;
> -
> - mt6397_irq_handle_reg(mt6397, mt6397->int_status[0], 0);
> - mt6397_irq_handle_reg(mt6397, mt6397->int_status[1], 16);
> -
> - return IRQ_HANDLED;
> -}
> -
> -static int mt6397_irq_domain_map(struct irq_domain *d, unsigned int irq,
> - irq_hw_number_t hw)
> -{
> - struct mt6397_chip *mt6397 = d->host_data;
> -
> - irq_set_chip_data(irq, mt6397);
> - irq_set_chip_and_handler(irq, &mt6397_irq_chip, handle_level_irq);
> - irq_set_nested_thread(irq, 1);
> - irq_set_noprobe(irq);
> -
> - return 0;
> -}
> -
> -static const struct irq_domain_ops mt6397_irq_domain_ops = {
> - .map = mt6397_irq_domain_map,
> -};
> -
> -static int mt6397_irq_init(struct mt6397_chip *mt6397)
> -{
> - int ret;
> -
> - mutex_init(&mt6397->irqlock);
> -
> - /* Mask all interrupt sources */
> - regmap_write(mt6397->regmap, mt6397->int_con[0], 0x0);
> - regmap_write(mt6397->regmap, mt6397->int_con[1], 0x0);
> -
> - mt6397->irq_domain = irq_domain_add_linear(mt6397->dev->of_node,
> - MT6397_IRQ_NR, &mt6397_irq_domain_ops, mt6397);
> - if (!mt6397->irq_domain) {
> - dev_err(mt6397->dev, "could not create irq domain\n");
> - return -ENOMEM;
> - }
> -
> - ret = devm_request_threaded_irq(mt6397->dev, mt6397->irq, NULL,
> - mt6397_irq_thread, IRQF_ONESHOT, "mt6397-pmic", mt6397);
> - if (ret) {
> - dev_err(mt6397->dev, "failed to register irq=%d; err: %d\n",
> - mt6397->irq, ret);
> - return ret;
> - }
> -
> - return 0;
> -}
> -
> #ifdef CONFIG_PM_SLEEP
> static int mt6397_irq_suspend(struct device *dev)
> {
> diff --git a/drivers/mfd/mt6397-irq.c b/drivers/mfd/mt6397-irq.c
> new file mode 100644
> index 000000000000..b2d3ce1f3115
> --- /dev/null
> +++ b/drivers/mfd/mt6397-irq.c
> @@ -0,0 +1,181 @@
> +// SPDX-License-Identifier: GPL-2.0
> +//
> +// Copyright (c) 2019 MediaTek Inc.
> +
> +#include <linux/interrupt.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/of_device.h>
> +#include <linux/of_irq.h>
> +#include <linux/platform_device.h>
> +#include <linux/regmap.h>
> +#include <linux/mfd/mt6323/core.h>
> +#include <linux/mfd/mt6323/registers.h>
> +#include <linux/mfd/mt6397/core.h>
> +#include <linux/mfd/mt6397/registers.h>
> +
> +static void mt6397_irq_lock(struct irq_data *data)
> +{
> + struct mt6397_chip *mt6397 = irq_data_get_irq_chip_data(data);
> +
> + mutex_lock(&mt6397->irqlock);
> +}
> +
> +static void mt6397_irq_sync_unlock(struct irq_data *data)
> +{
> + struct mt6397_chip *mt6397 = irq_data_get_irq_chip_data(data);
> +
> + regmap_write(mt6397->regmap, mt6397->int_con[0],
> + mt6397->irq_masks_cur[0]);
> + regmap_write(mt6397->regmap, mt6397->int_con[1],
> + mt6397->irq_masks_cur[1]);
> +
> + mutex_unlock(&mt6397->irqlock);
> +}
> +
> +static void mt6397_irq_disable(struct irq_data *data)
> +{
> + struct mt6397_chip *mt6397 = irq_data_get_irq_chip_data(data);
> + int shift = data->hwirq & 0xf;
> + int reg = data->hwirq >> 4;
> +
> + mt6397->irq_masks_cur[reg] &= ~BIT(shift);
> +}
> +
> +static void mt6397_irq_enable(struct irq_data *data)
> +{
> + struct mt6397_chip *mt6397 = irq_data_get_irq_chip_data(data);
> + int shift = data->hwirq & 0xf;
> + int reg = data->hwirq >> 4;
> +
> + mt6397->irq_masks_cur[reg] |= BIT(shift);
> +}
> +
> +#ifdef CONFIG_PM_SLEEP
> +static int mt6397_irq_set_wake(struct irq_data *irq_data, unsigned int on)
> +{
> + struct mt6397_chip *mt6397 = irq_data_get_irq_chip_data(irq_data);
> + int shift = irq_data->hwirq & 0xf;
> + int reg = irq_data->hwirq >> 4;
> +
> + if (on)
> + mt6397->wake_mask[reg] |= BIT(shift);
> + else
> + mt6397->wake_mask[reg] &= ~BIT(shift);
> +
> + return 0;
> +}
> +#else
> +#define mt6397_irq_set_wake NULL
> +#endif
> +
> +static struct irq_chip mt6397_irq_chip = {
> + .name = "mt6397-irq",
> + .irq_bus_lock = mt6397_irq_lock,
> + .irq_bus_sync_unlock = mt6397_irq_sync_unlock,
> + .irq_enable = mt6397_irq_enable,
> + .irq_disable = mt6397_irq_disable,
> + .irq_set_wake = mt6397_irq_set_wake,
> +};
> +
> +static void mt6397_irq_handle_reg(struct mt6397_chip *mt6397, int reg,
> + int irqbase)
> +{
> + unsigned int status;
> + int i, irq, ret;
> +
> + ret = regmap_read(mt6397->regmap, reg, &status);
> + if (ret) {
> + dev_err(mt6397->dev, "Failed to read irq status: %d\n", ret);
> + return;
> + }
> +
> + for (i = 0; i < 16; i++) {
> + if (status & BIT(i)) {
> + irq = irq_find_mapping(mt6397->irq_domain, irqbase + i);
> + if (irq)
> + handle_nested_irq(irq);
> + }
> + }
> +
> + regmap_write(mt6397->regmap, reg, status);
> +}
> +
> +static irqreturn_t mt6397_irq_thread(int irq, void *data)
> +{
> + struct mt6397_chip *mt6397 = data;
> +
> + mt6397_irq_handle_reg(mt6397, mt6397->int_status[0], 0);
> + mt6397_irq_handle_reg(mt6397, mt6397->int_status[1], 16);
> +
> + return IRQ_HANDLED;
> +}
> +
> +static int mt6397_irq_domain_map(struct irq_domain *d, unsigned int irq,
> + irq_hw_number_t hw)
> +{
> + struct mt6397_chip *mt6397 = d->host_data;
> +
> + irq_set_chip_data(irq, mt6397);
> + irq_set_chip_and_handler(irq, &mt6397_irq_chip, handle_level_irq);
> + irq_set_nested_thread(irq, 1);
> + irq_set_noprobe(irq);
> +
> + return 0;
> +}
> +
> +static const struct irq_domain_ops mt6397_irq_domain_ops = {
> + .map = mt6397_irq_domain_map,
> +};
> +
> +int mt6397_irq_init(struct mt6397_chip *chip)
> +{
> + int ret;
> +
> + mutex_init(&chip->irqlock);
> +
> + switch (chip->chip_id) {
> + case MT6323_CHIP_ID:
> + chip->int_con[0] = MT6323_INT_CON0;
> + chip->int_con[1] = MT6323_INT_CON1;
> + chip->int_status[0] = MT6323_INT_STATUS0;
> + chip->int_status[1] = MT6323_INT_STATUS1;
> + break;
> +
> + case MT6391_CHIP_ID:
> + case MT6397_CHIP_ID:
> + chip->int_con[0] = MT6397_INT_CON0;
> + chip->int_con[1] = MT6397_INT_CON1;
> + chip->int_status[0] = MT6397_INT_STATUS0;
> + chip->int_status[1] = MT6397_INT_STATUS1;
> + break;
> +
> + default:
> + dev_err(chip->dev, "unsupported chip: 0x%x\n", chip->chip_id);
> + return -ENODEV;
> + }
This switch/case wasn't there before the move... Doesn't that now
duplicates with code in mt6397_probe, or am I missing something?
> +
> + /* Mask all interrupt sources */
> + regmap_write(chip->regmap, chip->int_con[0], 0x0);
> + regmap_write(chip->regmap, chip->int_con[1], 0x0);
> +
> + chip->irq_domain = irq_domain_add_linear(chip->dev->of_node,
> + MT6397_IRQ_NR,
> + &mt6397_irq_domain_ops,
> + chip);
> + if (!chip->irq_domain) {
> + dev_err(chip->dev, "could not create irq domain\n");
> + return -ENOMEM;
> + }
> +
> + ret = devm_request_threaded_irq(chip->dev, chip->irq, NULL,
> + mt6397_irq_thread, IRQF_ONESHOT,
> + "mt6397-pmic", chip);
> + if (ret) {
> + dev_err(chip->dev, "failed to register irq=%d; err: %d\n",
> + chip->irq, ret);
> + return ret;
> + }
> +
> + return 0;
> +}
> diff --git a/include/linux/mfd/mt6397/core.h b/include/linux/mfd/mt6397/core.h
> index d678f526e498..93f9f5235575 100644
> --- a/include/linux/mfd/mt6397/core.h
> +++ b/include/linux/mfd/mt6397/core.h
> @@ -15,6 +15,12 @@
> #ifndef __MFD_MT6397_CORE_H__
> #define __MFD_MT6397_CORE_H__
>
> +enum chip_id {
> + MT6323_CHIP_ID = 0x23,
> + MT6391_CHIP_ID = 0x91,
> + MT6397_CHIP_ID = 0x97,
> +};
> +
> enum mt6397_irq_numbers {
> MT6397_IRQ_SPKL_AB = 0,
> MT6397_IRQ_SPKR_AB,
> @@ -62,6 +68,9 @@ struct mt6397_chip {
> u16 irq_masks_cache[2];
> u16 int_con[2];
> u16 int_status[2];
> + u16 chip_id;
> };
>
> +int mt6397_irq_init(struct mt6397_chip *chip);
> +
> #endif /* __MFD_MT6397_CORE_H__ */
> --
> 2.18.0
>
>
> _______________________________________________
> Linux-mediatek mailing list
> Linux-mediatek@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 22+ messages in thread* Re: [PATCH v3 02/10] mfd: mt6397: extract irq related code from core driver
2019-05-07 5:11 ` Nicolas Boichat
@ 2019-05-07 5:16 ` Nicolas Boichat
0 siblings, 0 replies; 22+ messages in thread
From: Nicolas Boichat @ 2019-05-07 5:16 UTC (permalink / raw)
To: Hsin-Hsiung Wang
Cc: Lee Jones, Rob Herring, Mark Brown, Matthias Brugger,
Mark Rutland, Alessandro Zummo, Alexandre Belloni,
srv_heupstream, devicetree, Sean Wang, Liam Girdwood, lkml,
moderated list:ARM/Mediatek SoC support, linux-arm Mailing List,
Eddie Huang, linux-rtc, Claire Chang
On Tue, May 7, 2019 at 2:11 PM Nicolas Boichat <drinkcat@chromium.org> wrote:
>
> On Fri, May 3, 2019 at 6:33 PM Hsin-Hsiung Wang
> <hsin-hsiung.wang@mediatek.com> wrote:
> >
> > In order to support different types of irq design, we decide to add
> > separate irq drivers for different design and keep mt6397 mfd core
> > simple and reusable to all generations of PMICs so far.
> >
> > Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>
> > ---
> > drivers/mfd/Makefile | 3 +-
> > drivers/mfd/mt6397-core.c | 146 --------------------------
> > drivers/mfd/mt6397-irq.c | 181 ++++++++++++++++++++++++++++++++
> > include/linux/mfd/mt6397/core.h | 9 ++
> > 4 files changed, 192 insertions(+), 147 deletions(-)
> > create mode 100644 drivers/mfd/mt6397-irq.c
> >
> > diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
> > index b4569ed7f3f3..ab1e228b5a2f 100644
> > --- a/drivers/mfd/Makefile
> > +++ b/drivers/mfd/Makefile
> > @@ -234,7 +234,8 @@ obj-$(CONFIG_INTEL_SOC_PMIC) += intel-soc-pmic.o
> > obj-$(CONFIG_INTEL_SOC_PMIC_BXTWC) += intel_soc_pmic_bxtwc.o
> > obj-$(CONFIG_INTEL_SOC_PMIC_CHTWC) += intel_soc_pmic_chtwc.o
> > obj-$(CONFIG_INTEL_SOC_PMIC_CHTDC_TI) += intel_soc_pmic_chtdc_ti.o
> > -obj-$(CONFIG_MFD_MT6397) += mt6397-core.o
> > +mt6397-objs := mt6397-core.o mt6397-irq.o
> > +obj-$(CONFIG_MFD_MT6397) += mt6397.o
> >
> > obj-$(CONFIG_MFD_ALTERA_A10SR) += altera-a10sr.o
> > obj-$(CONFIG_MFD_STPMIC1) += stpmic1.o
> > diff --git a/drivers/mfd/mt6397-core.c b/drivers/mfd/mt6397-core.c
> > index c9393bc86743..c80f0449fe7e 100644
> > --- a/drivers/mfd/mt6397-core.c
> > +++ b/drivers/mfd/mt6397-core.c
> > @@ -26,10 +26,6 @@
> > #define MT6397_RTC_BASE 0xe000
> > #define MT6397_RTC_SIZE 0x3e
> >
> > -#define MT6323_CHIP_ID 0x23
> > -#define MT6391_CHIP_ID 0x91
> > -#define MT6397_CHIP_ID 0x97
> > -
> > static const struct resource mt6397_rtc_resources[] = {
> > {
> > .start = MT6397_RTC_BASE,
> > @@ -94,148 +90,6 @@ static const struct mfd_cell mt6397_devs[] = {
> > }
> > };
> >
> > -static void mt6397_irq_lock(struct irq_data *data)
> > -{
> > - struct mt6397_chip *mt6397 = irq_data_get_irq_chip_data(data);
> > -
> > - mutex_lock(&mt6397->irqlock);
> > -}
> > -
> > -static void mt6397_irq_sync_unlock(struct irq_data *data)
> > -{
> > - struct mt6397_chip *mt6397 = irq_data_get_irq_chip_data(data);
> > -
> > - regmap_write(mt6397->regmap, mt6397->int_con[0],
> > - mt6397->irq_masks_cur[0]);
> > - regmap_write(mt6397->regmap, mt6397->int_con[1],
> > - mt6397->irq_masks_cur[1]);
> > -
> > - mutex_unlock(&mt6397->irqlock);
> > -}
> > -
> > -static void mt6397_irq_disable(struct irq_data *data)
> > -{
> > - struct mt6397_chip *mt6397 = irq_data_get_irq_chip_data(data);
> > - int shift = data->hwirq & 0xf;
> > - int reg = data->hwirq >> 4;
> > -
> > - mt6397->irq_masks_cur[reg] &= ~BIT(shift);
> > -}
> > -
> > -static void mt6397_irq_enable(struct irq_data *data)
> > -{
> > - struct mt6397_chip *mt6397 = irq_data_get_irq_chip_data(data);
> > - int shift = data->hwirq & 0xf;
> > - int reg = data->hwirq >> 4;
> > -
> > - mt6397->irq_masks_cur[reg] |= BIT(shift);
> > -}
> > -
> > -#ifdef CONFIG_PM_SLEEP
> > -static int mt6397_irq_set_wake(struct irq_data *irq_data, unsigned int on)
> > -{
> > - struct mt6397_chip *mt6397 = irq_data_get_irq_chip_data(irq_data);
> > - int shift = irq_data->hwirq & 0xf;
> > - int reg = irq_data->hwirq >> 4;
> > -
> > - if (on)
> > - mt6397->wake_mask[reg] |= BIT(shift);
> > - else
> > - mt6397->wake_mask[reg] &= ~BIT(shift);
> > -
> > - return 0;
> > -}
> > -#else
> > -#define mt6397_irq_set_wake NULL
> > -#endif
> > -
> > -static struct irq_chip mt6397_irq_chip = {
> > - .name = "mt6397-irq",
> > - .irq_bus_lock = mt6397_irq_lock,
> > - .irq_bus_sync_unlock = mt6397_irq_sync_unlock,
> > - .irq_enable = mt6397_irq_enable,
> > - .irq_disable = mt6397_irq_disable,
> > - .irq_set_wake = mt6397_irq_set_wake,
> > -};
> > -
> > -static void mt6397_irq_handle_reg(struct mt6397_chip *mt6397, int reg,
> > - int irqbase)
> > -{
> > - unsigned int status;
> > - int i, irq, ret;
> > -
> > - ret = regmap_read(mt6397->regmap, reg, &status);
> > - if (ret) {
> > - dev_err(mt6397->dev, "Failed to read irq status: %d\n", ret);
> > - return;
> > - }
> > -
> > - for (i = 0; i < 16; i++) {
> > - if (status & BIT(i)) {
> > - irq = irq_find_mapping(mt6397->irq_domain, irqbase + i);
> > - if (irq)
> > - handle_nested_irq(irq);
> > - }
> > - }
> > -
> > - regmap_write(mt6397->regmap, reg, status);
> > -}
> > -
> > -static irqreturn_t mt6397_irq_thread(int irq, void *data)
> > -{
> > - struct mt6397_chip *mt6397 = data;
> > -
> > - mt6397_irq_handle_reg(mt6397, mt6397->int_status[0], 0);
> > - mt6397_irq_handle_reg(mt6397, mt6397->int_status[1], 16);
> > -
> > - return IRQ_HANDLED;
> > -}
> > -
> > -static int mt6397_irq_domain_map(struct irq_domain *d, unsigned int irq,
> > - irq_hw_number_t hw)
> > -{
> > - struct mt6397_chip *mt6397 = d->host_data;
> > -
> > - irq_set_chip_data(irq, mt6397);
> > - irq_set_chip_and_handler(irq, &mt6397_irq_chip, handle_level_irq);
> > - irq_set_nested_thread(irq, 1);
> > - irq_set_noprobe(irq);
> > -
> > - return 0;
> > -}
> > -
> > -static const struct irq_domain_ops mt6397_irq_domain_ops = {
> > - .map = mt6397_irq_domain_map,
> > -};
> > -
> > -static int mt6397_irq_init(struct mt6397_chip *mt6397)
> > -{
> > - int ret;
> > -
> > - mutex_init(&mt6397->irqlock);
> > -
> > - /* Mask all interrupt sources */
> > - regmap_write(mt6397->regmap, mt6397->int_con[0], 0x0);
> > - regmap_write(mt6397->regmap, mt6397->int_con[1], 0x0);
> > -
> > - mt6397->irq_domain = irq_domain_add_linear(mt6397->dev->of_node,
> > - MT6397_IRQ_NR, &mt6397_irq_domain_ops, mt6397);
> > - if (!mt6397->irq_domain) {
> > - dev_err(mt6397->dev, "could not create irq domain\n");
> > - return -ENOMEM;
> > - }
> > -
> > - ret = devm_request_threaded_irq(mt6397->dev, mt6397->irq, NULL,
> > - mt6397_irq_thread, IRQF_ONESHOT, "mt6397-pmic", mt6397);
> > - if (ret) {
> > - dev_err(mt6397->dev, "failed to register irq=%d; err: %d\n",
> > - mt6397->irq, ret);
> > - return ret;
> > - }
> > -
> > - return 0;
> > -}
> > -
> > #ifdef CONFIG_PM_SLEEP
> > static int mt6397_irq_suspend(struct device *dev)
> > {
> > diff --git a/drivers/mfd/mt6397-irq.c b/drivers/mfd/mt6397-irq.c
> > new file mode 100644
> > index 000000000000..b2d3ce1f3115
> > --- /dev/null
> > +++ b/drivers/mfd/mt6397-irq.c
> > @@ -0,0 +1,181 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +//
> > +// Copyright (c) 2019 MediaTek Inc.
> > +
> > +#include <linux/interrupt.h>
> > +#include <linux/module.h>
> > +#include <linux/of.h>
> > +#include <linux/of_device.h>
> > +#include <linux/of_irq.h>
> > +#include <linux/platform_device.h>
> > +#include <linux/regmap.h>
> > +#include <linux/mfd/mt6323/core.h>
> > +#include <linux/mfd/mt6323/registers.h>
> > +#include <linux/mfd/mt6397/core.h>
> > +#include <linux/mfd/mt6397/registers.h>
> > +
> > +static void mt6397_irq_lock(struct irq_data *data)
> > +{
> > + struct mt6397_chip *mt6397 = irq_data_get_irq_chip_data(data);
> > +
> > + mutex_lock(&mt6397->irqlock);
> > +}
> > +
> > +static void mt6397_irq_sync_unlock(struct irq_data *data)
> > +{
> > + struct mt6397_chip *mt6397 = irq_data_get_irq_chip_data(data);
> > +
> > + regmap_write(mt6397->regmap, mt6397->int_con[0],
> > + mt6397->irq_masks_cur[0]);
> > + regmap_write(mt6397->regmap, mt6397->int_con[1],
> > + mt6397->irq_masks_cur[1]);
> > +
> > + mutex_unlock(&mt6397->irqlock);
> > +}
> > +
> > +static void mt6397_irq_disable(struct irq_data *data)
> > +{
> > + struct mt6397_chip *mt6397 = irq_data_get_irq_chip_data(data);
> > + int shift = data->hwirq & 0xf;
> > + int reg = data->hwirq >> 4;
> > +
> > + mt6397->irq_masks_cur[reg] &= ~BIT(shift);
> > +}
> > +
> > +static void mt6397_irq_enable(struct irq_data *data)
> > +{
> > + struct mt6397_chip *mt6397 = irq_data_get_irq_chip_data(data);
> > + int shift = data->hwirq & 0xf;
> > + int reg = data->hwirq >> 4;
> > +
> > + mt6397->irq_masks_cur[reg] |= BIT(shift);
> > +}
> > +
> > +#ifdef CONFIG_PM_SLEEP
> > +static int mt6397_irq_set_wake(struct irq_data *irq_data, unsigned int on)
> > +{
> > + struct mt6397_chip *mt6397 = irq_data_get_irq_chip_data(irq_data);
> > + int shift = irq_data->hwirq & 0xf;
> > + int reg = irq_data->hwirq >> 4;
> > +
> > + if (on)
> > + mt6397->wake_mask[reg] |= BIT(shift);
> > + else
> > + mt6397->wake_mask[reg] &= ~BIT(shift);
> > +
> > + return 0;
> > +}
> > +#else
> > +#define mt6397_irq_set_wake NULL
> > +#endif
> > +
> > +static struct irq_chip mt6397_irq_chip = {
> > + .name = "mt6397-irq",
> > + .irq_bus_lock = mt6397_irq_lock,
> > + .irq_bus_sync_unlock = mt6397_irq_sync_unlock,
> > + .irq_enable = mt6397_irq_enable,
> > + .irq_disable = mt6397_irq_disable,
> > + .irq_set_wake = mt6397_irq_set_wake,
> > +};
> > +
> > +static void mt6397_irq_handle_reg(struct mt6397_chip *mt6397, int reg,
> > + int irqbase)
> > +{
> > + unsigned int status;
> > + int i, irq, ret;
> > +
> > + ret = regmap_read(mt6397->regmap, reg, &status);
> > + if (ret) {
> > + dev_err(mt6397->dev, "Failed to read irq status: %d\n", ret);
> > + return;
> > + }
> > +
> > + for (i = 0; i < 16; i++) {
> > + if (status & BIT(i)) {
> > + irq = irq_find_mapping(mt6397->irq_domain, irqbase + i);
> > + if (irq)
> > + handle_nested_irq(irq);
> > + }
> > + }
> > +
> > + regmap_write(mt6397->regmap, reg, status);
> > +}
> > +
> > +static irqreturn_t mt6397_irq_thread(int irq, void *data)
> > +{
> > + struct mt6397_chip *mt6397 = data;
> > +
> > + mt6397_irq_handle_reg(mt6397, mt6397->int_status[0], 0);
> > + mt6397_irq_handle_reg(mt6397, mt6397->int_status[1], 16);
> > +
> > + return IRQ_HANDLED;
> > +}
> > +
> > +static int mt6397_irq_domain_map(struct irq_domain *d, unsigned int irq,
> > + irq_hw_number_t hw)
> > +{
> > + struct mt6397_chip *mt6397 = d->host_data;
> > +
> > + irq_set_chip_data(irq, mt6397);
> > + irq_set_chip_and_handler(irq, &mt6397_irq_chip, handle_level_irq);
> > + irq_set_nested_thread(irq, 1);
> > + irq_set_noprobe(irq);
> > +
> > + return 0;
> > +}
> > +
> > +static const struct irq_domain_ops mt6397_irq_domain_ops = {
> > + .map = mt6397_irq_domain_map,
> > +};
> > +
> > +int mt6397_irq_init(struct mt6397_chip *chip)
> > +{
> > + int ret;
> > +
> > + mutex_init(&chip->irqlock);
> > +
> > + switch (chip->chip_id) {
> > + case MT6323_CHIP_ID:
> > + chip->int_con[0] = MT6323_INT_CON0;
> > + chip->int_con[1] = MT6323_INT_CON1;
> > + chip->int_status[0] = MT6323_INT_STATUS0;
> > + chip->int_status[1] = MT6323_INT_STATUS1;
> > + break;
> > +
> > + case MT6391_CHIP_ID:
> > + case MT6397_CHIP_ID:
> > + chip->int_con[0] = MT6397_INT_CON0;
> > + chip->int_con[1] = MT6397_INT_CON1;
> > + chip->int_status[0] = MT6397_INT_STATUS0;
> > + chip->int_status[1] = MT6397_INT_STATUS1;
> > + break;
> > +
> > + default:
> > + dev_err(chip->dev, "unsupported chip: 0x%x\n", chip->chip_id);
> > + return -ENODEV;
> > + }
>
> This switch/case wasn't there before the move... Doesn't that now
> duplicates with code in mt6397_probe, or am I missing something?
Oh, I see, that's deleted in patch 3/10
(https://patchwork.kernel.org/patch/10928163/). That still does not
look right. I'd have another patch before this that moves the
switch/case statement, and keep this as a simple move with no
functional difference.
> > +
> > + /* Mask all interrupt sources */
> > + regmap_write(chip->regmap, chip->int_con[0], 0x0);
> > + regmap_write(chip->regmap, chip->int_con[1], 0x0);
> > +
> > + chip->irq_domain = irq_domain_add_linear(chip->dev->of_node,
> > + MT6397_IRQ_NR,
> > + &mt6397_irq_domain_ops,
> > + chip);
> > + if (!chip->irq_domain) {
> > + dev_err(chip->dev, "could not create irq domain\n");
> > + return -ENOMEM;
> > + }
> > +
> > + ret = devm_request_threaded_irq(chip->dev, chip->irq, NULL,
> > + mt6397_irq_thread, IRQF_ONESHOT,
> > + "mt6397-pmic", chip);
> > + if (ret) {
> > + dev_err(chip->dev, "failed to register irq=%d; err: %d\n",
> > + chip->irq, ret);
> > + return ret;
> > + }
> > +
> > + return 0;
> > +}
> > diff --git a/include/linux/mfd/mt6397/core.h b/include/linux/mfd/mt6397/core.h
> > index d678f526e498..93f9f5235575 100644
> > --- a/include/linux/mfd/mt6397/core.h
> > +++ b/include/linux/mfd/mt6397/core.h
> > @@ -15,6 +15,12 @@
> > #ifndef __MFD_MT6397_CORE_H__
> > #define __MFD_MT6397_CORE_H__
> >
> > +enum chip_id {
> > + MT6323_CHIP_ID = 0x23,
> > + MT6391_CHIP_ID = 0x91,
> > + MT6397_CHIP_ID = 0x97,
> > +};
> > +
> > enum mt6397_irq_numbers {
> > MT6397_IRQ_SPKL_AB = 0,
> > MT6397_IRQ_SPKR_AB,
> > @@ -62,6 +68,9 @@ struct mt6397_chip {
> > u16 irq_masks_cache[2];
> > u16 int_con[2];
> > u16 int_status[2];
> > + u16 chip_id;
> > };
> >
> > +int mt6397_irq_init(struct mt6397_chip *chip);
> > +
> > #endif /* __MFD_MT6397_CORE_H__ */
> > --
> > 2.18.0
> >
> >
> > _______________________________________________
> > Linux-mediatek mailing list
> > Linux-mediatek@lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH v3 03/10] mfd: mt6397: modify suspend/resume behavior
2019-05-03 9:31 [PATCH v3 00/10] Add Support for MediaTek PMIC MT6358 Hsin-Hsiung Wang
2019-05-03 9:31 ` [PATCH v3 01/10] mfd: mt6397: clean up code Hsin-Hsiung Wang
2019-05-03 9:31 ` [PATCH v3 02/10] mfd: mt6397: extract irq related code from core driver Hsin-Hsiung Wang
@ 2019-05-03 9:31 ` Hsin-Hsiung Wang
2019-05-03 9:31 ` [PATCH v3 04/10] dt-bindings: mfd: Add compatible for the MediaTek MT6358 PMIC Hsin-Hsiung Wang
` (6 subsequent siblings)
9 siblings, 0 replies; 22+ messages in thread
From: Hsin-Hsiung Wang @ 2019-05-03 9:31 UTC (permalink / raw)
To: Lee Jones, Rob Herring, Mark Brown, Matthias Brugger
Cc: Liam Girdwood, Mark Rutland, Eddie Huang, Sean Wang,
Alessandro Zummo, Alexandre Belloni, Hsin-Hsiung Wang,
devicetree, linux-arm-kernel, linux-mediatek, linux-kernel,
linux-rtc, srv_heupstream
Some pmics don't need backup interrupt settings, so we change to use
pm notifier for the pmics which are necessary to store settings.
Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>
---
drivers/mfd/mt6397-core.c | 89 ++++++++++++++-------------------
drivers/mfd/mt6397-irq.c | 33 ++++++++++++
include/linux/mfd/mt6397/core.h | 3 ++
3 files changed, 73 insertions(+), 52 deletions(-)
diff --git a/drivers/mfd/mt6397-core.c b/drivers/mfd/mt6397-core.c
index c80f0449fe7e..719687a341de 100644
--- a/drivers/mfd/mt6397-core.c
+++ b/drivers/mfd/mt6397-core.c
@@ -12,7 +12,6 @@
* GNU General Public License for more details.
*/
-#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/of_irq.h>
@@ -90,40 +89,27 @@ static const struct mfd_cell mt6397_devs[] = {
}
};
-#ifdef CONFIG_PM_SLEEP
-static int mt6397_irq_suspend(struct device *dev)
-{
- struct mt6397_chip *chip = dev_get_drvdata(dev);
-
- regmap_write(chip->regmap, chip->int_con[0], chip->wake_mask[0]);
- regmap_write(chip->regmap, chip->int_con[1], chip->wake_mask[1]);
-
- enable_irq_wake(chip->irq);
-
- return 0;
-}
-
-static int mt6397_irq_resume(struct device *dev)
-{
- struct mt6397_chip *chip = dev_get_drvdata(dev);
-
- regmap_write(chip->regmap, chip->int_con[0], chip->irq_masks_cur[0]);
- regmap_write(chip->regmap, chip->int_con[1], chip->irq_masks_cur[1]);
-
- disable_irq_wake(chip->irq);
+struct chip_data {
+ u32 cid_addr;
+ u32 cid_shift;
+};
- return 0;
-}
-#endif
+static const struct chip_data mt6323_core = {
+ .cid_addr = MT6323_CID,
+ .cid_shift = 0,
+};
-static SIMPLE_DEV_PM_OPS(mt6397_pm_ops, mt6397_irq_suspend,
- mt6397_irq_resume);
+static const struct chip_data mt6397_core = {
+ .cid_addr = MT6397_CID,
+ .cid_shift = 0,
+};
static int mt6397_probe(struct platform_device *pdev)
{
int ret;
unsigned int id;
struct mt6397_chip *pmic;
+ const struct chip_data *pmic_core;
pmic = devm_kzalloc(&pdev->dev, sizeof(*pmic), GFP_KERNEL);
if (!pmic)
@@ -139,28 +125,30 @@ static int mt6397_probe(struct platform_device *pdev)
if (!pmic->regmap)
return -ENODEV;
- platform_set_drvdata(pdev, pmic);
+ pmic_core = of_device_get_match_data(&pdev->dev);
+ if (!pmic_core)
+ return -ENODEV;
- ret = regmap_read(pmic->regmap, MT6397_CID, &id);
+ ret = regmap_read(pmic->regmap, pmic_core->cid_addr, &id);
if (ret) {
- dev_err(pmic->dev, "Failed to read chip id: %d\n", ret);
+ dev_err(&pdev->dev, "Failed to read chip id: %d\n", ret);
return ret;
}
+ pmic->chip_id = (id >> pmic_core->cid_shift) & 0xff;
+
+ platform_set_drvdata(pdev, pmic);
+
pmic->irq = platform_get_irq(pdev, 0);
if (pmic->irq <= 0)
return pmic->irq;
- switch (id & 0xff) {
- case MT6323_CHIP_ID:
- pmic->int_con[0] = MT6323_INT_CON0;
- pmic->int_con[1] = MT6323_INT_CON1;
- pmic->int_status[0] = MT6323_INT_STATUS0;
- pmic->int_status[1] = MT6323_INT_STATUS1;
- ret = mt6397_irq_init(pmic);
- if (ret)
- return ret;
+ ret = mt6397_irq_init(pmic);
+ if (ret)
+ return ret;
+ switch (pmic->chip_id) {
+ case MT6323_CHIP_ID:
ret = devm_mfd_add_devices(&pdev->dev, -1, mt6323_devs,
ARRAY_SIZE(mt6323_devs), NULL,
0, pmic->irq_domain);
@@ -168,21 +156,13 @@ static int mt6397_probe(struct platform_device *pdev)
case MT6391_CHIP_ID:
case MT6397_CHIP_ID:
- pmic->int_con[0] = MT6397_INT_CON0;
- pmic->int_con[1] = MT6397_INT_CON1;
- pmic->int_status[0] = MT6397_INT_STATUS0;
- pmic->int_status[1] = MT6397_INT_STATUS1;
- ret = mt6397_irq_init(pmic);
- if (ret)
- return ret;
-
ret = devm_mfd_add_devices(&pdev->dev, -1, mt6397_devs,
ARRAY_SIZE(mt6397_devs), NULL,
0, pmic->irq_domain);
break;
default:
- dev_err(&pdev->dev, "unsupported chip: %d\n", id);
+ dev_err(&pdev->dev, "unsupported chip: %d\n", pmic->chip_id);
return -ENODEV;
}
@@ -195,9 +175,15 @@ static int mt6397_probe(struct platform_device *pdev)
}
static const struct of_device_id mt6397_of_match[] = {
- { .compatible = "mediatek,mt6397" },
- { .compatible = "mediatek,mt6323" },
- { }
+ {
+ .compatible = "mediatek,mt6323",
+ .data = &mt6323_core,
+ }, {
+ .compatible = "mediatek,mt6397",
+ .data = &mt6397_core,
+ }, {
+ /* sentinel */
+ }
};
MODULE_DEVICE_TABLE(of, mt6397_of_match);
@@ -212,7 +198,6 @@ static struct platform_driver mt6397_driver = {
.driver = {
.name = "mt6397",
.of_match_table = of_match_ptr(mt6397_of_match),
- .pm = &mt6397_pm_ops,
},
.id_table = mt6397_id,
};
diff --git a/drivers/mfd/mt6397-irq.c b/drivers/mfd/mt6397-irq.c
index b2d3ce1f3115..669e93df54ef 100644
--- a/drivers/mfd/mt6397-irq.c
+++ b/drivers/mfd/mt6397-irq.c
@@ -9,6 +9,7 @@
#include <linux/of_irq.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
+#include <linux/suspend.h>
#include <linux/mfd/mt6323/core.h>
#include <linux/mfd/mt6323/registers.h>
#include <linux/mfd/mt6397/core.h>
@@ -128,6 +129,36 @@ static const struct irq_domain_ops mt6397_irq_domain_ops = {
.map = mt6397_irq_domain_map,
};
+static int mt6397_irq_pm_notifier(struct notifier_block *notifier,
+ unsigned long pm_event, void *unused)
+{
+ struct mt6397_chip *chip =
+ container_of(notifier, struct mt6397_chip, pm_nb);
+
+ switch (pm_event) {
+ case PM_SUSPEND_PREPARE:
+ regmap_write(chip->regmap,
+ chip->int_con[0], chip->wake_mask[0]);
+ regmap_write(chip->regmap,
+ chip->int_con[1], chip->wake_mask[1]);
+ enable_irq_wake(chip->irq);
+ break;
+
+ case PM_POST_SUSPEND:
+ regmap_write(chip->regmap,
+ chip->int_con[0], chip->irq_masks_cur[0]);
+ regmap_write(chip->regmap,
+ chip->int_con[1], chip->irq_masks_cur[1]);
+ disable_irq_wake(chip->irq);
+ break;
+
+ default:
+ break;
+ }
+
+ return NOTIFY_DONE;
+}
+
int mt6397_irq_init(struct mt6397_chip *chip)
{
int ret;
@@ -159,6 +190,7 @@ int mt6397_irq_init(struct mt6397_chip *chip)
regmap_write(chip->regmap, chip->int_con[0], 0x0);
regmap_write(chip->regmap, chip->int_con[1], 0x0);
+ chip->pm_nb.notifier_call = mt6397_irq_pm_notifier;
chip->irq_domain = irq_domain_add_linear(chip->dev->of_node,
MT6397_IRQ_NR,
&mt6397_irq_domain_ops,
@@ -177,5 +209,6 @@ int mt6397_irq_init(struct mt6397_chip *chip)
return ret;
}
+ register_pm_notifier(&chip->pm_nb);
return 0;
}
diff --git a/include/linux/mfd/mt6397/core.h b/include/linux/mfd/mt6397/core.h
index 93f9f5235575..0cb5d4b0895b 100644
--- a/include/linux/mfd/mt6397/core.h
+++ b/include/linux/mfd/mt6397/core.h
@@ -15,6 +15,8 @@
#ifndef __MFD_MT6397_CORE_H__
#define __MFD_MT6397_CORE_H__
+#include <linux/notifier.h>
+
enum chip_id {
MT6323_CHIP_ID = 0x23,
MT6391_CHIP_ID = 0x91,
@@ -60,6 +62,7 @@ enum mt6397_irq_numbers {
struct mt6397_chip {
struct device *dev;
struct regmap *regmap;
+ struct notifier_block pm_nb;
int irq;
struct irq_domain *irq_domain;
struct mutex irqlock;
--
2.18.0
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH v3 04/10] dt-bindings: mfd: Add compatible for the MediaTek MT6358 PMIC
2019-05-03 9:31 [PATCH v3 00/10] Add Support for MediaTek PMIC MT6358 Hsin-Hsiung Wang
` (2 preceding siblings ...)
2019-05-03 9:31 ` [PATCH v3 03/10] mfd: mt6397: modify suspend/resume behavior Hsin-Hsiung Wang
@ 2019-05-03 9:31 ` Hsin-Hsiung Wang
2019-05-07 5:24 ` Nicolas Boichat
2019-05-13 15:04 ` Rob Herring
2019-05-03 9:31 ` [PATCH v3 05/10] regulator: Add document for MT6358 regulator Hsin-Hsiung Wang
` (5 subsequent siblings)
9 siblings, 2 replies; 22+ messages in thread
From: Hsin-Hsiung Wang @ 2019-05-03 9:31 UTC (permalink / raw)
To: Lee Jones, Rob Herring, Mark Brown, Matthias Brugger
Cc: Liam Girdwood, Mark Rutland, Eddie Huang, Sean Wang,
Alessandro Zummo, Alexandre Belloni, Hsin-Hsiung Wang,
devicetree, linux-arm-kernel, linux-mediatek, linux-kernel,
linux-rtc, srv_heupstream
This adds compatible for the MediaTek MT6358 PMIC.
Acked-for-MFD-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>
---
Documentation/devicetree/bindings/mfd/mt6397.txt | 11 ++++++++---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/mfd/mt6397.txt b/Documentation/devicetree/bindings/mfd/mt6397.txt
index 0ebd08af777d..62f1c17c7738 100644
--- a/Documentation/devicetree/bindings/mfd/mt6397.txt
+++ b/Documentation/devicetree/bindings/mfd/mt6397.txt
@@ -17,22 +17,27 @@ Documentation/devicetree/bindings/soc/mediatek/pwrap.txt
This document describes the binding for MFD device and its sub module.
Required properties:
-compatible: "mediatek,mt6397" or "mediatek,mt6323"
+compatible:
+ "mediatek,mt6323" for PMIC MT6323
+ "mediatek,mt6358" for PMIC MT6358
+ "mediatek,mt6397" for PMIC MT6397
Optional subnodes:
- rtc
Required properties:
- - compatible: "mediatek,mt6397-rtc"
+ - compatible: "mediatek,mt6397-rtc" or "mediatek,mt6358-rtc"
- regulators
Required properties:
- compatible: "mediatek,mt6397-regulator"
see Documentation/devicetree/bindings/regulator/mt6397-regulator.txt
+ - compatible: "mediatek,mt6358-regulator"
+ see Documentation/devicetree/bindings/regulator/mt6358-regulator.txt
- compatible: "mediatek,mt6323-regulator"
see Documentation/devicetree/bindings/regulator/mt6323-regulator.txt
- codec
Required properties:
- - compatible: "mediatek,mt6397-codec"
+ - compatible: "mediatek,mt6397-codec" or "mediatek,mt6358-sound"
- clk
Required properties:
- compatible: "mediatek,mt6397-clk"
--
2.18.0
^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [PATCH v3 04/10] dt-bindings: mfd: Add compatible for the MediaTek MT6358 PMIC
2019-05-03 9:31 ` [PATCH v3 04/10] dt-bindings: mfd: Add compatible for the MediaTek MT6358 PMIC Hsin-Hsiung Wang
@ 2019-05-07 5:24 ` Nicolas Boichat
2019-08-02 13:28 ` Hsin-hsiung Wang
2019-05-13 15:04 ` Rob Herring
1 sibling, 1 reply; 22+ messages in thread
From: Nicolas Boichat @ 2019-05-07 5:24 UTC (permalink / raw)
To: Hsin-Hsiung Wang
Cc: Lee Jones, Rob Herring, Mark Brown, Matthias Brugger,
Mark Rutland, Alessandro Zummo, Alexandre Belloni,
srv_heupstream, devicetree, Sean Wang, Liam Girdwood, lkml,
moderated list:ARM/Mediatek SoC support, linux-arm Mailing List,
Eddie Huang, linux-rtc
On Fri, May 3, 2019 at 6:34 PM Hsin-Hsiung Wang
<hsin-hsiung.wang@mediatek.com> wrote:
>
> This adds compatible for the MediaTek MT6358 PMIC.
>
> Acked-for-MFD-by: Lee Jones <lee.jones@linaro.org>
> Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>
> ---
> Documentation/devicetree/bindings/mfd/mt6397.txt | 11 ++++++++---
> 1 file changed, 8 insertions(+), 3 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/mfd/mt6397.txt b/Documentation/devicetree/bindings/mfd/mt6397.txt
> index 0ebd08af777d..62f1c17c7738 100644
> --- a/Documentation/devicetree/bindings/mfd/mt6397.txt
> +++ b/Documentation/devicetree/bindings/mfd/mt6397.txt
> @@ -17,22 +17,27 @@ Documentation/devicetree/bindings/soc/mediatek/pwrap.txt
> This document describes the binding for MFD device and its sub module.
>
> Required properties:
> -compatible: "mediatek,mt6397" or "mediatek,mt6323"
> +compatible:
> + "mediatek,mt6323" for PMIC MT6323
> + "mediatek,mt6358" for PMIC MT6358
> + "mediatek,mt6397" for PMIC MT6397
>
> Optional subnodes:
>
> - rtc
> Required properties:
> - - compatible: "mediatek,mt6397-rtc"
> + - compatible: "mediatek,mt6397-rtc" or "mediatek,mt6358-rtc"
> - regulators
> Required properties:
> - compatible: "mediatek,mt6397-regulator"
> see Documentation/devicetree/bindings/regulator/mt6397-regulator.txt
> + - compatible: "mediatek,mt6358-regulator"
> + see Documentation/devicetree/bindings/regulator/mt6358-regulator.txt
> - compatible: "mediatek,mt6323-regulator"
> see Documentation/devicetree/bindings/regulator/mt6323-regulator.txt
> - codec
> Required properties:
> - - compatible: "mediatek,mt6397-codec"
> + - compatible: "mediatek,mt6397-codec" or "mediatek,mt6358-sound"
Sean had a question about this
(https://patchwork.kernel.org/patch/10846669/#22524299):
"why didn't we use a more consistent naming as mt6358-codec?"
> - clk
> Required properties:
> - compatible: "mediatek,mt6397-clk"
> --
> 2.18.0
>
>
> _______________________________________________
> Linux-mediatek mailing list
> Linux-mediatek@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v3 04/10] dt-bindings: mfd: Add compatible for the MediaTek MT6358 PMIC
2019-05-07 5:24 ` Nicolas Boichat
@ 2019-08-02 13:28 ` Hsin-hsiung Wang
0 siblings, 0 replies; 22+ messages in thread
From: Hsin-hsiung Wang @ 2019-08-02 13:28 UTC (permalink / raw)
To: Nicolas Boichat
Cc: Lee Jones, Rob Herring, Mark Brown, Matthias Brugger,
Mark Rutland, Alessandro Zummo, Alexandre Belloni,
srv_heupstream, devicetree, Sean Wang, Liam Girdwood, lkml,
moderated list:ARM/Mediatek SoC support, linux-arm Mailing List,
Eddie Huang, linux-rtc
Hi Nicolas,
On Tue, 2019-05-07 at 14:24 +0900, Nicolas Boichat wrote:
> On Fri, May 3, 2019 at 6:34 PM Hsin-Hsiung Wang
> <hsin-hsiung.wang@mediatek.com> wrote:
> >
...
> > This adds compatible for the MediaTek MT6358 PMIC.
> >
> > Acked-for-MFD-by: Lee Jones <lee.jones@linaro.org>
> > Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>
> > ---
> > Documentation/devicetree/bindings/mfd/mt6397.txt | 11 ++++++++---
> > 1 file changed, 8 insertions(+), 3 deletions(-)
> >
> > diff --git a/Documentation/devicetree/bindings/mfd/mt6397.txt b/Documentation/devicetree/bindings/mfd/mt6397.txt
> > index 0ebd08af777d..62f1c17c7738 100644
> > --- a/Documentation/devicetree/bindings/mfd/mt6397.txt
> > +++ b/Documentation/devicetree/bindings/mfd/mt6397.txt
> > @@ -17,22 +17,27 @@ Documentation/devicetree/bindings/soc/mediatek/pwrap.txt
> > This document describes the binding for MFD device and its sub module.
> >
> > Required properties:
> > -compatible: "mediatek,mt6397" or "mediatek,mt6323"
> > +compatible:
> > + "mediatek,mt6323" for PMIC MT6323
> > + "mediatek,mt6358" for PMIC MT6358
> > + "mediatek,mt6397" for PMIC MT6397
> >
> > Optional subnodes:
> >
> > - rtc
> > Required properties:
> > - - compatible: "mediatek,mt6397-rtc"
> > + - compatible: "mediatek,mt6397-rtc" or "mediatek,mt6358-rtc"
> > - regulators
> > Required properties:
> > - compatible: "mediatek,mt6397-regulator"
> > see Documentation/devicetree/bindings/regulator/mt6397-regulator.txt
> > + - compatible: "mediatek,mt6358-regulator"
> > + see Documentation/devicetree/bindings/regulator/mt6358-regulator.txt
> > - compatible: "mediatek,mt6323-regulator"
> > see Documentation/devicetree/bindings/regulator/mt6323-regulator.txt
> > - codec
> > Required properties:
> > - - compatible: "mediatek,mt6397-codec"
> > + - compatible: "mediatek,mt6397-codec" or "mediatek,mt6358-sound"
>
> Sean had a question about this
> (https://patchwork.kernel.org/patch/10846669/#22524299):
> "why didn't we use a more consistent naming as mt6358-codec?"
>
The compatible name, "mediatek,mt6358-sound", is already in mt6358 audio
driver which is already in the upstream codebase.
After discussing with audio owner, we will submit another patch to fix
it.
Thanks.
> > - clk
> > Required properties:
> > - compatible: "mediatek,mt6397-clk"
> > --
> > 2.18.0
> >
> >
> > _______________________________________________
> > Linux-mediatek mailing list
> > Linux-mediatek@lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v3 04/10] dt-bindings: mfd: Add compatible for the MediaTek MT6358 PMIC
2019-05-03 9:31 ` [PATCH v3 04/10] dt-bindings: mfd: Add compatible for the MediaTek MT6358 PMIC Hsin-Hsiung Wang
2019-05-07 5:24 ` Nicolas Boichat
@ 2019-05-13 15:04 ` Rob Herring
1 sibling, 0 replies; 22+ messages in thread
From: Rob Herring @ 2019-05-13 15:04 UTC (permalink / raw)
To: Hsin-Hsiung Wang
Cc: Lee Jones, Mark Brown, Matthias Brugger, Liam Girdwood,
Mark Rutland, Eddie Huang, Sean Wang, Alessandro Zummo,
Alexandre Belloni, devicetree, linux-arm-kernel, linux-mediatek,
linux-kernel, linux-rtc, srv_heupstream
On Fri, May 03, 2019 at 05:31:11PM +0800, Hsin-Hsiung Wang wrote:
> This adds compatible for the MediaTek MT6358 PMIC.
>
> Acked-for-MFD-by: Lee Jones <lee.jones@linaro.org>
> Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>
> ---
> Documentation/devicetree/bindings/mfd/mt6397.txt | 11 ++++++++---
> 1 file changed, 8 insertions(+), 3 deletions(-)
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH v3 05/10] regulator: Add document for MT6358 regulator
2019-05-03 9:31 [PATCH v3 00/10] Add Support for MediaTek PMIC MT6358 Hsin-Hsiung Wang
` (3 preceding siblings ...)
2019-05-03 9:31 ` [PATCH v3 04/10] dt-bindings: mfd: Add compatible for the MediaTek MT6358 PMIC Hsin-Hsiung Wang
@ 2019-05-03 9:31 ` Hsin-Hsiung Wang
2019-05-13 15:06 ` Rob Herring
2019-05-03 9:31 ` [PATCH v3 06/10] mfd: Add support for the MediaTek MT6358 PMIC Hsin-Hsiung Wang
` (4 subsequent siblings)
9 siblings, 1 reply; 22+ messages in thread
From: Hsin-Hsiung Wang @ 2019-05-03 9:31 UTC (permalink / raw)
To: Lee Jones, Rob Herring, Mark Brown, Matthias Brugger
Cc: Liam Girdwood, Mark Rutland, Eddie Huang, Sean Wang,
Alessandro Zummo, Alexandre Belloni, Hsin-Hsiung Wang,
devicetree, linux-arm-kernel, linux-mediatek, linux-kernel,
linux-rtc, srv_heupstream
add dt-binding document for MediaTek MT6358 PMIC
Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>
---
.../bindings/regulator/mt6358-regulator.txt | 358 ++++++++++++++++++
1 file changed, 358 insertions(+)
create mode 100644 Documentation/devicetree/bindings/regulator/mt6358-regulator.txt
diff --git a/Documentation/devicetree/bindings/regulator/mt6358-regulator.txt b/Documentation/devicetree/bindings/regulator/mt6358-regulator.txt
new file mode 100644
index 000000000000..9a90a92f2d7e
--- /dev/null
+++ b/Documentation/devicetree/bindings/regulator/mt6358-regulator.txt
@@ -0,0 +1,358 @@
+MediaTek MT6358 Regulator
+
+All voltage regulators provided by the MT6358 PMIC are described as the
+subnodes of the MT6358 regulators node. Each regulator is named according
+to its regulator type, buck_<name> and ldo_<name>. The definition for each
+of these nodes is defined using the standard binding for regulators at
+Documentation/devicetree/bindings/regulator/regulator.txt.
+
+The valid names for regulators are::
+BUCK:
+ buck_vdram1, buck_vcore, buck_vpa, buck_vproc11, buck_vproc12, buck_vgpu,
+ buck_vs2, buck_vmodem, buck_vs1
+LDO:
+ ldo_vdram2, ldo_vsim1, ldo_vibr, ldo_vrf12, ldo_vio18, ldo_vusb, ldo_vcamio,
+ ldo_vcamd, ldo_vcn18, ldo_vfe28, ldo_vsram_proc11, ldo_vcn28, ldo_vsram_others,
+ ldo_vsram_gpu, ldo_vxo22, ldo_vefuse, ldo_vaux18, ldo_vmch, ldo_vbif28,
+ ldo_vsram_proc12, ldo_vcama1, ldo_vemc, ldo_vio28, ldo_va12, ldo_vrf18,
+ ldo_vcn33_bt, ldo_vcn33_wifi, ldo_vcama2, ldo_vmc, ldo_vldo28, ldo_vaud28,
+ ldo_vsim2
+
+Example:
+
+ pmic {
+ compatible = "mediatek,mt6358";
+
+ mt6358regulator: mt6358regulator {
+ compatible = "mediatek,mt6358-regulator";
+
+ mt6358_vdram1_reg: buck_vdram1 {
+ regulator-compatible = "buck_vdram1";
+ regulator-name = "vdram1";
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <2087500>;
+ regulator-ramp-delay = <12500>;
+ regulator-enable-ramp-delay = <0>;
+ regulator-always-on;
+ };
+
+ mt6358_vcore_reg: buck_vcore {
+ regulator-name = "vcore";
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1293750>;
+ regulator-ramp-delay = <6250>;
+ regulator-enable-ramp-delay = <200>;
+ regulator-always-on;
+ };
+
+ mt6358_vpa_reg: buck_vpa {
+ regulator-name = "vpa";
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <3650000>;
+ regulator-ramp-delay = <50000>;
+ regulator-enable-ramp-delay = <250>;
+ };
+
+ mt6358_vproc11_reg: buck_vproc11 {
+ regulator-name = "vproc11";
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1293750>;
+ regulator-ramp-delay = <6250>;
+ regulator-enable-ramp-delay = <200>;
+ regulator-always-on;
+ };
+
+ mt6358_vproc12_reg: buck_vproc12 {
+ regulator-name = "vproc12";
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1293750>;
+ regulator-ramp-delay = <6250>;
+ regulator-enable-ramp-delay = <200>;
+ regulator-always-on;
+ };
+
+ mt6358_vgpu_reg: buck_vgpu {
+ regulator-name = "vgpu";
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1293750>;
+ regulator-ramp-delay = <6250>;
+ regulator-enable-ramp-delay = <200>;
+ };
+
+ mt6358_vs2_reg: buck_vs2 {
+ regulator-name = "vs2";
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <2087500>;
+ regulator-ramp-delay = <12500>;
+ regulator-enable-ramp-delay = <0>;
+ regulator-always-on;
+ };
+
+ mt6358_vmodem_reg: buck_vmodem {
+ regulator-name = "vmodem";
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1293750>;
+ regulator-ramp-delay = <6250>;
+ regulator-enable-ramp-delay = <900>;
+ regulator-always-on;
+ };
+
+ mt6358_vs1_reg: buck_vs1 {
+ regulator-name = "vs1";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <2587500>;
+ regulator-ramp-delay = <12500>;
+ regulator-enable-ramp-delay = <0>;
+ regulator-always-on;
+ };
+
+ mt6358_vdram2_reg: ldo_vdram2 {
+ regulator-name = "vdram2";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-enable-ramp-delay = <3300>;
+ };
+
+ mt6358_vsim1_reg: ldo_vsim1 {
+ regulator-name = "vsim1";
+ regulator-min-microvolt = <1700000>;
+ regulator-max-microvolt = <3100000>;
+ regulator-enable-ramp-delay = <540>;
+ };
+
+ mt6358_vibr_reg: ldo_vibr {
+ regulator-name = "vibr";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-enable-ramp-delay = <60>;
+ };
+
+ mt6358_vrf12_reg: ldo_vrf12 {
+ compatible = "regulator-fixed";
+ regulator-name = "vrf12";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-enable-ramp-delay = <120>;
+ };
+
+ mt6358_vio18_reg: ldo_vio18 {
+ compatible = "regulator-fixed";
+ regulator-name = "vio18";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-enable-ramp-delay = <2700>;
+ regulator-always-on;
+ };
+
+ mt6358_vusb_reg: ldo_vusb {
+ regulator-name = "vusb";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3100000>;
+ regulator-enable-ramp-delay = <270>;
+ regulator-always-on;
+ };
+
+ mt6358_vcamio_reg: ldo_vcamio {
+ compatible = "regulator-fixed";
+ regulator-name = "vcamio";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-enable-ramp-delay = <270>;
+ };
+
+ mt6358_vcamd_reg: ldo_vcamd {
+ regulator-name = "vcamd";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-enable-ramp-delay = <270>;
+ };
+
+ mt6358_vcn18_reg: ldo_vcn18 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcn18";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-enable-ramp-delay = <270>;
+ };
+
+ mt6358_vfe28_reg: ldo_vfe28 {
+ compatible = "regulator-fixed";
+ regulator-name = "vfe28";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-enable-ramp-delay = <270>;
+ };
+
+ mt6358_vsram_proc11_reg: ldo_vsram_proc11 {
+ regulator-name = "vsram_proc11";
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1293750>;
+ regulator-ramp-delay = <6250>;
+ regulator-enable-ramp-delay = <240>;
+ regulator-always-on;
+ };
+
+ mt6358_vcn28_reg: ldo_vcn28 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcn28";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-enable-ramp-delay = <270>;
+ };
+
+ mt6358_vsram_others_reg: ldo_vsram_others {
+ regulator-name = "vsram_others";
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1293750>;
+ regulator-ramp-delay = <6250>;
+ regulator-enable-ramp-delay = <240>;
+ regulator-always-on;
+ };
+
+ mt6358_vsram_gpu_reg: ldo_vsram_gpu {
+ regulator-name = "vsram_gpu";
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1293750>;
+ regulator-ramp-delay = <6250>;
+ regulator-enable-ramp-delay = <240>;
+ };
+
+ mt6358_vxo22_reg: ldo_vxo22 {
+ compatible = "regulator-fixed";
+ regulator-name = "vxo22";
+ regulator-min-microvolt = <2200000>;
+ regulator-max-microvolt = <2200000>;
+ regulator-enable-ramp-delay = <120>;
+ regulator-always-on;
+ };
+
+ mt6358_vefuse_reg: ldo_vefuse {
+ regulator-name = "vefuse";
+ regulator-min-microvolt = <1700000>;
+ regulator-max-microvolt = <1900000>;
+ regulator-enable-ramp-delay = <270>;
+ };
+
+ mt6358_vaux18_reg: ldo_vaux18 {
+ compatible = "regulator-fixed";
+ regulator-name = "vaux18";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-enable-ramp-delay = <270>;
+ };
+
+ mt6358_vmch_reg: ldo_vmch {
+ regulator-name = "vmch";
+ regulator-min-microvolt = <2900000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-enable-ramp-delay = <60>;
+ };
+
+ mt6358_vbif28_reg: ldo_vbif28 {
+ compatible = "regulator-fixed";
+ regulator-name = "vbif28";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-enable-ramp-delay = <270>;
+ };
+
+ mt6358_vsram_proc12_reg: ldo_vsram_proc12 {
+ regulator-name = "vsram_proc12";
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1293750>;
+ regulator-ramp-delay = <6250>;
+ regulator-enable-ramp-delay = <240>;
+ regulator-always-on;
+ };
+
+ mt6358_vcama1_reg: ldo_vcama1 {
+ regulator-name = "vcama1";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-enable-ramp-delay = <270>;
+ };
+
+ mt6358_vemc_reg: ldo_vemc {
+ regulator-name = "vemc";
+ regulator-min-microvolt = <2900000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-enable-ramp-delay = <60>;
+ regulator-always-on;
+ };
+
+ mt6358_vio28_reg: ldo_vio28 {
+ compatible = "regulator-fixed";
+ regulator-name = "vio28";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-enable-ramp-delay = <270>;
+ };
+
+ mt6358_va12_reg: ldo_va12 {
+ compatible = "regulator-fixed";
+ regulator-name = "va12";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-enable-ramp-delay = <270>;
+ regulator-always-on;
+ };
+
+ mt6358_vrf18_reg: ldo_vrf18 {
+ compatible = "regulator-fixed";
+ regulator-name = "vrf18";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-enable-ramp-delay = <120>;
+ };
+
+ mt6358_vcn33_bt_reg: ldo_vcn33_bt {
+ regulator-name = "vcn33_bt";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3500000>;
+ regulator-enable-ramp-delay = <270>;
+ };
+
+ mt6358_vcn33_wifi_reg: ldo_vcn33_wifi {
+ regulator-name = "vcn33_wifi";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3500000>;
+ regulator-enable-ramp-delay = <270>;
+ };
+
+ mt6358_vcama2_reg: ldo_vcama2 {
+ regulator-name = "vcama2";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-enable-ramp-delay = <270>;
+ };
+
+ mt6358_vmc_reg: ldo_vmc {
+ regulator-name = "vmc";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-enable-ramp-delay = <60>;
+ };
+
+ mt6358_vldo28_reg: ldo_vldo28 {
+ regulator-name = "vldo28";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-enable-ramp-delay = <270>;
+ };
+
+ mt6358_vaud28_reg: ldo_vaud28 {
+ compatible = "regulator-fixed";
+ regulator-name = "vaud28";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-enable-ramp-delay = <270>;
+ };
+
+ mt6358_vsim2_reg: ldo_vsim2 {
+ regulator-name = "vsim2";
+ regulator-min-microvolt = <1700000>;
+ regulator-max-microvolt = <3100000>;
+ regulator-enable-ramp-delay = <540>;
+ };
+ };
+ };
--
2.18.0
^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [PATCH v3 05/10] regulator: Add document for MT6358 regulator
2019-05-03 9:31 ` [PATCH v3 05/10] regulator: Add document for MT6358 regulator Hsin-Hsiung Wang
@ 2019-05-13 15:06 ` Rob Herring
0 siblings, 0 replies; 22+ messages in thread
From: Rob Herring @ 2019-05-13 15:06 UTC (permalink / raw)
To: Hsin-Hsiung Wang
Cc: Lee Jones, Mark Brown, Matthias Brugger, Liam Girdwood,
Mark Rutland, Eddie Huang, Sean Wang, Alessandro Zummo,
Alexandre Belloni, devicetree, linux-arm-kernel, linux-mediatek,
linux-kernel, linux-rtc, srv_heupstream
On Fri, May 03, 2019 at 05:31:12PM +0800, Hsin-Hsiung Wang wrote:
> add dt-binding document for MediaTek MT6358 PMIC
>
> Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>
> ---
> .../bindings/regulator/mt6358-regulator.txt | 358 ++++++++++++++++++
> 1 file changed, 358 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/regulator/mt6358-regulator.txt
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH v3 06/10] mfd: Add support for the MediaTek MT6358 PMIC
2019-05-03 9:31 [PATCH v3 00/10] Add Support for MediaTek PMIC MT6358 Hsin-Hsiung Wang
` (4 preceding siblings ...)
2019-05-03 9:31 ` [PATCH v3 05/10] regulator: Add document for MT6358 regulator Hsin-Hsiung Wang
@ 2019-05-03 9:31 ` Hsin-Hsiung Wang
2019-05-07 5:34 ` Nicolas Boichat
2019-05-03 9:31 ` [PATCH v3 07/10] regulator: mt6358: Add support for MT6358 regulator Hsin-Hsiung Wang
` (3 subsequent siblings)
9 siblings, 1 reply; 22+ messages in thread
From: Hsin-Hsiung Wang @ 2019-05-03 9:31 UTC (permalink / raw)
To: Lee Jones, Rob Herring, Mark Brown, Matthias Brugger
Cc: Liam Girdwood, Mark Rutland, Eddie Huang, Sean Wang,
Alessandro Zummo, Alexandre Belloni, Hsin-Hsiung Wang,
devicetree, linux-arm-kernel, linux-mediatek, linux-kernel,
linux-rtc, srv_heupstream
This adds support for the MediaTek MT6358 PMIC. This is a
multifunction device with the following sub modules:
- Regulator
- RTC
- Codec
- Interrupt
It is interfaced to the host controller using SPI interface
by a proprietary hardware called PMIC wrapper or pwrap.
MT6358 MFD is a child device of the pwrap.
Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>
---
drivers/mfd/Makefile | 3 +-
drivers/mfd/mt6358-irq.c | 229 ++++++++++++++++++++++
drivers/mfd/mt6397-core.c | 64 +++++-
include/linux/mfd/mt6358/core.h | 158 +++++++++++++++
include/linux/mfd/mt6358/registers.h | 282 +++++++++++++++++++++++++++
include/linux/mfd/mt6397/core.h | 3 +
6 files changed, 737 insertions(+), 2 deletions(-)
create mode 100644 drivers/mfd/mt6358-irq.c
create mode 100644 include/linux/mfd/mt6358/core.h
create mode 100644 include/linux/mfd/mt6358/registers.h
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index ab1e228b5a2f..6e7b2b0951e7 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -234,7 +234,8 @@ obj-$(CONFIG_INTEL_SOC_PMIC) += intel-soc-pmic.o
obj-$(CONFIG_INTEL_SOC_PMIC_BXTWC) += intel_soc_pmic_bxtwc.o
obj-$(CONFIG_INTEL_SOC_PMIC_CHTWC) += intel_soc_pmic_chtwc.o
obj-$(CONFIG_INTEL_SOC_PMIC_CHTDC_TI) += intel_soc_pmic_chtdc_ti.o
-mt6397-objs := mt6397-core.o mt6397-irq.o
+
+mt6397-objs := mt6397-core.o mt6397-irq.o mt6358-irq.o
obj-$(CONFIG_MFD_MT6397) += mt6397.o
obj-$(CONFIG_MFD_ALTERA_A10SR) += altera-a10sr.o
diff --git a/drivers/mfd/mt6358-irq.c b/drivers/mfd/mt6358-irq.c
new file mode 100644
index 000000000000..a6e8252c3431
--- /dev/null
+++ b/drivers/mfd/mt6358-irq.c
@@ -0,0 +1,229 @@
+// SPDX-License-Identifier: GPL-2.0
+//
+// Copyright (c) 2019 MediaTek Inc.
+
+#include <linux/interrupt.h>
+#include <linux/mfd/mt6358/core.h>
+#include <linux/mfd/mt6358/registers.h>
+#include <linux/mfd/mt6397/core.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/of_irq.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+
+static struct irq_top_t mt6358_ints[] = {
+ MT6358_TOP_GEN(BUCK),
+ MT6358_TOP_GEN(LDO),
+ MT6358_TOP_GEN(PSC),
+ MT6358_TOP_GEN(SCK),
+ MT6358_TOP_GEN(BM),
+ MT6358_TOP_GEN(HK),
+ MT6358_TOP_GEN(AUD),
+ MT6358_TOP_GEN(MISC),
+};
+
+static void pmic_irq_enable(struct irq_data *data)
+{
+ unsigned int hwirq = irqd_to_hwirq(data);
+ struct mt6397_chip *chip = irq_data_get_irq_chip_data(data);
+ struct pmic_irq_data *irqd = chip->irq_data;
+
+ irqd->enable_hwirq[hwirq] = true;
+}
+
+static void pmic_irq_disable(struct irq_data *data)
+{
+ unsigned int hwirq = irqd_to_hwirq(data);
+ struct mt6397_chip *chip = irq_data_get_irq_chip_data(data);
+ struct pmic_irq_data *irqd = chip->irq_data;
+
+ irqd->enable_hwirq[hwirq] = false;
+}
+
+static void pmic_irq_lock(struct irq_data *data)
+{
+ struct mt6397_chip *chip = irq_data_get_irq_chip_data(data);
+
+ mutex_lock(&chip->irqlock);
+}
+
+static void pmic_irq_sync_unlock(struct irq_data *data)
+{
+ unsigned int i, top_gp, en_reg, int_regs, shift;
+ struct mt6397_chip *chip = irq_data_get_irq_chip_data(data);
+ struct pmic_irq_data *irqd = chip->irq_data;
+
+ for (i = 0; i < irqd->num_pmic_irqs; i++) {
+ if (irqd->enable_hwirq[i] == irqd->cache_hwirq[i])
+ continue;
+
+ top_gp = 0;
+ while ((top_gp + 1) < ARRAY_SIZE(mt6358_ints) && i >=
+ mt6358_ints[top_gp + 1].hwirq_base)
+ top_gp++;
+
+ if (top_gp >= ARRAY_SIZE(mt6358_ints)) {
+ mutex_unlock(&chip->irqlock);
+ dev_err(chip->dev,
+ "Failed to get top_group: %d\n", top_gp);
+ return;
+ }
+
+ int_regs = (i - mt6358_ints[top_gp].hwirq_base) /
+ MT6358_REG_WIDTH;
+ en_reg = mt6358_ints[top_gp].en_reg +
+ mt6358_ints[top_gp].en_reg_shift * int_regs;
+ shift = (i - mt6358_ints[top_gp].hwirq_base) % MT6358_REG_WIDTH;
+ regmap_update_bits(chip->regmap, en_reg, BIT(shift),
+ irqd->enable_hwirq[i] << shift);
+ irqd->cache_hwirq[i] = irqd->enable_hwirq[i];
+ }
+ mutex_unlock(&chip->irqlock);
+}
+
+static struct irq_chip mt6358_irq_chip = {
+ .name = "mt6358-irq",
+ .flags = IRQCHIP_SKIP_SET_WAKE,
+ .irq_enable = pmic_irq_enable,
+ .irq_disable = pmic_irq_disable,
+ .irq_bus_lock = pmic_irq_lock,
+ .irq_bus_sync_unlock = pmic_irq_sync_unlock,
+};
+
+static void mt6358_irq_sp_handler(struct mt6397_chip *chip,
+ unsigned int top_gp)
+{
+ unsigned int sta_reg, irq_status;
+ unsigned int hwirq, virq;
+ int ret, i, j;
+
+ for (i = 0; i < mt6358_ints[top_gp].num_int_regs; i++) {
+ sta_reg = mt6358_ints[top_gp].sta_reg +
+ mt6358_ints[top_gp].sta_reg_shift * i;
+ ret = regmap_read(chip->regmap, sta_reg, &irq_status);
+ if (ret) {
+ dev_err(chip->dev,
+ "Failed to read irq status: %d\n", ret);
+ return;
+ }
+
+ if (!irq_status)
+ continue;
+
+ for (j = 0; j < MT6358_REG_WIDTH ; j++) {
+ if ((irq_status & BIT(j)) == 0)
+ continue;
+ hwirq = mt6358_ints[top_gp].hwirq_base +
+ MT6358_REG_WIDTH * i + j;
+ virq = irq_find_mapping(chip->irq_domain, hwirq);
+ if (virq)
+ handle_nested_irq(virq);
+ }
+
+ regmap_write(chip->regmap, sta_reg, irq_status);
+ }
+}
+
+static irqreturn_t mt6358_irq_handler(int irq, void *data)
+{
+ struct mt6397_chip *chip = data;
+ struct pmic_irq_data *mt6358_irq_data = chip->irq_data;
+ unsigned int top_irq_status;
+ unsigned int i;
+ int ret;
+
+ ret = regmap_read(chip->regmap,
+ mt6358_irq_data->top_int_status_reg,
+ &top_irq_status);
+ if (ret) {
+ dev_err(chip->dev, "Can't read TOP_INT_STATUS ret=%d\n", ret);
+ return IRQ_NONE;
+ }
+
+ for (i = 0; i < mt6358_irq_data->num_top; i++) {
+ if (top_irq_status & BIT(mt6358_ints[i].top_offset))
+ mt6358_irq_sp_handler(chip, i);
+ }
+
+ return IRQ_HANDLED;
+}
+
+static int pmic_irq_domain_map(struct irq_domain *d, unsigned int irq,
+ irq_hw_number_t hw)
+{
+ struct mt6397_chip *mt6397 = d->host_data;
+
+ irq_set_chip_data(irq, mt6397);
+ irq_set_chip_and_handler(irq, &mt6358_irq_chip, handle_level_irq);
+ irq_set_nested_thread(irq, 1);
+ irq_set_noprobe(irq);
+
+ return 0;
+}
+
+static const struct irq_domain_ops mt6358_irq_domain_ops = {
+ .map = pmic_irq_domain_map,
+ .xlate = irq_domain_xlate_twocell,
+};
+
+int mt6358_irq_init(struct mt6397_chip *chip)
+{
+ int i, j, ret;
+ struct pmic_irq_data *irqd;
+
+ irqd = devm_kzalloc(chip->dev, sizeof(struct pmic_irq_data *),
+ GFP_KERNEL);
+ if (!irqd)
+ return -ENOMEM;
+
+ chip->irq_data = irqd;
+
+ mutex_init(&chip->irqlock);
+ irqd->top_int_status_reg = MT6358_TOP_INT_STATUS0;
+ irqd->num_pmic_irqs = MT6358_IRQ_NR;
+ irqd->num_top = ARRAY_SIZE(mt6358_ints);
+
+ irqd->enable_hwirq = devm_kcalloc(chip->dev,
+ irqd->num_pmic_irqs,
+ sizeof(bool),
+ GFP_KERNEL);
+ if (!irqd->enable_hwirq)
+ return -ENOMEM;
+
+ irqd->cache_hwirq = devm_kcalloc(chip->dev,
+ irqd->num_pmic_irqs,
+ sizeof(bool),
+ GFP_KERNEL);
+ if (!irqd->cache_hwirq)
+ return -ENOMEM;
+
+ /* Disable all interrupt for initializing */
+ for (i = 0; i < irqd->num_top; i++) {
+ for (j = 0; j < mt6358_ints[i].num_int_regs; j++)
+ regmap_write(chip->regmap,
+ mt6358_ints[i].en_reg +
+ mt6358_ints[i].en_reg_shift * j, 0);
+ }
+
+ chip->irq_domain = irq_domain_add_linear(chip->dev->of_node,
+ irqd->num_pmic_irqs,
+ &mt6358_irq_domain_ops, chip);
+ if (!chip->irq_domain) {
+ dev_err(chip->dev, "could not create irq domain\n");
+ return -ENODEV;
+ }
+
+ ret = devm_request_threaded_irq(chip->dev, chip->irq, NULL,
+ mt6358_irq_handler, IRQF_ONESHOT,
+ mt6358_irq_chip.name, chip);
+ if (ret) {
+ dev_err(chip->dev, "failed to register irq=%d; err: %d\n",
+ chip->irq, ret);
+ return ret;
+ }
+
+ enable_irq_wake(chip->irq);
+ return ret;
+}
diff --git a/drivers/mfd/mt6397-core.c b/drivers/mfd/mt6397-core.c
index 719687a341de..8fe61ea256ee 100644
--- a/drivers/mfd/mt6397-core.c
+++ b/drivers/mfd/mt6397-core.c
@@ -18,12 +18,36 @@
#include <linux/regmap.h>
#include <linux/mfd/core.h>
#include <linux/mfd/mt6323/core.h>
+#include <linux/mfd/mt6358/core.h>
#include <linux/mfd/mt6397/core.h>
#include <linux/mfd/mt6323/registers.h>
+#include <linux/mfd/mt6358/registers.h>
#include <linux/mfd/mt6397/registers.h>
+#define MT6358_RTC_BASE 0x0588
+#define MT6358_RTC_SIZE 0x3c
+#define MT6358_RTC_WRTGR_OFFSET 0x3a
#define MT6397_RTC_BASE 0xe000
#define MT6397_RTC_SIZE 0x3e
+#define MT6397_RTC_WRTGR_OFFSET 0x3c
+
+static const struct resource mt6358_rtc_resources[] = {
+ {
+ .start = MT6358_RTC_BASE,
+ .end = MT6358_RTC_BASE + MT6358_RTC_SIZE,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .start = MT6358_IRQ_RTC,
+ .end = MT6358_IRQ_RTC,
+ .flags = IORESOURCE_IRQ,
+ },
+ {
+ .start = MT6358_RTC_WRTGR_OFFSET,
+ .end = MT6358_RTC_WRTGR_OFFSET,
+ .flags = IORESOURCE_REG,
+ },
+};
static const struct resource mt6397_rtc_resources[] = {
{
@@ -36,6 +60,11 @@ static const struct resource mt6397_rtc_resources[] = {
.end = MT6397_IRQ_RTC,
.flags = IORESOURCE_IRQ,
},
+ {
+ .start = MT6397_RTC_WRTGR_OFFSET,
+ .end = MT6397_RTC_WRTGR_OFFSET,
+ .flags = IORESOURCE_REG,
+ },
};
static const struct resource mt6323_keys_resources[] = {
@@ -63,6 +92,21 @@ static const struct mfd_cell mt6323_devs[] = {
},
};
+static const struct mfd_cell mt6358_devs[] = {
+ {
+ .name = "mt6358-regulator",
+ .of_compatible = "mediatek,mt6358-regulator"
+ }, {
+ .name = "mt6397-rtc",
+ .num_resources = ARRAY_SIZE(mt6358_rtc_resources),
+ .resources = mt6358_rtc_resources,
+ .of_compatible = "mediatek,mt6358-rtc",
+ }, {
+ .name = "mt6358-sound",
+ .of_compatible = "mediatek,mt6358-sound"
+ },
+};
+
static const struct mfd_cell mt6397_devs[] = {
{
.name = "mt6397-rtc",
@@ -99,6 +143,11 @@ static const struct chip_data mt6323_core = {
.cid_shift = 0,
};
+static const struct chip_data mt6358_core = {
+ .cid_addr = MT6358_SWCID,
+ .cid_shift = 8,
+};
+
static const struct chip_data mt6397_core = {
.cid_addr = MT6397_CID,
.cid_shift = 0,
@@ -143,7 +192,11 @@ static int mt6397_probe(struct platform_device *pdev)
if (pmic->irq <= 0)
return pmic->irq;
- ret = mt6397_irq_init(pmic);
+ if (pmic->chip_id == MT6358_CHIP_ID)
+ ret = mt6358_irq_init(pmic);
+ else
+ ret = mt6397_irq_init(pmic);
+
if (ret)
return ret;
@@ -154,6 +207,12 @@ static int mt6397_probe(struct platform_device *pdev)
0, pmic->irq_domain);
break;
+ case MT6358_CHIP_ID:
+ ret = devm_mfd_add_devices(&pdev->dev, -1, mt6358_devs,
+ ARRAY_SIZE(mt6358_devs), NULL,
+ 0, pmic->irq_domain);
+ break;
+
case MT6391_CHIP_ID:
case MT6397_CHIP_ID:
ret = devm_mfd_add_devices(&pdev->dev, -1, mt6397_devs,
@@ -178,6 +237,9 @@ static const struct of_device_id mt6397_of_match[] = {
{
.compatible = "mediatek,mt6323",
.data = &mt6323_core,
+ }, {
+ .compatible = "mediatek,mt6358",
+ .data = &mt6358_core,
}, {
.compatible = "mediatek,mt6397",
.data = &mt6397_core,
diff --git a/include/linux/mfd/mt6358/core.h b/include/linux/mfd/mt6358/core.h
new file mode 100644
index 000000000000..05108617bc74
--- /dev/null
+++ b/include/linux/mfd/mt6358/core.h
@@ -0,0 +1,158 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ */
+
+#ifndef __MFD_MT6358_CORE_H__
+#define __MFD_MT6358_CORE_H__
+
+#define MT6358_REG_WIDTH 16
+
+struct irq_top_t {
+ int hwirq_base;
+ unsigned int num_int_regs;
+ unsigned int num_int_bits;
+ unsigned int en_reg;
+ unsigned int en_reg_shift;
+ unsigned int sta_reg;
+ unsigned int sta_reg_shift;
+ unsigned int top_offset;
+};
+
+struct pmic_irq_data {
+ unsigned int num_top;
+ unsigned int num_pmic_irqs;
+ unsigned short top_int_status_reg;
+ bool *enable_hwirq;
+ bool *cache_hwirq;
+};
+
+enum mt6358_irq_top_status_shift {
+ MT6358_BUCK_TOP = 0,
+ MT6358_LDO_TOP,
+ MT6358_PSC_TOP,
+ MT6358_SCK_TOP,
+ MT6358_BM_TOP,
+ MT6358_HK_TOP,
+ MT6358_AUD_TOP,
+ MT6358_MISC_TOP,
+};
+
+enum mt6358_irq_numbers {
+ MT6358_IRQ_VPROC11_OC = 0,
+ MT6358_IRQ_VPROC12_OC,
+ MT6358_IRQ_VCORE_OC,
+ MT6358_IRQ_VGPU_OC,
+ MT6358_IRQ_VMODEM_OC,
+ MT6358_IRQ_VDRAM1_OC,
+ MT6358_IRQ_VS1_OC,
+ MT6358_IRQ_VS2_OC,
+ MT6358_IRQ_VPA_OC,
+ MT6358_IRQ_VCORE_PREOC,
+ MT6358_IRQ_VFE28_OC = 16,
+ MT6358_IRQ_VXO22_OC,
+ MT6358_IRQ_VRF18_OC,
+ MT6358_IRQ_VRF12_OC,
+ MT6358_IRQ_VEFUSE_OC,
+ MT6358_IRQ_VCN33_OC,
+ MT6358_IRQ_VCN28_OC,
+ MT6358_IRQ_VCN18_OC,
+ MT6358_IRQ_VCAMA1_OC,
+ MT6358_IRQ_VCAMA2_OC,
+ MT6358_IRQ_VCAMD_OC,
+ MT6358_IRQ_VCAMIO_OC,
+ MT6358_IRQ_VLDO28_OC,
+ MT6358_IRQ_VA12_OC,
+ MT6358_IRQ_VAUX18_OC,
+ MT6358_IRQ_VAUD28_OC,
+ MT6358_IRQ_VIO28_OC,
+ MT6358_IRQ_VIO18_OC,
+ MT6358_IRQ_VSRAM_PROC11_OC,
+ MT6358_IRQ_VSRAM_PROC12_OC,
+ MT6358_IRQ_VSRAM_OTHERS_OC,
+ MT6358_IRQ_VSRAM_GPU_OC,
+ MT6358_IRQ_VDRAM2_OC,
+ MT6358_IRQ_VMC_OC,
+ MT6358_IRQ_VMCH_OC,
+ MT6358_IRQ_VEMC_OC,
+ MT6358_IRQ_VSIM1_OC,
+ MT6358_IRQ_VSIM2_OC,
+ MT6358_IRQ_VIBR_OC,
+ MT6358_IRQ_VUSB_OC,
+ MT6358_IRQ_VBIF28_OC,
+ MT6358_IRQ_PWRKEY = 48,
+ MT6358_IRQ_HOMEKEY,
+ MT6358_IRQ_PWRKEY_R,
+ MT6358_IRQ_HOMEKEY_R,
+ MT6358_IRQ_NI_LBAT_INT,
+ MT6358_IRQ_CHRDET,
+ MT6358_IRQ_CHRDET_EDGE,
+ MT6358_IRQ_VCDT_HV_DET,
+ MT6358_IRQ_RTC = 64,
+ MT6358_IRQ_FG_BAT0_H = 80,
+ MT6358_IRQ_FG_BAT0_L,
+ MT6358_IRQ_FG_CUR_H,
+ MT6358_IRQ_FG_CUR_L,
+ MT6358_IRQ_FG_ZCV,
+ MT6358_IRQ_FG_BAT1_H,
+ MT6358_IRQ_FG_BAT1_L,
+ MT6358_IRQ_FG_N_CHARGE_L,
+ MT6358_IRQ_FG_IAVG_H,
+ MT6358_IRQ_FG_IAVG_L,
+ MT6358_IRQ_FG_TIME_H,
+ MT6358_IRQ_FG_DISCHARGE,
+ MT6358_IRQ_FG_CHARGE,
+ MT6358_IRQ_BATON_LV = 96,
+ MT6358_IRQ_BATON_HT,
+ MT6358_IRQ_BATON_BAT_IN,
+ MT6358_IRQ_BATON_BAT_OUT,
+ MT6358_IRQ_BIF,
+ MT6358_IRQ_BAT_H = 112,
+ MT6358_IRQ_BAT_L,
+ MT6358_IRQ_BAT2_H,
+ MT6358_IRQ_BAT2_L,
+ MT6358_IRQ_BAT_TEMP_H,
+ MT6358_IRQ_BAT_TEMP_L,
+ MT6358_IRQ_AUXADC_IMP,
+ MT6358_IRQ_NAG_C_DLTV,
+ MT6358_IRQ_AUDIO = 128,
+ MT6358_IRQ_ACCDET = 133,
+ MT6358_IRQ_ACCDET_EINT0,
+ MT6358_IRQ_ACCDET_EINT1,
+ MT6358_IRQ_SPI_CMD_ALERT = 144,
+ MT6358_IRQ_NR,
+};
+
+#define MT6358_IRQ_BUCK_BASE MT6358_IRQ_VPROC11_OC
+#define MT6358_IRQ_LDO_BASE MT6358_IRQ_VFE28_OC
+#define MT6358_IRQ_PSC_BASE MT6358_IRQ_PWRKEY
+#define MT6358_IRQ_SCK_BASE MT6358_IRQ_RTC
+#define MT6358_IRQ_BM_BASE MT6358_IRQ_FG_BAT0_H
+#define MT6358_IRQ_HK_BASE MT6358_IRQ_BAT_H
+#define MT6358_IRQ_AUD_BASE MT6358_IRQ_AUDIO
+#define MT6358_IRQ_MISC_BASE MT6358_IRQ_SPI_CMD_ALERT
+
+#define MT6358_IRQ_BUCK_BITS (MT6358_IRQ_VCORE_PREOC - MT6358_IRQ_BUCK_BASE + 1)
+#define MT6358_IRQ_LDO_BITS (MT6358_IRQ_VBIF28_OC - MT6358_IRQ_LDO_BASE + 1)
+#define MT6358_IRQ_PSC_BITS (MT6358_IRQ_VCDT_HV_DET - MT6358_IRQ_PSC_BASE + 1)
+#define MT6358_IRQ_SCK_BITS (MT6358_IRQ_RTC - MT6358_IRQ_SCK_BASE + 1)
+#define MT6358_IRQ_BM_BITS (MT6358_IRQ_BIF - MT6358_IRQ_BM_BASE + 1)
+#define MT6358_IRQ_HK_BITS (MT6358_IRQ_NAG_C_DLTV - MT6358_IRQ_HK_BASE + 1)
+#define MT6358_IRQ_AUD_BITS (MT6358_IRQ_ACCDET_EINT1 - MT6358_IRQ_AUD_BASE + 1)
+#define MT6358_IRQ_MISC_BITS \
+ (MT6358_IRQ_SPI_CMD_ALERT - MT6358_IRQ_MISC_BASE + 1)
+
+#define MT6358_TOP_GEN(sp) \
+{ \
+ .hwirq_base = MT6358_IRQ_##sp##_BASE, \
+ .num_int_regs = \
+ ((MT6358_IRQ_##sp##_BITS - 1) / MT6358_REG_WIDTH) + 1, \
+ .num_int_bits = MT6358_IRQ_##sp##_BITS, \
+ .en_reg = MT6358_##sp##_TOP_INT_CON0, \
+ .en_reg_shift = 0x6, \
+ .sta_reg = MT6358_##sp##_TOP_INT_STATUS0, \
+ .sta_reg_shift = 0x2, \
+ .top_offset = MT6358_##sp##_TOP, \
+}
+
+#endif /* __MFD_MT6358_CORE_H__ */
diff --git a/include/linux/mfd/mt6358/registers.h b/include/linux/mfd/mt6358/registers.h
new file mode 100644
index 000000000000..ff5645b9348c
--- /dev/null
+++ b/include/linux/mfd/mt6358/registers.h
@@ -0,0 +1,282 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ */
+
+#ifndef __MFD_MT6358_REGISTERS_H__
+#define __MFD_MT6358_REGISTERS_H__
+
+/* PMIC Registers */
+#define MT6358_SWCID 0xa
+#define MT6358_MISC_TOP_INT_CON0 0x188
+#define MT6358_MISC_TOP_INT_STATUS0 0x194
+#define MT6358_TOP_INT_STATUS0 0x19e
+#define MT6358_SCK_TOP_INT_CON0 0x52e
+#define MT6358_SCK_TOP_INT_STATUS0 0x53a
+#define MT6358_EOSC_CALI_CON0 0x540
+#define MT6358_EOSC_CALI_CON1 0x542
+#define MT6358_RTC_MIX_CON0 0x544
+#define MT6358_RTC_MIX_CON1 0x546
+#define MT6358_RTC_MIX_CON2 0x548
+#define MT6358_RTC_DSN_ID 0x580
+#define MT6358_RTC_DSN_REV0 0x582
+#define MT6358_RTC_DBI 0x584
+#define MT6358_RTC_DXI 0x586
+#define MT6358_RTC_BBPU 0x588
+#define MT6358_RTC_IRQ_STA 0x58a
+#define MT6358_RTC_IRQ_EN 0x58c
+#define MT6358_RTC_CII_EN 0x58e
+#define MT6358_RTC_AL_MASK 0x590
+#define MT6358_RTC_TC_SEC 0x592
+#define MT6358_RTC_TC_MIN 0x594
+#define MT6358_RTC_TC_HOU 0x596
+#define MT6358_RTC_TC_DOM 0x598
+#define MT6358_RTC_TC_DOW 0x59a
+#define MT6358_RTC_TC_MTH 0x59c
+#define MT6358_RTC_TC_YEA 0x59e
+#define MT6358_RTC_AL_SEC 0x5a0
+#define MT6358_RTC_AL_MIN 0x5a2
+#define MT6358_RTC_AL_HOU 0x5a4
+#define MT6358_RTC_AL_DOM 0x5a6
+#define MT6358_RTC_AL_DOW 0x5a8
+#define MT6358_RTC_AL_MTH 0x5aa
+#define MT6358_RTC_AL_YEA 0x5ac
+#define MT6358_RTC_OSC32CON 0x5ae
+#define MT6358_RTC_POWERKEY1 0x5b0
+#define MT6358_RTC_POWERKEY2 0x5b2
+#define MT6358_RTC_PDN1 0x5b4
+#define MT6358_RTC_PDN2 0x5b6
+#define MT6358_RTC_SPAR0 0x5b8
+#define MT6358_RTC_SPAR1 0x5ba
+#define MT6358_RTC_PROT 0x5bc
+#define MT6358_RTC_DIFF 0x5be
+#define MT6358_RTC_CALI 0x5c0
+#define MT6358_RTC_WRTGR 0x5c2
+#define MT6358_RTC_CON 0x5c4
+#define MT6358_RTC_SEC_CTRL 0x5c6
+#define MT6358_RTC_INT_CNT 0x5c8
+#define MT6358_RTC_SEC_DAT0 0x5ca
+#define MT6358_RTC_SEC_DAT1 0x5cc
+#define MT6358_RTC_SEC_DAT2 0x5ce
+#define MT6358_RTC_SEC_DSN_ID 0x600
+#define MT6358_RTC_SEC_DSN_REV0 0x602
+#define MT6358_RTC_SEC_DBI 0x604
+#define MT6358_RTC_SEC_DXI 0x606
+#define MT6358_RTC_TC_SEC_SEC 0x608
+#define MT6358_RTC_TC_MIN_SEC 0x60a
+#define MT6358_RTC_TC_HOU_SEC 0x60c
+#define MT6358_RTC_TC_DOM_SEC 0x60e
+#define MT6358_RTC_TC_DOW_SEC 0x610
+#define MT6358_RTC_TC_MTH_SEC 0x612
+#define MT6358_RTC_TC_YEA_SEC 0x614
+#define MT6358_RTC_SEC_CK_PDN 0x616
+#define MT6358_RTC_SEC_WRTGR 0x618
+#define MT6358_PSC_TOP_INT_CON0 0x910
+#define MT6358_PSC_TOP_INT_STATUS0 0x91c
+#define MT6358_BM_TOP_INT_CON0 0xc32
+#define MT6358_BM_TOP_INT_CON1 0xc38
+#define MT6358_BM_TOP_INT_STATUS0 0xc4a
+#define MT6358_BM_TOP_INT_STATUS1 0xc4c
+#define MT6358_HK_TOP_INT_CON0 0xf92
+#define MT6358_HK_TOP_INT_STATUS0 0xf9e
+#define MT6358_BUCK_TOP_INT_CON0 0x1318
+#define MT6358_BUCK_TOP_INT_STATUS0 0x1324
+#define MT6358_BUCK_VPROC11_CON0 0x1388
+#define MT6358_BUCK_VPROC11_DBG0 0x139e
+#define MT6358_BUCK_VPROC11_DBG1 0x13a0
+#define MT6358_BUCK_VPROC11_ELR0 0x13a6
+#define MT6358_BUCK_VPROC12_CON0 0x1408
+#define MT6358_BUCK_VPROC12_DBG0 0x141e
+#define MT6358_BUCK_VPROC12_DBG1 0x1420
+#define MT6358_BUCK_VPROC12_ELR0 0x1426
+#define MT6358_BUCK_VCORE_CON0 0x1488
+#define MT6358_BUCK_VCORE_DBG0 0x149e
+#define MT6358_BUCK_VCORE_DBG1 0x14a0
+#define MT6358_BUCK_VCORE_ELR0 0x14aa
+#define MT6358_BUCK_VGPU_CON0 0x1508
+#define MT6358_BUCK_VGPU_DBG0 0x151e
+#define MT6358_BUCK_VGPU_DBG1 0x1520
+#define MT6358_BUCK_VGPU_ELR0 0x1526
+#define MT6358_BUCK_VMODEM_CON0 0x1588
+#define MT6358_BUCK_VMODEM_DBG0 0x159e
+#define MT6358_BUCK_VMODEM_DBG1 0x15a0
+#define MT6358_BUCK_VMODEM_ELR0 0x15a6
+#define MT6358_BUCK_VDRAM1_CON0 0x1608
+#define MT6358_BUCK_VDRAM1_DBG0 0x161e
+#define MT6358_BUCK_VDRAM1_DBG1 0x1620
+#define MT6358_BUCK_VDRAM1_ELR0 0x1626
+#define MT6358_BUCK_VS1_CON0 0x1688
+#define MT6358_BUCK_VS1_DBG0 0x169e
+#define MT6358_BUCK_VS1_DBG1 0x16a0
+#define MT6358_BUCK_VS1_ELR0 0x16ae
+#define MT6358_BUCK_VS2_CON0 0x1708
+#define MT6358_BUCK_VS2_DBG0 0x171e
+#define MT6358_BUCK_VS2_DBG1 0x1720
+#define MT6358_BUCK_VS2_ELR0 0x172e
+#define MT6358_BUCK_VPA_CON0 0x1788
+#define MT6358_BUCK_VPA_CON1 0x178a
+#define MT6358_BUCK_VPA_ELR0 MT6358_BUCK_VPA_CON1
+#define MT6358_BUCK_VPA_DBG0 0x1792
+#define MT6358_BUCK_VPA_DBG1 0x1794
+#define MT6358_VPROC_ANA_CON0 0x180c
+#define MT6358_VCORE_VGPU_ANA_CON0 0x1828
+#define MT6358_VMODEM_ANA_CON0 0x1888
+#define MT6358_VDRAM1_ANA_CON0 0x1896
+#define MT6358_VS1_ANA_CON0 0x18a2
+#define MT6358_VS2_ANA_CON0 0x18ae
+#define MT6358_VPA_ANA_CON0 0x18ba
+#define MT6358_LDO_TOP_INT_CON0 0x1a50
+#define MT6358_LDO_TOP_INT_CON1 0x1a56
+#define MT6358_LDO_TOP_INT_STATUS0 0x1a68
+#define MT6358_LDO_TOP_INT_STATUS1 0x1a6a
+#define MT6358_LDO_VXO22_CON0 0x1a88
+#define MT6358_LDO_VXO22_CON1 0x1a96
+#define MT6358_LDO_VA12_CON0 0x1a9c
+#define MT6358_LDO_VA12_CON1 0x1aaa
+#define MT6358_LDO_VAUX18_CON0 0x1ab0
+#define MT6358_LDO_VAUX18_CON1 0x1abe
+#define MT6358_LDO_VAUD28_CON0 0x1ac4
+#define MT6358_LDO_VAUD28_CON1 0x1ad2
+#define MT6358_LDO_VIO28_CON0 0x1ad8
+#define MT6358_LDO_VIO28_CON1 0x1ae6
+#define MT6358_LDO_VIO18_CON0 0x1aec
+#define MT6358_LDO_VIO18_CON1 0x1afa
+#define MT6358_LDO_VDRAM2_CON0 0x1b08
+#define MT6358_LDO_VDRAM2_CON1 0x1b16
+#define MT6358_LDO_VEMC_CON0 0x1b1c
+#define MT6358_LDO_VEMC_CON1 0x1b2a
+#define MT6358_LDO_VUSB_CON0_0 0x1b30
+#define MT6358_LDO_VUSB_CON1 0x1b40
+#define MT6358_LDO_VSRAM_PROC11_CON0 0x1b46
+#define MT6358_LDO_VSRAM_PROC11_DBG0 0x1b60
+#define MT6358_LDO_VSRAM_PROC11_DBG1 0x1b62
+#define MT6358_LDO_VSRAM_PROC11_TRACKING_CON0 0x1b64
+#define MT6358_LDO_VSRAM_PROC11_TRACKING_CON1 0x1b66
+#define MT6358_LDO_VSRAM_PROC11_TRACKING_CON2 0x1b68
+#define MT6358_LDO_VSRAM_PROC11_TRACKING_CON3 0x1b6a
+#define MT6358_LDO_VSRAM_PROC12_TRACKING_CON0 0x1b6c
+#define MT6358_LDO_VSRAM_PROC12_TRACKING_CON1 0x1b6e
+#define MT6358_LDO_VSRAM_PROC12_TRACKING_CON2 0x1b70
+#define MT6358_LDO_VSRAM_PROC12_TRACKING_CON3 0x1b72
+#define MT6358_LDO_VSRAM_WAKEUP_CON0 0x1b74
+#define MT6358_LDO_GON1_ELR_NUM 0x1b76
+#define MT6358_LDO_VDRAM2_ELR0 0x1b78
+#define MT6358_LDO_VSRAM_PROC12_CON0 0x1b88
+#define MT6358_LDO_VSRAM_PROC12_DBG0 0x1ba2
+#define MT6358_LDO_VSRAM_PROC12_DBG1 0x1ba4
+#define MT6358_LDO_VSRAM_OTHERS_CON0 0x1ba6
+#define MT6358_LDO_VSRAM_OTHERS_DBG0 0x1bc0
+#define MT6358_LDO_VSRAM_OTHERS_DBG1 0x1bc2
+#define MT6358_LDO_VSRAM_GPU_CON0 0x1bc8
+#define MT6358_LDO_VSRAM_GPU_DBG0 0x1be2
+#define MT6358_LDO_VSRAM_GPU_DBG1 0x1be4
+#define MT6358_LDO_VSRAM_CON0 0x1bee
+#define MT6358_LDO_VSRAM_CON1 0x1bf0
+#define MT6358_LDO_VSRAM_CON2 0x1bf2
+#define MT6358_LDO_VSRAM_CON3 0x1bf4
+#define MT6358_LDO_VFE28_CON0 0x1c08
+#define MT6358_LDO_VFE28_CON1 0x1c16
+#define MT6358_LDO_VFE28_CON2 0x1c18
+#define MT6358_LDO_VFE28_CON3 0x1c1a
+#define MT6358_LDO_VRF18_CON0 0x1c1c
+#define MT6358_LDO_VRF18_CON1 0x1c2a
+#define MT6358_LDO_VRF18_CON2 0x1c2c
+#define MT6358_LDO_VRF18_CON3 0x1c2e
+#define MT6358_LDO_VRF12_CON0 0x1c30
+#define MT6358_LDO_VRF12_CON1 0x1c3e
+#define MT6358_LDO_VRF12_CON2 0x1c40
+#define MT6358_LDO_VRF12_CON3 0x1c42
+#define MT6358_LDO_VEFUSE_CON0 0x1c44
+#define MT6358_LDO_VEFUSE_CON1 0x1c52
+#define MT6358_LDO_VEFUSE_CON2 0x1c54
+#define MT6358_LDO_VEFUSE_CON3 0x1c56
+#define MT6358_LDO_VCN18_CON0 0x1c58
+#define MT6358_LDO_VCN18_CON1 0x1c66
+#define MT6358_LDO_VCN18_CON2 0x1c68
+#define MT6358_LDO_VCN18_CON3 0x1c6a
+#define MT6358_LDO_VCAMA1_CON0 0x1c6c
+#define MT6358_LDO_VCAMA1_CON1 0x1c7a
+#define MT6358_LDO_VCAMA1_CON2 0x1c7c
+#define MT6358_LDO_VCAMA1_CON3 0x1c7e
+#define MT6358_LDO_VCAMA2_CON0 0x1c88
+#define MT6358_LDO_VCAMA2_CON1 0x1c96
+#define MT6358_LDO_VCAMA2_CON2 0x1c98
+#define MT6358_LDO_VCAMA2_CON3 0x1c9a
+#define MT6358_LDO_VCAMD_CON0 0x1c9c
+#define MT6358_LDO_VCAMD_CON1 0x1caa
+#define MT6358_LDO_VCAMD_CON2 0x1cac
+#define MT6358_LDO_VCAMD_CON3 0x1cae
+#define MT6358_LDO_VCAMIO_CON0 0x1cb0
+#define MT6358_LDO_VCAMIO_CON1 0x1cbe
+#define MT6358_LDO_VCAMIO_CON2 0x1cc0
+#define MT6358_LDO_VCAMIO_CON3 0x1cc2
+#define MT6358_LDO_VMC_CON0 0x1cc4
+#define MT6358_LDO_VMC_CON1 0x1cd2
+#define MT6358_LDO_VMC_CON2 0x1cd4
+#define MT6358_LDO_VMC_CON3 0x1cd6
+#define MT6358_LDO_VMCH_CON0 0x1cd8
+#define MT6358_LDO_VMCH_CON1 0x1ce6
+#define MT6358_LDO_VMCH_CON2 0x1ce8
+#define MT6358_LDO_VMCH_CON3 0x1cea
+#define MT6358_LDO_VIBR_CON0 0x1d08
+#define MT6358_LDO_VIBR_CON1 0x1d16
+#define MT6358_LDO_VIBR_CON2 0x1d18
+#define MT6358_LDO_VIBR_CON3 0x1d1a
+#define MT6358_LDO_VCN33_CON0_0 0x1d1c
+#define MT6358_LDO_VCN33_CON0_1 0x1d2a
+#define MT6358_LDO_VCN33_CON1 0x1d2c
+#define MT6358_LDO_VCN33_BT_CON1 MT6358_LDO_VCN33_CON1
+#define MT6358_LDO_VCN33_WIFI_CON1 MT6358_LDO_VCN33_CON1
+#define MT6358_LDO_VCN33_CON2 0x1d2e
+#define MT6358_LDO_VCN33_CON3 0x1d30
+#define MT6358_LDO_VLDO28_CON0_0 0x1d32
+#define MT6358_LDO_VLDO28_CON0_1 0x1d40
+#define MT6358_LDO_VLDO28_CON1 0x1d42
+#define MT6358_LDO_VLDO28_CON2 0x1d44
+#define MT6358_LDO_VLDO28_CON3 0x1d46
+#define MT6358_LDO_VSIM1_CON0 0x1d48
+#define MT6358_LDO_VSIM1_CON1 0x1d56
+#define MT6358_LDO_VSIM1_CON2 0x1d58
+#define MT6358_LDO_VSIM1_CON3 0x1d5a
+#define MT6358_LDO_VSIM2_CON0 0x1d5c
+#define MT6358_LDO_VSIM2_CON1 0x1d6a
+#define MT6358_LDO_VSIM2_CON2 0x1d6c
+#define MT6358_LDO_VSIM2_CON3 0x1d6e
+#define MT6358_LDO_VCN28_CON0 0x1d88
+#define MT6358_LDO_VCN28_CON1 0x1d96
+#define MT6358_LDO_VCN28_CON2 0x1d98
+#define MT6358_LDO_VCN28_CON3 0x1d9a
+#define MT6358_VRTC28_CON0 0x1d9c
+#define MT6358_LDO_VBIF28_CON0 0x1d9e
+#define MT6358_LDO_VBIF28_CON1 0x1dac
+#define MT6358_LDO_VBIF28_CON2 0x1dae
+#define MT6358_LDO_VBIF28_CON3 0x1db0
+#define MT6358_VCAMA1_ANA_CON0 0x1e08
+#define MT6358_VCAMA2_ANA_CON0 0x1e0c
+#define MT6358_VCN33_ANA_CON0 0x1e28
+#define MT6358_VSIM1_ANA_CON0 0x1e2c
+#define MT6358_VSIM2_ANA_CON0 0x1e30
+#define MT6358_VUSB_ANA_CON0 0x1e34
+#define MT6358_VEMC_ANA_CON0 0x1e38
+#define MT6358_VLDO28_ANA_CON0 0x1e3c
+#define MT6358_VIO28_ANA_CON0 0x1e40
+#define MT6358_VIBR_ANA_CON0 0x1e44
+#define MT6358_VMCH_ANA_CON0 0x1e48
+#define MT6358_VMC_ANA_CON0 0x1e4c
+#define MT6358_VRF18_ANA_CON0 0x1e88
+#define MT6358_VCN18_ANA_CON0 0x1e8c
+#define MT6358_VCAMIO_ANA_CON0 0x1e90
+#define MT6358_VIO18_ANA_CON0 0x1e94
+#define MT6358_VEFUSE_ANA_CON0 0x1e98
+#define MT6358_VRF12_ANA_CON0 0x1e9c
+#define MT6358_VSRAM_PROC11_ANA_CON0 0x1ea0
+#define MT6358_VSRAM_PROC12_ANA_CON0 0x1ea4
+#define MT6358_VSRAM_OTHERS_ANA_CON0 0x1ea6
+#define MT6358_VSRAM_GPU_ANA_CON0 0x1ea8
+#define MT6358_VDRAM2_ANA_CON0 0x1eaa
+#define MT6358_VCAMD_ANA_CON0 0x1eae
+#define MT6358_VA12_ANA_CON0 0x1eb2
+#define MT6358_AUD_TOP_INT_CON0 0x2228
+#define MT6358_AUD_TOP_INT_STATUS0 0x2234
+
+#endif /* __MFD_MT6358_REGISTERS_H__ */
diff --git a/include/linux/mfd/mt6397/core.h b/include/linux/mfd/mt6397/core.h
index 0cb5d4b0895b..efdea4814329 100644
--- a/include/linux/mfd/mt6397/core.h
+++ b/include/linux/mfd/mt6397/core.h
@@ -19,6 +19,7 @@
enum chip_id {
MT6323_CHIP_ID = 0x23,
+ MT6358_CHIP_ID = 0x58,
MT6391_CHIP_ID = 0x91,
MT6397_CHIP_ID = 0x97,
};
@@ -72,8 +73,10 @@ struct mt6397_chip {
u16 int_con[2];
u16 int_status[2];
u16 chip_id;
+ void *irq_data;
};
+int mt6358_irq_init(struct mt6397_chip *chip);
int mt6397_irq_init(struct mt6397_chip *chip);
#endif /* __MFD_MT6397_CORE_H__ */
--
2.18.0
^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [PATCH v3 06/10] mfd: Add support for the MediaTek MT6358 PMIC
2019-05-03 9:31 ` [PATCH v3 06/10] mfd: Add support for the MediaTek MT6358 PMIC Hsin-Hsiung Wang
@ 2019-05-07 5:34 ` Nicolas Boichat
0 siblings, 0 replies; 22+ messages in thread
From: Nicolas Boichat @ 2019-05-07 5:34 UTC (permalink / raw)
To: Hsin-Hsiung Wang
Cc: Lee Jones, Rob Herring, Mark Brown, Matthias Brugger,
Liam Girdwood, Mark Rutland, Eddie Huang, Sean Wang,
Alessandro Zummo, Alexandre Belloni, devicetree,
linux-arm Mailing List, moderated list:ARM/Mediatek SoC support,
lkml, linux-rtc, srv_heupstream, Claire Chang
On Fri, May 3, 2019 at 6:34 PM Hsin-Hsiung Wang
<hsin-hsiung.wang@mediatek.com> wrote:
>
> This adds support for the MediaTek MT6358 PMIC. This is a
> multifunction device with the following sub modules:
>
> - Regulator
> - RTC
> - Codec
> - Interrupt
>
> It is interfaced to the host controller using SPI interface
> by a proprietary hardware called PMIC wrapper or pwrap.
> MT6358 MFD is a child device of the pwrap.
>
> Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>
> ---
> drivers/mfd/Makefile | 3 +-
> drivers/mfd/mt6358-irq.c | 229 ++++++++++++++++++++++
> drivers/mfd/mt6397-core.c | 64 +++++-
> include/linux/mfd/mt6358/core.h | 158 +++++++++++++++
> include/linux/mfd/mt6358/registers.h | 282 +++++++++++++++++++++++++++
> include/linux/mfd/mt6397/core.h | 3 +
> 6 files changed, 737 insertions(+), 2 deletions(-)
> create mode 100644 drivers/mfd/mt6358-irq.c
> create mode 100644 include/linux/mfd/mt6358/core.h
> create mode 100644 include/linux/mfd/mt6358/registers.h
>
> diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
> index ab1e228b5a2f..6e7b2b0951e7 100644
> --- a/drivers/mfd/Makefile
> +++ b/drivers/mfd/Makefile
> @@ -234,7 +234,8 @@ obj-$(CONFIG_INTEL_SOC_PMIC) += intel-soc-pmic.o
> obj-$(CONFIG_INTEL_SOC_PMIC_BXTWC) += intel_soc_pmic_bxtwc.o
> obj-$(CONFIG_INTEL_SOC_PMIC_CHTWC) += intel_soc_pmic_chtwc.o
> obj-$(CONFIG_INTEL_SOC_PMIC_CHTDC_TI) += intel_soc_pmic_chtdc_ti.o
> -mt6397-objs := mt6397-core.o mt6397-irq.o
> +
> +mt6397-objs := mt6397-core.o mt6397-irq.o mt6358-irq.o
> obj-$(CONFIG_MFD_MT6397) += mt6397.o
>
> obj-$(CONFIG_MFD_ALTERA_A10SR) += altera-a10sr.o
> diff --git a/drivers/mfd/mt6358-irq.c b/drivers/mfd/mt6358-irq.c
> new file mode 100644
> index 000000000000..a6e8252c3431
> --- /dev/null
> +++ b/drivers/mfd/mt6358-irq.c
> @@ -0,0 +1,229 @@
> +// SPDX-License-Identifier: GPL-2.0
> +//
> +// Copyright (c) 2019 MediaTek Inc.
> +
> +#include <linux/interrupt.h>
> +#include <linux/mfd/mt6358/core.h>
> +#include <linux/mfd/mt6358/registers.h>
> +#include <linux/mfd/mt6397/core.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/of_device.h>
> +#include <linux/of_irq.h>
> +#include <linux/platform_device.h>
> +#include <linux/regmap.h>
> +
> +static struct irq_top_t mt6358_ints[] = {
> + MT6358_TOP_GEN(BUCK),
> + MT6358_TOP_GEN(LDO),
> + MT6358_TOP_GEN(PSC),
> + MT6358_TOP_GEN(SCK),
> + MT6358_TOP_GEN(BM),
> + MT6358_TOP_GEN(HK),
> + MT6358_TOP_GEN(AUD),
> + MT6358_TOP_GEN(MISC),
> +};
> +
> +static void pmic_irq_enable(struct irq_data *data)
> +{
> + unsigned int hwirq = irqd_to_hwirq(data);
> + struct mt6397_chip *chip = irq_data_get_irq_chip_data(data);
> + struct pmic_irq_data *irqd = chip->irq_data;
> +
> + irqd->enable_hwirq[hwirq] = true;
> +}
> +
> +static void pmic_irq_disable(struct irq_data *data)
> +{
> + unsigned int hwirq = irqd_to_hwirq(data);
> + struct mt6397_chip *chip = irq_data_get_irq_chip_data(data);
> + struct pmic_irq_data *irqd = chip->irq_data;
> +
> + irqd->enable_hwirq[hwirq] = false;
> +}
> +
> +static void pmic_irq_lock(struct irq_data *data)
> +{
> + struct mt6397_chip *chip = irq_data_get_irq_chip_data(data);
> +
> + mutex_lock(&chip->irqlock);
> +}
> +
> +static void pmic_irq_sync_unlock(struct irq_data *data)
> +{
> + unsigned int i, top_gp, en_reg, int_regs, shift;
> + struct mt6397_chip *chip = irq_data_get_irq_chip_data(data);
> + struct pmic_irq_data *irqd = chip->irq_data;
> +
> + for (i = 0; i < irqd->num_pmic_irqs; i++) {
> + if (irqd->enable_hwirq[i] == irqd->cache_hwirq[i])
> + continue;
> +
> + top_gp = 0;
> + while ((top_gp + 1) < ARRAY_SIZE(mt6358_ints) && i >=
> + mt6358_ints[top_gp + 1].hwirq_base)
nit: Move all of:
i >= mt6358_ints[top_gp + 1].hwirq_base
to the second line
> + top_gp++;
> +
> + if (top_gp >= ARRAY_SIZE(mt6358_ints)) {
> + mutex_unlock(&chip->irqlock);
> + dev_err(chip->dev,
> + "Failed to get top_group: %d\n", top_gp);
> + return;
> + }
> +
> + int_regs = (i - mt6358_ints[top_gp].hwirq_base) /
> + MT6358_REG_WIDTH;
> + en_reg = mt6358_ints[top_gp].en_reg +
> + mt6358_ints[top_gp].en_reg_shift * int_regs;
> + shift = (i - mt6358_ints[top_gp].hwirq_base) % MT6358_REG_WIDTH;
> + regmap_update_bits(chip->regmap, en_reg, BIT(shift),
> + irqd->enable_hwirq[i] << shift);
> + irqd->cache_hwirq[i] = irqd->enable_hwirq[i];
> + }
> + mutex_unlock(&chip->irqlock);
> +}
> +
> +static struct irq_chip mt6358_irq_chip = {
> + .name = "mt6358-irq",
> + .flags = IRQCHIP_SKIP_SET_WAKE,
> + .irq_enable = pmic_irq_enable,
> + .irq_disable = pmic_irq_disable,
> + .irq_bus_lock = pmic_irq_lock,
> + .irq_bus_sync_unlock = pmic_irq_sync_unlock,
> +};
> +
> +static void mt6358_irq_sp_handler(struct mt6397_chip *chip,
> + unsigned int top_gp)
> +{
> + unsigned int sta_reg, irq_status;
> + unsigned int hwirq, virq;
> + int ret, i, j;
> +
> + for (i = 0; i < mt6358_ints[top_gp].num_int_regs; i++) {
> + sta_reg = mt6358_ints[top_gp].sta_reg +
> + mt6358_ints[top_gp].sta_reg_shift * i;
> + ret = regmap_read(chip->regmap, sta_reg, &irq_status);
> + if (ret) {
> + dev_err(chip->dev,
> + "Failed to read irq status: %d\n", ret);
> + return;
> + }
> +
> + if (!irq_status)
> + continue;
> +
> + for (j = 0; j < MT6358_REG_WIDTH ; j++) {
> + if ((irq_status & BIT(j)) == 0)
> + continue;
> + hwirq = mt6358_ints[top_gp].hwirq_base +
> + MT6358_REG_WIDTH * i + j;
> + virq = irq_find_mapping(chip->irq_domain, hwirq);
> + if (virq)
> + handle_nested_irq(virq);
> + }
> +
> + regmap_write(chip->regmap, sta_reg, irq_status);
> + }
> +}
> +
> +static irqreturn_t mt6358_irq_handler(int irq, void *data)
> +{
> + struct mt6397_chip *chip = data;
> + struct pmic_irq_data *mt6358_irq_data = chip->irq_data;
> + unsigned int top_irq_status;
> + unsigned int i;
> + int ret;
> +
> + ret = regmap_read(chip->regmap,
> + mt6358_irq_data->top_int_status_reg,
> + &top_irq_status);
> + if (ret) {
> + dev_err(chip->dev, "Can't read TOP_INT_STATUS ret=%d\n", ret);
> + return IRQ_NONE;
> + }
> +
> + for (i = 0; i < mt6358_irq_data->num_top; i++) {
> + if (top_irq_status & BIT(mt6358_ints[i].top_offset))
> + mt6358_irq_sp_handler(chip, i);
> + }
> +
> + return IRQ_HANDLED;
> +}
> +
> +static int pmic_irq_domain_map(struct irq_domain *d, unsigned int irq,
> + irq_hw_number_t hw)
> +{
> + struct mt6397_chip *mt6397 = d->host_data;
> +
> + irq_set_chip_data(irq, mt6397);
> + irq_set_chip_and_handler(irq, &mt6358_irq_chip, handle_level_irq);
> + irq_set_nested_thread(irq, 1);
> + irq_set_noprobe(irq);
> +
> + return 0;
> +}
> +
> +static const struct irq_domain_ops mt6358_irq_domain_ops = {
> + .map = pmic_irq_domain_map,
> + .xlate = irq_domain_xlate_twocell,
> +};
> +
> +int mt6358_irq_init(struct mt6397_chip *chip)
> +{
> + int i, j, ret;
> + struct pmic_irq_data *irqd;
> +
> + irqd = devm_kzalloc(chip->dev, sizeof(struct pmic_irq_data *),
> + GFP_KERNEL);
> + if (!irqd)
> + return -ENOMEM;
> +
> + chip->irq_data = irqd;
> +
> + mutex_init(&chip->irqlock);
> + irqd->top_int_status_reg = MT6358_TOP_INT_STATUS0;
> + irqd->num_pmic_irqs = MT6358_IRQ_NR;
> + irqd->num_top = ARRAY_SIZE(mt6358_ints);
> +
> + irqd->enable_hwirq = devm_kcalloc(chip->dev,
> + irqd->num_pmic_irqs,
> + sizeof(bool),
> + GFP_KERNEL);
> + if (!irqd->enable_hwirq)
> + return -ENOMEM;
> +
> + irqd->cache_hwirq = devm_kcalloc(chip->dev,
> + irqd->num_pmic_irqs,
> + sizeof(bool),
> + GFP_KERNEL);
> + if (!irqd->cache_hwirq)
> + return -ENOMEM;
> +
> + /* Disable all interrupt for initializing */
> + for (i = 0; i < irqd->num_top; i++) {
> + for (j = 0; j < mt6358_ints[i].num_int_regs; j++)
> + regmap_write(chip->regmap,
> + mt6358_ints[i].en_reg +
> + mt6358_ints[i].en_reg_shift * j, 0);
> + }
> +
> + chip->irq_domain = irq_domain_add_linear(chip->dev->of_node,
> + irqd->num_pmic_irqs,
> + &mt6358_irq_domain_ops, chip);
> + if (!chip->irq_domain) {
> + dev_err(chip->dev, "could not create irq domain\n");
> + return -ENODEV;
> + }
> +
> + ret = devm_request_threaded_irq(chip->dev, chip->irq, NULL,
> + mt6358_irq_handler, IRQF_ONESHOT,
> + mt6358_irq_chip.name, chip);
> + if (ret) {
> + dev_err(chip->dev, "failed to register irq=%d; err: %d\n",
> + chip->irq, ret);
> + return ret;
> + }
> +
> + enable_irq_wake(chip->irq);
> + return ret;
> +}
> diff --git a/drivers/mfd/mt6397-core.c b/drivers/mfd/mt6397-core.c
> index 719687a341de..8fe61ea256ee 100644
> --- a/drivers/mfd/mt6397-core.c
> +++ b/drivers/mfd/mt6397-core.c
> @@ -18,12 +18,36 @@
> #include <linux/regmap.h>
> #include <linux/mfd/core.h>
> #include <linux/mfd/mt6323/core.h>
> +#include <linux/mfd/mt6358/core.h>
> #include <linux/mfd/mt6397/core.h>
> #include <linux/mfd/mt6323/registers.h>
> +#include <linux/mfd/mt6358/registers.h>
> #include <linux/mfd/mt6397/registers.h>
>
> +#define MT6358_RTC_BASE 0x0588
> +#define MT6358_RTC_SIZE 0x3c
> +#define MT6358_RTC_WRTGR_OFFSET 0x3a
> #define MT6397_RTC_BASE 0xe000
> #define MT6397_RTC_SIZE 0x3e
> +#define MT6397_RTC_WRTGR_OFFSET 0x3c
> +
> +static const struct resource mt6358_rtc_resources[] = {
> + {
> + .start = MT6358_RTC_BASE,
> + .end = MT6358_RTC_BASE + MT6358_RTC_SIZE,
> + .flags = IORESOURCE_MEM,
> + },
> + {
> + .start = MT6358_IRQ_RTC,
> + .end = MT6358_IRQ_RTC,
> + .flags = IORESOURCE_IRQ,
> + },
> + {
> + .start = MT6358_RTC_WRTGR_OFFSET,
> + .end = MT6358_RTC_WRTGR_OFFSET,
> + .flags = IORESOURCE_REG,
> + },
> +};
>
> static const struct resource mt6397_rtc_resources[] = {
> {
> @@ -36,6 +60,11 @@ static const struct resource mt6397_rtc_resources[] = {
> .end = MT6397_IRQ_RTC,
> .flags = IORESOURCE_IRQ,
> },
> + {
> + .start = MT6397_RTC_WRTGR_OFFSET,
> + .end = MT6397_RTC_WRTGR_OFFSET,
> + .flags = IORESOURCE_REG,
> + },
> };
>
> static const struct resource mt6323_keys_resources[] = {
> @@ -63,6 +92,21 @@ static const struct mfd_cell mt6323_devs[] = {
> },
> };
>
> +static const struct mfd_cell mt6358_devs[] = {
> + {
> + .name = "mt6358-regulator",
> + .of_compatible = "mediatek,mt6358-regulator"
> + }, {
> + .name = "mt6397-rtc",
> + .num_resources = ARRAY_SIZE(mt6358_rtc_resources),
> + .resources = mt6358_rtc_resources,
> + .of_compatible = "mediatek,mt6358-rtc",
> + }, {
> + .name = "mt6358-sound",
> + .of_compatible = "mediatek,mt6358-sound"
> + },
> +};
> +
> static const struct mfd_cell mt6397_devs[] = {
> {
> .name = "mt6397-rtc",
> @@ -99,6 +143,11 @@ static const struct chip_data mt6323_core = {
> .cid_shift = 0,
> };
>
> +static const struct chip_data mt6358_core = {
> + .cid_addr = MT6358_SWCID,
> + .cid_shift = 8,
> +};
> +
> static const struct chip_data mt6397_core = {
> .cid_addr = MT6397_CID,
> .cid_shift = 0,
> @@ -143,7 +192,11 @@ static int mt6397_probe(struct platform_device *pdev)
> if (pmic->irq <= 0)
> return pmic->irq;
>
> - ret = mt6397_irq_init(pmic);
> + if (pmic->chip_id == MT6358_CHIP_ID)
> + ret = mt6358_irq_init(pmic);
> + else
> + ret = mt6397_irq_init(pmic);
> +
> if (ret)
> return ret;
>
> @@ -154,6 +207,12 @@ static int mt6397_probe(struct platform_device *pdev)
> 0, pmic->irq_domain);
> break;
>
> + case MT6358_CHIP_ID:
> + ret = devm_mfd_add_devices(&pdev->dev, -1, mt6358_devs,
> + ARRAY_SIZE(mt6358_devs), NULL,
> + 0, pmic->irq_domain);
> + break;
> +
> case MT6391_CHIP_ID:
> case MT6397_CHIP_ID:
> ret = devm_mfd_add_devices(&pdev->dev, -1, mt6397_devs,
> @@ -178,6 +237,9 @@ static const struct of_device_id mt6397_of_match[] = {
> {
> .compatible = "mediatek,mt6323",
> .data = &mt6323_core,
> + }, {
> + .compatible = "mediatek,mt6358",
> + .data = &mt6358_core,
> }, {
> .compatible = "mediatek,mt6397",
> .data = &mt6397_core,
> diff --git a/include/linux/mfd/mt6358/core.h b/include/linux/mfd/mt6358/core.h
> new file mode 100644
> index 000000000000..05108617bc74
> --- /dev/null
> +++ b/include/linux/mfd/mt6358/core.h
> @@ -0,0 +1,158 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Copyright (c) 2019 MediaTek Inc.
> + */
> +
> +#ifndef __MFD_MT6358_CORE_H__
> +#define __MFD_MT6358_CORE_H__
> +
> +#define MT6358_REG_WIDTH 16
> +
> +struct irq_top_t {
> + int hwirq_base;
> + unsigned int num_int_regs;
> + unsigned int num_int_bits;
> + unsigned int en_reg;
> + unsigned int en_reg_shift;
> + unsigned int sta_reg;
> + unsigned int sta_reg_shift;
> + unsigned int top_offset;
> +};
> +
> +struct pmic_irq_data {
> + unsigned int num_top;
> + unsigned int num_pmic_irqs;
> + unsigned short top_int_status_reg;
> + bool *enable_hwirq;
> + bool *cache_hwirq;
> +};
> +
> +enum mt6358_irq_top_status_shift {
> + MT6358_BUCK_TOP = 0,
> + MT6358_LDO_TOP,
> + MT6358_PSC_TOP,
> + MT6358_SCK_TOP,
> + MT6358_BM_TOP,
> + MT6358_HK_TOP,
> + MT6358_AUD_TOP,
> + MT6358_MISC_TOP,
> +};
> +
> +enum mt6358_irq_numbers {
> + MT6358_IRQ_VPROC11_OC = 0,
> + MT6358_IRQ_VPROC12_OC,
> + MT6358_IRQ_VCORE_OC,
> + MT6358_IRQ_VGPU_OC,
> + MT6358_IRQ_VMODEM_OC,
> + MT6358_IRQ_VDRAM1_OC,
> + MT6358_IRQ_VS1_OC,
> + MT6358_IRQ_VS2_OC,
> + MT6358_IRQ_VPA_OC,
> + MT6358_IRQ_VCORE_PREOC,
> + MT6358_IRQ_VFE28_OC = 16,
> + MT6358_IRQ_VXO22_OC,
> + MT6358_IRQ_VRF18_OC,
> + MT6358_IRQ_VRF12_OC,
> + MT6358_IRQ_VEFUSE_OC,
> + MT6358_IRQ_VCN33_OC,
> + MT6358_IRQ_VCN28_OC,
> + MT6358_IRQ_VCN18_OC,
> + MT6358_IRQ_VCAMA1_OC,
> + MT6358_IRQ_VCAMA2_OC,
> + MT6358_IRQ_VCAMD_OC,
> + MT6358_IRQ_VCAMIO_OC,
> + MT6358_IRQ_VLDO28_OC,
> + MT6358_IRQ_VA12_OC,
> + MT6358_IRQ_VAUX18_OC,
> + MT6358_IRQ_VAUD28_OC,
> + MT6358_IRQ_VIO28_OC,
> + MT6358_IRQ_VIO18_OC,
> + MT6358_IRQ_VSRAM_PROC11_OC,
> + MT6358_IRQ_VSRAM_PROC12_OC,
> + MT6358_IRQ_VSRAM_OTHERS_OC,
> + MT6358_IRQ_VSRAM_GPU_OC,
> + MT6358_IRQ_VDRAM2_OC,
> + MT6358_IRQ_VMC_OC,
> + MT6358_IRQ_VMCH_OC,
> + MT6358_IRQ_VEMC_OC,
> + MT6358_IRQ_VSIM1_OC,
> + MT6358_IRQ_VSIM2_OC,
> + MT6358_IRQ_VIBR_OC,
> + MT6358_IRQ_VUSB_OC,
> + MT6358_IRQ_VBIF28_OC,
> + MT6358_IRQ_PWRKEY = 48,
> + MT6358_IRQ_HOMEKEY,
> + MT6358_IRQ_PWRKEY_R,
> + MT6358_IRQ_HOMEKEY_R,
> + MT6358_IRQ_NI_LBAT_INT,
> + MT6358_IRQ_CHRDET,
> + MT6358_IRQ_CHRDET_EDGE,
> + MT6358_IRQ_VCDT_HV_DET,
> + MT6358_IRQ_RTC = 64,
> + MT6358_IRQ_FG_BAT0_H = 80,
> + MT6358_IRQ_FG_BAT0_L,
> + MT6358_IRQ_FG_CUR_H,
> + MT6358_IRQ_FG_CUR_L,
> + MT6358_IRQ_FG_ZCV,
> + MT6358_IRQ_FG_BAT1_H,
> + MT6358_IRQ_FG_BAT1_L,
> + MT6358_IRQ_FG_N_CHARGE_L,
> + MT6358_IRQ_FG_IAVG_H,
> + MT6358_IRQ_FG_IAVG_L,
> + MT6358_IRQ_FG_TIME_H,
> + MT6358_IRQ_FG_DISCHARGE,
> + MT6358_IRQ_FG_CHARGE,
> + MT6358_IRQ_BATON_LV = 96,
> + MT6358_IRQ_BATON_HT,
> + MT6358_IRQ_BATON_BAT_IN,
> + MT6358_IRQ_BATON_BAT_OUT,
> + MT6358_IRQ_BIF,
> + MT6358_IRQ_BAT_H = 112,
> + MT6358_IRQ_BAT_L,
> + MT6358_IRQ_BAT2_H,
> + MT6358_IRQ_BAT2_L,
> + MT6358_IRQ_BAT_TEMP_H,
> + MT6358_IRQ_BAT_TEMP_L,
> + MT6358_IRQ_AUXADC_IMP,
> + MT6358_IRQ_NAG_C_DLTV,
> + MT6358_IRQ_AUDIO = 128,
> + MT6358_IRQ_ACCDET = 133,
> + MT6358_IRQ_ACCDET_EINT0,
> + MT6358_IRQ_ACCDET_EINT1,
> + MT6358_IRQ_SPI_CMD_ALERT = 144,
> + MT6358_IRQ_NR,
> +};
> +
> +#define MT6358_IRQ_BUCK_BASE MT6358_IRQ_VPROC11_OC
> +#define MT6358_IRQ_LDO_BASE MT6358_IRQ_VFE28_OC
> +#define MT6358_IRQ_PSC_BASE MT6358_IRQ_PWRKEY
> +#define MT6358_IRQ_SCK_BASE MT6358_IRQ_RTC
> +#define MT6358_IRQ_BM_BASE MT6358_IRQ_FG_BAT0_H
> +#define MT6358_IRQ_HK_BASE MT6358_IRQ_BAT_H
> +#define MT6358_IRQ_AUD_BASE MT6358_IRQ_AUDIO
> +#define MT6358_IRQ_MISC_BASE MT6358_IRQ_SPI_CMD_ALERT
> +
> +#define MT6358_IRQ_BUCK_BITS (MT6358_IRQ_VCORE_PREOC - MT6358_IRQ_BUCK_BASE + 1)
> +#define MT6358_IRQ_LDO_BITS (MT6358_IRQ_VBIF28_OC - MT6358_IRQ_LDO_BASE + 1)
> +#define MT6358_IRQ_PSC_BITS (MT6358_IRQ_VCDT_HV_DET - MT6358_IRQ_PSC_BASE + 1)
> +#define MT6358_IRQ_SCK_BITS (MT6358_IRQ_RTC - MT6358_IRQ_SCK_BASE + 1)
> +#define MT6358_IRQ_BM_BITS (MT6358_IRQ_BIF - MT6358_IRQ_BM_BASE + 1)
> +#define MT6358_IRQ_HK_BITS (MT6358_IRQ_NAG_C_DLTV - MT6358_IRQ_HK_BASE + 1)
> +#define MT6358_IRQ_AUD_BITS (MT6358_IRQ_ACCDET_EINT1 - MT6358_IRQ_AUD_BASE + 1)
> +#define MT6358_IRQ_MISC_BITS \
> + (MT6358_IRQ_SPI_CMD_ALERT - MT6358_IRQ_MISC_BASE + 1)
> +
> +#define MT6358_TOP_GEN(sp) \
> +{ \
> + .hwirq_base = MT6358_IRQ_##sp##_BASE, \
> + .num_int_regs = \
> + ((MT6358_IRQ_##sp##_BITS - 1) / MT6358_REG_WIDTH) + 1, \
> + .num_int_bits = MT6358_IRQ_##sp##_BITS, \
> + .en_reg = MT6358_##sp##_TOP_INT_CON0, \
> + .en_reg_shift = 0x6, \
> + .sta_reg = MT6358_##sp##_TOP_INT_STATUS0, \
> + .sta_reg_shift = 0x2, \
> + .top_offset = MT6358_##sp##_TOP, \
> +}
> +
> +#endif /* __MFD_MT6358_CORE_H__ */
> diff --git a/include/linux/mfd/mt6358/registers.h b/include/linux/mfd/mt6358/registers.h
> new file mode 100644
> index 000000000000..ff5645b9348c
> --- /dev/null
> +++ b/include/linux/mfd/mt6358/registers.h
> @@ -0,0 +1,282 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Copyright (c) 2019 MediaTek Inc.
> + */
> +
> +#ifndef __MFD_MT6358_REGISTERS_H__
> +#define __MFD_MT6358_REGISTERS_H__
> +
> +/* PMIC Registers */
> +#define MT6358_SWCID 0xa
> +#define MT6358_MISC_TOP_INT_CON0 0x188
> +#define MT6358_MISC_TOP_INT_STATUS0 0x194
> +#define MT6358_TOP_INT_STATUS0 0x19e
> +#define MT6358_SCK_TOP_INT_CON0 0x52e
> +#define MT6358_SCK_TOP_INT_STATUS0 0x53a
> +#define MT6358_EOSC_CALI_CON0 0x540
> +#define MT6358_EOSC_CALI_CON1 0x542
> +#define MT6358_RTC_MIX_CON0 0x544
> +#define MT6358_RTC_MIX_CON1 0x546
> +#define MT6358_RTC_MIX_CON2 0x548
> +#define MT6358_RTC_DSN_ID 0x580
> +#define MT6358_RTC_DSN_REV0 0x582
> +#define MT6358_RTC_DBI 0x584
> +#define MT6358_RTC_DXI 0x586
> +#define MT6358_RTC_BBPU 0x588
> +#define MT6358_RTC_IRQ_STA 0x58a
> +#define MT6358_RTC_IRQ_EN 0x58c
> +#define MT6358_RTC_CII_EN 0x58e
> +#define MT6358_RTC_AL_MASK 0x590
> +#define MT6358_RTC_TC_SEC 0x592
> +#define MT6358_RTC_TC_MIN 0x594
> +#define MT6358_RTC_TC_HOU 0x596
> +#define MT6358_RTC_TC_DOM 0x598
> +#define MT6358_RTC_TC_DOW 0x59a
> +#define MT6358_RTC_TC_MTH 0x59c
> +#define MT6358_RTC_TC_YEA 0x59e
> +#define MT6358_RTC_AL_SEC 0x5a0
> +#define MT6358_RTC_AL_MIN 0x5a2
> +#define MT6358_RTC_AL_HOU 0x5a4
> +#define MT6358_RTC_AL_DOM 0x5a6
> +#define MT6358_RTC_AL_DOW 0x5a8
> +#define MT6358_RTC_AL_MTH 0x5aa
> +#define MT6358_RTC_AL_YEA 0x5ac
> +#define MT6358_RTC_OSC32CON 0x5ae
> +#define MT6358_RTC_POWERKEY1 0x5b0
> +#define MT6358_RTC_POWERKEY2 0x5b2
> +#define MT6358_RTC_PDN1 0x5b4
> +#define MT6358_RTC_PDN2 0x5b6
> +#define MT6358_RTC_SPAR0 0x5b8
> +#define MT6358_RTC_SPAR1 0x5ba
> +#define MT6358_RTC_PROT 0x5bc
> +#define MT6358_RTC_DIFF 0x5be
> +#define MT6358_RTC_CALI 0x5c0
> +#define MT6358_RTC_WRTGR 0x5c2
> +#define MT6358_RTC_CON 0x5c4
> +#define MT6358_RTC_SEC_CTRL 0x5c6
> +#define MT6358_RTC_INT_CNT 0x5c8
> +#define MT6358_RTC_SEC_DAT0 0x5ca
> +#define MT6358_RTC_SEC_DAT1 0x5cc
> +#define MT6358_RTC_SEC_DAT2 0x5ce
> +#define MT6358_RTC_SEC_DSN_ID 0x600
> +#define MT6358_RTC_SEC_DSN_REV0 0x602
> +#define MT6358_RTC_SEC_DBI 0x604
> +#define MT6358_RTC_SEC_DXI 0x606
> +#define MT6358_RTC_TC_SEC_SEC 0x608
> +#define MT6358_RTC_TC_MIN_SEC 0x60a
> +#define MT6358_RTC_TC_HOU_SEC 0x60c
> +#define MT6358_RTC_TC_DOM_SEC 0x60e
> +#define MT6358_RTC_TC_DOW_SEC 0x610
> +#define MT6358_RTC_TC_MTH_SEC 0x612
> +#define MT6358_RTC_TC_YEA_SEC 0x614
> +#define MT6358_RTC_SEC_CK_PDN 0x616
> +#define MT6358_RTC_SEC_WRTGR 0x618
> +#define MT6358_PSC_TOP_INT_CON0 0x910
> +#define MT6358_PSC_TOP_INT_STATUS0 0x91c
> +#define MT6358_BM_TOP_INT_CON0 0xc32
> +#define MT6358_BM_TOP_INT_CON1 0xc38
> +#define MT6358_BM_TOP_INT_STATUS0 0xc4a
> +#define MT6358_BM_TOP_INT_STATUS1 0xc4c
> +#define MT6358_HK_TOP_INT_CON0 0xf92
> +#define MT6358_HK_TOP_INT_STATUS0 0xf9e
> +#define MT6358_BUCK_TOP_INT_CON0 0x1318
> +#define MT6358_BUCK_TOP_INT_STATUS0 0x1324
> +#define MT6358_BUCK_VPROC11_CON0 0x1388
> +#define MT6358_BUCK_VPROC11_DBG0 0x139e
> +#define MT6358_BUCK_VPROC11_DBG1 0x13a0
> +#define MT6358_BUCK_VPROC11_ELR0 0x13a6
> +#define MT6358_BUCK_VPROC12_CON0 0x1408
> +#define MT6358_BUCK_VPROC12_DBG0 0x141e
> +#define MT6358_BUCK_VPROC12_DBG1 0x1420
> +#define MT6358_BUCK_VPROC12_ELR0 0x1426
> +#define MT6358_BUCK_VCORE_CON0 0x1488
> +#define MT6358_BUCK_VCORE_DBG0 0x149e
> +#define MT6358_BUCK_VCORE_DBG1 0x14a0
> +#define MT6358_BUCK_VCORE_ELR0 0x14aa
> +#define MT6358_BUCK_VGPU_CON0 0x1508
> +#define MT6358_BUCK_VGPU_DBG0 0x151e
> +#define MT6358_BUCK_VGPU_DBG1 0x1520
> +#define MT6358_BUCK_VGPU_ELR0 0x1526
> +#define MT6358_BUCK_VMODEM_CON0 0x1588
> +#define MT6358_BUCK_VMODEM_DBG0 0x159e
> +#define MT6358_BUCK_VMODEM_DBG1 0x15a0
> +#define MT6358_BUCK_VMODEM_ELR0 0x15a6
> +#define MT6358_BUCK_VDRAM1_CON0 0x1608
> +#define MT6358_BUCK_VDRAM1_DBG0 0x161e
> +#define MT6358_BUCK_VDRAM1_DBG1 0x1620
> +#define MT6358_BUCK_VDRAM1_ELR0 0x1626
> +#define MT6358_BUCK_VS1_CON0 0x1688
> +#define MT6358_BUCK_VS1_DBG0 0x169e
> +#define MT6358_BUCK_VS1_DBG1 0x16a0
> +#define MT6358_BUCK_VS1_ELR0 0x16ae
> +#define MT6358_BUCK_VS2_CON0 0x1708
> +#define MT6358_BUCK_VS2_DBG0 0x171e
> +#define MT6358_BUCK_VS2_DBG1 0x1720
> +#define MT6358_BUCK_VS2_ELR0 0x172e
> +#define MT6358_BUCK_VPA_CON0 0x1788
> +#define MT6358_BUCK_VPA_CON1 0x178a
> +#define MT6358_BUCK_VPA_ELR0 MT6358_BUCK_VPA_CON1
> +#define MT6358_BUCK_VPA_DBG0 0x1792
> +#define MT6358_BUCK_VPA_DBG1 0x1794
> +#define MT6358_VPROC_ANA_CON0 0x180c
> +#define MT6358_VCORE_VGPU_ANA_CON0 0x1828
> +#define MT6358_VMODEM_ANA_CON0 0x1888
> +#define MT6358_VDRAM1_ANA_CON0 0x1896
> +#define MT6358_VS1_ANA_CON0 0x18a2
> +#define MT6358_VS2_ANA_CON0 0x18ae
> +#define MT6358_VPA_ANA_CON0 0x18ba
> +#define MT6358_LDO_TOP_INT_CON0 0x1a50
> +#define MT6358_LDO_TOP_INT_CON1 0x1a56
> +#define MT6358_LDO_TOP_INT_STATUS0 0x1a68
> +#define MT6358_LDO_TOP_INT_STATUS1 0x1a6a
> +#define MT6358_LDO_VXO22_CON0 0x1a88
> +#define MT6358_LDO_VXO22_CON1 0x1a96
> +#define MT6358_LDO_VA12_CON0 0x1a9c
> +#define MT6358_LDO_VA12_CON1 0x1aaa
> +#define MT6358_LDO_VAUX18_CON0 0x1ab0
> +#define MT6358_LDO_VAUX18_CON1 0x1abe
> +#define MT6358_LDO_VAUD28_CON0 0x1ac4
> +#define MT6358_LDO_VAUD28_CON1 0x1ad2
> +#define MT6358_LDO_VIO28_CON0 0x1ad8
> +#define MT6358_LDO_VIO28_CON1 0x1ae6
> +#define MT6358_LDO_VIO18_CON0 0x1aec
> +#define MT6358_LDO_VIO18_CON1 0x1afa
> +#define MT6358_LDO_VDRAM2_CON0 0x1b08
> +#define MT6358_LDO_VDRAM2_CON1 0x1b16
> +#define MT6358_LDO_VEMC_CON0 0x1b1c
> +#define MT6358_LDO_VEMC_CON1 0x1b2a
> +#define MT6358_LDO_VUSB_CON0_0 0x1b30
> +#define MT6358_LDO_VUSB_CON1 0x1b40
> +#define MT6358_LDO_VSRAM_PROC11_CON0 0x1b46
> +#define MT6358_LDO_VSRAM_PROC11_DBG0 0x1b60
> +#define MT6358_LDO_VSRAM_PROC11_DBG1 0x1b62
> +#define MT6358_LDO_VSRAM_PROC11_TRACKING_CON0 0x1b64
> +#define MT6358_LDO_VSRAM_PROC11_TRACKING_CON1 0x1b66
> +#define MT6358_LDO_VSRAM_PROC11_TRACKING_CON2 0x1b68
> +#define MT6358_LDO_VSRAM_PROC11_TRACKING_CON3 0x1b6a
> +#define MT6358_LDO_VSRAM_PROC12_TRACKING_CON0 0x1b6c
> +#define MT6358_LDO_VSRAM_PROC12_TRACKING_CON1 0x1b6e
> +#define MT6358_LDO_VSRAM_PROC12_TRACKING_CON2 0x1b70
> +#define MT6358_LDO_VSRAM_PROC12_TRACKING_CON3 0x1b72
> +#define MT6358_LDO_VSRAM_WAKEUP_CON0 0x1b74
> +#define MT6358_LDO_GON1_ELR_NUM 0x1b76
> +#define MT6358_LDO_VDRAM2_ELR0 0x1b78
> +#define MT6358_LDO_VSRAM_PROC12_CON0 0x1b88
> +#define MT6358_LDO_VSRAM_PROC12_DBG0 0x1ba2
> +#define MT6358_LDO_VSRAM_PROC12_DBG1 0x1ba4
> +#define MT6358_LDO_VSRAM_OTHERS_CON0 0x1ba6
> +#define MT6358_LDO_VSRAM_OTHERS_DBG0 0x1bc0
> +#define MT6358_LDO_VSRAM_OTHERS_DBG1 0x1bc2
> +#define MT6358_LDO_VSRAM_GPU_CON0 0x1bc8
> +#define MT6358_LDO_VSRAM_GPU_DBG0 0x1be2
> +#define MT6358_LDO_VSRAM_GPU_DBG1 0x1be4
> +#define MT6358_LDO_VSRAM_CON0 0x1bee
> +#define MT6358_LDO_VSRAM_CON1 0x1bf0
> +#define MT6358_LDO_VSRAM_CON2 0x1bf2
> +#define MT6358_LDO_VSRAM_CON3 0x1bf4
> +#define MT6358_LDO_VFE28_CON0 0x1c08
> +#define MT6358_LDO_VFE28_CON1 0x1c16
> +#define MT6358_LDO_VFE28_CON2 0x1c18
> +#define MT6358_LDO_VFE28_CON3 0x1c1a
> +#define MT6358_LDO_VRF18_CON0 0x1c1c
> +#define MT6358_LDO_VRF18_CON1 0x1c2a
> +#define MT6358_LDO_VRF18_CON2 0x1c2c
> +#define MT6358_LDO_VRF18_CON3 0x1c2e
> +#define MT6358_LDO_VRF12_CON0 0x1c30
> +#define MT6358_LDO_VRF12_CON1 0x1c3e
> +#define MT6358_LDO_VRF12_CON2 0x1c40
> +#define MT6358_LDO_VRF12_CON3 0x1c42
> +#define MT6358_LDO_VEFUSE_CON0 0x1c44
> +#define MT6358_LDO_VEFUSE_CON1 0x1c52
> +#define MT6358_LDO_VEFUSE_CON2 0x1c54
> +#define MT6358_LDO_VEFUSE_CON3 0x1c56
> +#define MT6358_LDO_VCN18_CON0 0x1c58
> +#define MT6358_LDO_VCN18_CON1 0x1c66
> +#define MT6358_LDO_VCN18_CON2 0x1c68
> +#define MT6358_LDO_VCN18_CON3 0x1c6a
> +#define MT6358_LDO_VCAMA1_CON0 0x1c6c
> +#define MT6358_LDO_VCAMA1_CON1 0x1c7a
> +#define MT6358_LDO_VCAMA1_CON2 0x1c7c
> +#define MT6358_LDO_VCAMA1_CON3 0x1c7e
> +#define MT6358_LDO_VCAMA2_CON0 0x1c88
> +#define MT6358_LDO_VCAMA2_CON1 0x1c96
> +#define MT6358_LDO_VCAMA2_CON2 0x1c98
> +#define MT6358_LDO_VCAMA2_CON3 0x1c9a
> +#define MT6358_LDO_VCAMD_CON0 0x1c9c
> +#define MT6358_LDO_VCAMD_CON1 0x1caa
> +#define MT6358_LDO_VCAMD_CON2 0x1cac
> +#define MT6358_LDO_VCAMD_CON3 0x1cae
> +#define MT6358_LDO_VCAMIO_CON0 0x1cb0
> +#define MT6358_LDO_VCAMIO_CON1 0x1cbe
> +#define MT6358_LDO_VCAMIO_CON2 0x1cc0
> +#define MT6358_LDO_VCAMIO_CON3 0x1cc2
> +#define MT6358_LDO_VMC_CON0 0x1cc4
> +#define MT6358_LDO_VMC_CON1 0x1cd2
> +#define MT6358_LDO_VMC_CON2 0x1cd4
> +#define MT6358_LDO_VMC_CON3 0x1cd6
> +#define MT6358_LDO_VMCH_CON0 0x1cd8
> +#define MT6358_LDO_VMCH_CON1 0x1ce6
> +#define MT6358_LDO_VMCH_CON2 0x1ce8
> +#define MT6358_LDO_VMCH_CON3 0x1cea
> +#define MT6358_LDO_VIBR_CON0 0x1d08
> +#define MT6358_LDO_VIBR_CON1 0x1d16
> +#define MT6358_LDO_VIBR_CON2 0x1d18
> +#define MT6358_LDO_VIBR_CON3 0x1d1a
> +#define MT6358_LDO_VCN33_CON0_0 0x1d1c
> +#define MT6358_LDO_VCN33_CON0_1 0x1d2a
> +#define MT6358_LDO_VCN33_CON1 0x1d2c
> +#define MT6358_LDO_VCN33_BT_CON1 MT6358_LDO_VCN33_CON1
> +#define MT6358_LDO_VCN33_WIFI_CON1 MT6358_LDO_VCN33_CON1
> +#define MT6358_LDO_VCN33_CON2 0x1d2e
> +#define MT6358_LDO_VCN33_CON3 0x1d30
> +#define MT6358_LDO_VLDO28_CON0_0 0x1d32
> +#define MT6358_LDO_VLDO28_CON0_1 0x1d40
> +#define MT6358_LDO_VLDO28_CON1 0x1d42
> +#define MT6358_LDO_VLDO28_CON2 0x1d44
> +#define MT6358_LDO_VLDO28_CON3 0x1d46
> +#define MT6358_LDO_VSIM1_CON0 0x1d48
> +#define MT6358_LDO_VSIM1_CON1 0x1d56
> +#define MT6358_LDO_VSIM1_CON2 0x1d58
> +#define MT6358_LDO_VSIM1_CON3 0x1d5a
> +#define MT6358_LDO_VSIM2_CON0 0x1d5c
> +#define MT6358_LDO_VSIM2_CON1 0x1d6a
> +#define MT6358_LDO_VSIM2_CON2 0x1d6c
> +#define MT6358_LDO_VSIM2_CON3 0x1d6e
> +#define MT6358_LDO_VCN28_CON0 0x1d88
> +#define MT6358_LDO_VCN28_CON1 0x1d96
> +#define MT6358_LDO_VCN28_CON2 0x1d98
> +#define MT6358_LDO_VCN28_CON3 0x1d9a
> +#define MT6358_VRTC28_CON0 0x1d9c
> +#define MT6358_LDO_VBIF28_CON0 0x1d9e
> +#define MT6358_LDO_VBIF28_CON1 0x1dac
> +#define MT6358_LDO_VBIF28_CON2 0x1dae
> +#define MT6358_LDO_VBIF28_CON3 0x1db0
> +#define MT6358_VCAMA1_ANA_CON0 0x1e08
> +#define MT6358_VCAMA2_ANA_CON0 0x1e0c
> +#define MT6358_VCN33_ANA_CON0 0x1e28
> +#define MT6358_VSIM1_ANA_CON0 0x1e2c
> +#define MT6358_VSIM2_ANA_CON0 0x1e30
> +#define MT6358_VUSB_ANA_CON0 0x1e34
> +#define MT6358_VEMC_ANA_CON0 0x1e38
> +#define MT6358_VLDO28_ANA_CON0 0x1e3c
> +#define MT6358_VIO28_ANA_CON0 0x1e40
> +#define MT6358_VIBR_ANA_CON0 0x1e44
> +#define MT6358_VMCH_ANA_CON0 0x1e48
> +#define MT6358_VMC_ANA_CON0 0x1e4c
> +#define MT6358_VRF18_ANA_CON0 0x1e88
> +#define MT6358_VCN18_ANA_CON0 0x1e8c
> +#define MT6358_VCAMIO_ANA_CON0 0x1e90
> +#define MT6358_VIO18_ANA_CON0 0x1e94
> +#define MT6358_VEFUSE_ANA_CON0 0x1e98
> +#define MT6358_VRF12_ANA_CON0 0x1e9c
> +#define MT6358_VSRAM_PROC11_ANA_CON0 0x1ea0
> +#define MT6358_VSRAM_PROC12_ANA_CON0 0x1ea4
> +#define MT6358_VSRAM_OTHERS_ANA_CON0 0x1ea6
> +#define MT6358_VSRAM_GPU_ANA_CON0 0x1ea8
> +#define MT6358_VDRAM2_ANA_CON0 0x1eaa
> +#define MT6358_VCAMD_ANA_CON0 0x1eae
> +#define MT6358_VA12_ANA_CON0 0x1eb2
> +#define MT6358_AUD_TOP_INT_CON0 0x2228
> +#define MT6358_AUD_TOP_INT_STATUS0 0x2234
> +
> +#endif /* __MFD_MT6358_REGISTERS_H__ */
> diff --git a/include/linux/mfd/mt6397/core.h b/include/linux/mfd/mt6397/core.h
> index 0cb5d4b0895b..efdea4814329 100644
> --- a/include/linux/mfd/mt6397/core.h
> +++ b/include/linux/mfd/mt6397/core.h
> @@ -19,6 +19,7 @@
>
> enum chip_id {
> MT6323_CHIP_ID = 0x23,
> + MT6358_CHIP_ID = 0x58,
> MT6391_CHIP_ID = 0x91,
> MT6397_CHIP_ID = 0x97,
> };
> @@ -72,8 +73,10 @@ struct mt6397_chip {
> u16 int_con[2];
> u16 int_status[2];
> u16 chip_id;
> + void *irq_data;
> };
>
> +int mt6358_irq_init(struct mt6397_chip *chip);
> int mt6397_irq_init(struct mt6397_chip *chip);
>
> #endif /* __MFD_MT6397_CORE_H__ */
> --
> 2.18.0
>
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH v3 07/10] regulator: mt6358: Add support for MT6358 regulator
2019-05-03 9:31 [PATCH v3 00/10] Add Support for MediaTek PMIC MT6358 Hsin-Hsiung Wang
` (5 preceding siblings ...)
2019-05-03 9:31 ` [PATCH v3 06/10] mfd: Add support for the MediaTek MT6358 PMIC Hsin-Hsiung Wang
@ 2019-05-03 9:31 ` Hsin-Hsiung Wang
2019-05-06 3:37 ` Mark Brown
2019-05-07 5:40 ` Nicolas Boichat
2019-05-03 9:31 ` [PATCH v3 08/10] arm64: dts: mt6358: add PMIC MT6358 related nodes Hsin-Hsiung Wang
` (2 subsequent siblings)
9 siblings, 2 replies; 22+ messages in thread
From: Hsin-Hsiung Wang @ 2019-05-03 9:31 UTC (permalink / raw)
To: Lee Jones, Rob Herring, Mark Brown, Matthias Brugger
Cc: Liam Girdwood, Mark Rutland, Eddie Huang, Sean Wang,
Alessandro Zummo, Alexandre Belloni, Hsin-Hsiung Wang,
devicetree, linux-arm-kernel, linux-mediatek, linux-kernel,
linux-rtc, srv_heupstream
The MT6358 is a regulator found on boards based on MediaTek MT8183 and
probably other SoCs. It is a so called pmic and connects as a slave to
SoC using SPI, wrapped inside the pmic-wrapper.
Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>
---
drivers/regulator/Kconfig | 9 +
drivers/regulator/Makefile | 1 +
drivers/regulator/mt6358-regulator.c | 586 +++++++++++++++++++++
include/linux/regulator/mt6358-regulator.h | 56 ++
4 files changed, 652 insertions(+)
create mode 100644 drivers/regulator/mt6358-regulator.c
create mode 100644 include/linux/regulator/mt6358-regulator.h
diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig
index b7f249ee5e68..668e9716558c 100644
--- a/drivers/regulator/Kconfig
+++ b/drivers/regulator/Kconfig
@@ -615,6 +615,15 @@ config REGULATOR_MT6323
This driver supports the control of different power rails of device
through regulator interface.
+config REGULATOR_MT6358
+ tristate "MediaTek MT6358 PMIC"
+ depends on MFD_MT6397
+ help
+ Say y here to select this option to enable the power regulator of
+ MediaTek MT6358 PMIC.
+ This driver supports the control of different power rails of device
+ through regulator interface.
+
config REGULATOR_MT6380
tristate "MediaTek MT6380 PMIC"
depends on MTK_PMIC_WRAP
diff --git a/drivers/regulator/Makefile b/drivers/regulator/Makefile
index 1169f8a27d91..eeb60395c692 100644
--- a/drivers/regulator/Makefile
+++ b/drivers/regulator/Makefile
@@ -79,6 +79,7 @@ obj-$(CONFIG_REGULATOR_MC13XXX_CORE) += mc13xxx-regulator-core.o
obj-$(CONFIG_REGULATOR_MCP16502) += mcp16502.o
obj-$(CONFIG_REGULATOR_MT6311) += mt6311-regulator.o
obj-$(CONFIG_REGULATOR_MT6323) += mt6323-regulator.o
+obj-$(CONFIG_REGULATOR_MT6358) += mt6358-regulator.o
obj-$(CONFIG_REGULATOR_MT6380) += mt6380-regulator.o
obj-$(CONFIG_REGULATOR_MT6397) += mt6397-regulator.o
obj-$(CONFIG_REGULATOR_QCOM_RPM) += qcom_rpm-regulator.o
diff --git a/drivers/regulator/mt6358-regulator.c b/drivers/regulator/mt6358-regulator.c
new file mode 100644
index 000000000000..fd528a3e55fd
--- /dev/null
+++ b/drivers/regulator/mt6358-regulator.c
@@ -0,0 +1,586 @@
+// SPDX-License-Identifier: GPL-2.0
+//
+// Copyright (c) 2019 MediaTek Inc.
+
+#include <linux/mfd/mt6358/registers.h>
+#include <linux/mfd/mt6397/core.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/regulator/driver.h>
+#include <linux/regulator/machine.h>
+#include <linux/regulator/mt6358-regulator.h>
+#include <linux/regulator/of_regulator.h>
+
+#define MT6358_BUCK_MODE_AUTO 0
+#define MT6358_BUCK_MODE_FORCE_PWM 1
+
+/*
+ * MT6358 regulators' information
+ *
+ * @desc: standard fields of regulator description.
+ * @qi: Mask for query enable signal status of regulators
+ */
+struct mt6358_regulator_info {
+ struct regulator_desc desc;
+ u32 status_reg;
+ u32 qi;
+ const u32 *index_table;
+ unsigned int n_table;
+ u32 vsel_shift;
+ u32 da_vsel_reg;
+ u32 da_vsel_mask;
+ u32 da_vsel_shift;
+ u32 modeset_reg;
+ u32 modeset_mask;
+ u32 modeset_shift;
+};
+
+#define MT6358_BUCK(match, vreg, min, max, step, \
+ volt_ranges, vosel_mask, _da_vsel_reg, _da_vsel_mask, \
+ _da_vsel_shift, _modeset_reg, _modeset_shift) \
+[MT6358_ID_##vreg] = { \
+ .desc = { \
+ .name = #vreg, \
+ .of_match = of_match_ptr(match), \
+ .ops = &mt6358_volt_range_ops, \
+ .type = REGULATOR_VOLTAGE, \
+ .id = MT6358_ID_##vreg, \
+ .owner = THIS_MODULE, \
+ .n_voltages = ((max) - (min)) / (step) + 1, \
+ .linear_ranges = volt_ranges, \
+ .n_linear_ranges = ARRAY_SIZE(volt_ranges), \
+ .vsel_reg = MT6358_BUCK_##vreg##_ELR0, \
+ .vsel_mask = vosel_mask, \
+ .enable_reg = MT6358_BUCK_##vreg##_CON0, \
+ .enable_mask = BIT(0), \
+ .of_map_mode = mt6358_map_mode, \
+ }, \
+ .status_reg = MT6358_BUCK_##vreg##_DBG1, \
+ .qi = BIT(0), \
+ .da_vsel_reg = _da_vsel_reg, \
+ .da_vsel_mask = _da_vsel_mask, \
+ .da_vsel_shift = _da_vsel_shift, \
+ .modeset_reg = _modeset_reg, \
+ .modeset_mask = BIT(_modeset_shift), \
+ .modeset_shift = _modeset_shift \
+}
+
+#define MT6358_LDO(match, vreg, ldo_volt_table, \
+ ldo_index_table, enreg, enbit, vosel, \
+ vosel_mask, vosel_shift) \
+[MT6358_ID_##vreg] = { \
+ .desc = { \
+ .name = #vreg, \
+ .of_match = of_match_ptr(match), \
+ .ops = &mt6358_volt_table_ops, \
+ .type = REGULATOR_VOLTAGE, \
+ .id = MT6358_ID_##vreg, \
+ .owner = THIS_MODULE, \
+ .n_voltages = ARRAY_SIZE(ldo_volt_table), \
+ .volt_table = ldo_volt_table, \
+ .vsel_reg = vosel, \
+ .vsel_mask = vosel_mask, \
+ .enable_reg = enreg, \
+ .enable_mask = BIT(enbit), \
+ }, \
+ .status_reg = MT6358_LDO_##vreg##_CON1, \
+ .qi = BIT(15), \
+ .index_table = ldo_index_table, \
+ .n_table = ARRAY_SIZE(ldo_index_table), \
+ .vsel_shift = vosel_shift, \
+}
+
+#define MT6358_LDO1(match, vreg, min, max, step, \
+ volt_ranges, _da_vsel_reg, _da_vsel_mask, \
+ _da_vsel_shift, vosel, vosel_mask) \
+[MT6358_ID_##vreg] = { \
+ .desc = { \
+ .name = #vreg, \
+ .of_match = of_match_ptr(match), \
+ .ops = &mt6358_volt_range_ops, \
+ .type = REGULATOR_VOLTAGE, \
+ .id = MT6358_ID_##vreg, \
+ .owner = THIS_MODULE, \
+ .n_voltages = ((max) - (min)) / (step) + 1, \
+ .linear_ranges = volt_ranges, \
+ .n_linear_ranges = ARRAY_SIZE(volt_ranges), \
+ .vsel_reg = vosel, \
+ .vsel_mask = vosel_mask, \
+ .enable_reg = MT6358_LDO_##vreg##_CON0, \
+ .enable_mask = BIT(0), \
+ }, \
+ .da_vsel_reg = _da_vsel_reg, \
+ .da_vsel_mask = _da_vsel_mask, \
+ .da_vsel_shift = _da_vsel_shift, \
+ .status_reg = MT6358_LDO_##vreg##_DBG1, \
+ .qi = BIT(0), \
+}
+
+#define MT6358_REG_FIXED(match, vreg, \
+ enreg, enbit, volt) \
+[MT6358_ID_##vreg] = { \
+ .desc = { \
+ .name = #vreg, \
+ .of_match = of_match_ptr(match), \
+ .ops = &mt6358_volt_fixed_ops, \
+ .type = REGULATOR_VOLTAGE, \
+ .id = MT6358_ID_##vreg, \
+ .owner = THIS_MODULE, \
+ .n_voltages = 1, \
+ .enable_reg = enreg, \
+ .enable_mask = BIT(enbit), \
+ .min_uV = volt, \
+ }, \
+ .status_reg = MT6358_LDO_##vreg##_CON1, \
+ .qi = BIT(15), \
+}
+
+static const struct regulator_linear_range buck_volt_range1[] = {
+ REGULATOR_LINEAR_RANGE(500000, 0, 0x7f, 6250),
+};
+
+static const struct regulator_linear_range buck_volt_range2[] = {
+ REGULATOR_LINEAR_RANGE(500000, 0, 0x7f, 12500),
+};
+
+static const struct regulator_linear_range buck_volt_range3[] = {
+ REGULATOR_LINEAR_RANGE(500000, 0, 0x3f, 50000),
+};
+
+static const struct regulator_linear_range buck_volt_range4[] = {
+ REGULATOR_LINEAR_RANGE(1000000, 0, 0x7f, 12500),
+};
+
+static const u32 vdram2_voltages[] = {
+ 600000, 1800000,
+};
+
+static const u32 vsim1_voltages[] = {
+ 1700000, 1800000, 2700000, 3000000, 3100000,
+};
+
+static const u32 vibr_voltages[] = {
+ 1200000, 1300000, 1500000, 1800000,
+ 2000000, 2800000, 3000000, 3300000,
+};
+
+static const u32 vusb_voltages[] = {
+ 3000000, 3100000,
+};
+
+static const u32 vcamd_voltages[] = {
+ 900000, 1000000, 1100000, 1200000,
+ 1300000, 1500000, 1800000,
+};
+
+static const u32 vefuse_voltages[] = {
+ 1700000, 1800000, 1900000,
+};
+
+static const u32 vmch_voltages[] = {
+ 2900000, 3000000, 3300000,
+};
+
+static const u32 vcama1_voltages[] = {
+ 1800000, 2500000, 2700000,
+ 2800000, 2900000, 3000000,
+};
+
+static const u32 vemc_voltages[] = {
+ 2900000, 3000000, 3300000,
+};
+
+static const u32 vcn33_bt_wifi_voltages[] = {
+ 3300000, 3400000, 3500000,
+};
+
+static const u32 vcama2_voltages[] = {
+ 1800000, 2500000, 2700000,
+ 2800000, 2900000, 3000000,
+};
+
+static const u32 vmc_voltages[] = {
+ 1800000, 2900000, 3000000, 3300000,
+};
+
+static const u32 vldo28_voltages[] = {
+ 2800000, 3000000,
+};
+
+static const u32 vsim2_voltages[] = {
+ 1700000, 1800000, 2700000,
+ 3000000, 3100000,
+};
+
+static const u32 vdram2_idx[] = {
+ 0, 12,
+};
+
+static const u32 vsim1_idx[] = {
+ 3, 4, 8, 11, 12,
+};
+
+static const u32 vibr_idx[] = {
+ 0, 1, 2, 4, 5, 9, 11, 13,
+};
+
+static const u32 vusb_idx[] = {
+ 3, 4,
+};
+
+static const u32 vcamd_idx[] = {
+ 3, 4, 5, 6, 7, 9, 12,
+};
+
+static const u32 vefuse_idx[] = {
+ 11, 12, 13,
+};
+
+static const u32 vmch_idx[] = {
+ 2, 3, 5,
+};
+
+static const u32 vcama1_idx[] = {
+ 0, 7, 9, 10, 11, 12,
+};
+
+static const u32 vemc_idx[] = {
+ 2, 3, 5,
+};
+
+static const u32 vcn33_bt_wifi_idx[] = {
+ 1, 2, 3,
+};
+
+static const u32 vcama2_idx[] = {
+ 0, 7, 9, 10, 11, 12,
+};
+
+static const u32 vmc_idx[] = {
+ 4, 10, 11, 13,
+};
+
+static const u32 vldo28_idx[] = {
+ 1, 3,
+};
+
+static const u32 vsim2_idx[] = {
+ 3, 4, 8, 11, 12,
+};
+
+static inline unsigned int mt6358_map_mode(unsigned int mode)
+{
+ return mode == MT6358_BUCK_MODE_AUTO ?
+ REGULATOR_MODE_NORMAL : REGULATOR_MODE_FAST;
+}
+
+static int mt6358_set_voltage_sel(struct regulator_dev *rdev,
+ unsigned int selector)
+{
+ int idx, ret;
+ const u32 *pvol;
+ struct mt6358_regulator_info *info = rdev_get_drvdata(rdev);
+
+ pvol = (const u32 *)info->index_table;
+
+ idx = pvol[selector];
+ ret = regmap_update_bits(rdev->regmap, info->desc.vsel_reg,
+ info->desc.vsel_mask,
+ idx << info->vsel_shift);
+
+ return ret;
+}
+
+static int mt6358_get_voltage_sel(struct regulator_dev *rdev)
+{
+ int idx, ret;
+ u32 selector;
+ struct mt6358_regulator_info *info = rdev_get_drvdata(rdev);
+ const u32 *pvol;
+
+ ret = regmap_read(rdev->regmap, info->desc.vsel_reg, &selector);
+ if (ret != 0) {
+ dev_info(&rdev->dev,
+ "Failed to get mt6358 %s vsel reg: %d\n",
+ info->desc.name, ret);
+ return ret;
+ }
+
+ selector = (selector & info->desc.vsel_mask) >> info->vsel_shift;
+ pvol = (const u32 *)info->index_table;
+ ret = -1;
+ for (idx = 0; idx < info->desc.n_voltages; idx++) {
+ if (pvol[idx] == selector) {
+ ret = idx;
+ break;
+ }
+ }
+
+ return ret;
+}
+
+static int mt6358_get_buck_voltage_sel(struct regulator_dev *rdev)
+{
+ int ret, regval;
+ struct mt6358_regulator_info *info = rdev_get_drvdata(rdev);
+
+ ret = regmap_read(rdev->regmap, info->da_vsel_reg, ®val);
+ if (ret != 0) {
+ dev_info(&rdev->dev,
+ "Failed to get mt6358 Buck %s vsel reg: %d\n",
+ info->desc.name, ret);
+ return ret;
+ }
+
+ ret = (regval >> info->da_vsel_shift) & info->da_vsel_mask;
+
+ return ret;
+}
+
+static int mt6358_get_status(struct regulator_dev *rdev)
+{
+ int ret;
+ u32 regval;
+ struct mt6358_regulator_info *info = rdev_get_drvdata(rdev);
+
+ ret = regmap_read(rdev->regmap, info->status_reg, ®val);
+ if (ret != 0) {
+ dev_info(&rdev->dev, "Failed to get enable reg: %d\n", ret);
+ return ret;
+ }
+
+ return (regval & info->qi) ? REGULATOR_STATUS_ON : REGULATOR_STATUS_OFF;
+}
+
+static int mt6358_regulator_set_mode(struct regulator_dev *rdev,
+ unsigned int mode)
+{
+ struct mt6358_regulator_info *info = rdev_get_drvdata(rdev);
+ int ret, val;
+
+ switch (mode) {
+ case REGULATOR_MODE_FAST:
+ val = MT6358_BUCK_MODE_FORCE_PWM;
+ break;
+ case REGULATOR_MODE_NORMAL:
+ val = MT6358_BUCK_MODE_AUTO;
+ break;
+ default:
+ ret = -EINVAL;
+ goto err_mode;
+ }
+
+ dev_dbg(&rdev->dev, "mt6358 buck set_mode %#x, %#x, %#x, %#x\n",
+ info->modeset_reg, info->modeset_mask,
+ info->modeset_shift, val);
+
+ val <<= info->modeset_shift;
+ ret = regmap_update_bits(rdev->regmap, info->modeset_reg,
+ info->modeset_mask, val);
+err_mode:
+ if (ret != 0) {
+ dev_err(&rdev->dev,
+ "Failed to set mt6358 buck mode: %d\n", ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+static unsigned int mt6358_regulator_get_mode(struct regulator_dev *rdev)
+{
+ struct mt6358_regulator_info *info = rdev_get_drvdata(rdev);
+ int ret, regval;
+
+ ret = regmap_read(rdev->regmap, info->modeset_reg, ®val);
+ if (ret != 0) {
+ dev_err(&rdev->dev,
+ "Failed to get mt6358 buck mode: %d\n", ret);
+ return ret;
+ }
+
+ switch ((regval & info->modeset_mask) >> info->modeset_shift) {
+ case MT6358_BUCK_MODE_AUTO:
+ return REGULATOR_MODE_NORMAL;
+ case MT6358_BUCK_MODE_FORCE_PWM:
+ return REGULATOR_MODE_FAST;
+ default:
+ return -EINVAL;
+ }
+}
+
+static const struct regulator_ops mt6358_volt_range_ops = {
+ .list_voltage = regulator_list_voltage_linear_range,
+ .map_voltage = regulator_map_voltage_linear_range,
+ .set_voltage_sel = regulator_set_voltage_sel_regmap,
+ .get_voltage_sel = mt6358_get_buck_voltage_sel,
+ .set_voltage_time_sel = regulator_set_voltage_time_sel,
+ .enable = regulator_enable_regmap,
+ .disable = regulator_disable_regmap,
+ .is_enabled = regulator_is_enabled_regmap,
+ .get_status = mt6358_get_status,
+ .set_mode = mt6358_regulator_set_mode,
+ .get_mode = mt6358_regulator_get_mode,
+};
+
+static const struct regulator_ops mt6358_volt_table_ops = {
+ .list_voltage = regulator_list_voltage_table,
+ .map_voltage = regulator_map_voltage_iterate,
+ .set_voltage_sel = mt6358_set_voltage_sel,
+ .get_voltage_sel = mt6358_get_voltage_sel,
+ .set_voltage_time_sel = regulator_set_voltage_time_sel,
+ .enable = regulator_enable_regmap,
+ .disable = regulator_disable_regmap,
+ .is_enabled = regulator_is_enabled_regmap,
+ .get_status = mt6358_get_status,
+};
+
+static const struct regulator_ops mt6358_volt_fixed_ops = {
+ .list_voltage = regulator_list_voltage_linear,
+ .enable = regulator_enable_regmap,
+ .disable = regulator_disable_regmap,
+ .is_enabled = regulator_is_enabled_regmap,
+ .get_status = mt6358_get_status,
+};
+
+/* The array is indexed by id(MT6358_ID_XXX) */
+static struct mt6358_regulator_info mt6358_regulators[] = {
+ MT6358_BUCK("buck_vdram1", VDRAM1, 500000, 2087500, 12500,
+ buck_volt_range2, 0x7f, MT6358_BUCK_VDRAM1_DBG0, 0x7f,
+ 0, MT6358_VDRAM1_ANA_CON0, 8),
+ MT6358_BUCK("buck_vcore", VCORE, 500000, 1293750, 6250,
+ buck_volt_range1, 0x7f, MT6358_BUCK_VCORE_DBG0, 0x7f,
+ 0, MT6358_VCORE_VGPU_ANA_CON0, 1),
+ MT6358_BUCK("buck_vpa", VPA, 500000, 3650000, 50000,
+ buck_volt_range3, 0x3f, MT6358_BUCK_VPA_DBG0, 0x3f, 0,
+ MT6358_VPA_ANA_CON0, 3),
+ MT6358_BUCK("buck_vproc11", VPROC11, 500000, 1293750, 6250,
+ buck_volt_range1, 0x7f, MT6358_BUCK_VPROC11_DBG0, 0x7f,
+ 0, MT6358_VPROC_ANA_CON0, 1),
+ MT6358_BUCK("buck_vproc12", VPROC12, 500000, 1293750, 6250,
+ buck_volt_range1, 0x7f, MT6358_BUCK_VPROC12_DBG0, 0x7f,
+ 0, MT6358_VPROC_ANA_CON0, 2),
+ MT6358_BUCK("buck_vgpu", VGPU, 500000, 1293750, 6250,
+ buck_volt_range1, 0x7f, MT6358_BUCK_VGPU_DBG0, 0x7f, 0,
+ MT6358_VCORE_VGPU_ANA_CON0, 2),
+ MT6358_BUCK("buck_vs2", VS2, 500000, 2087500, 12500,
+ buck_volt_range2, 0x7f, MT6358_BUCK_VS2_DBG0, 0x7f, 0,
+ MT6358_VS2_ANA_CON0, 8),
+ MT6358_BUCK("buck_vmodem", VMODEM, 500000, 1293750, 6250,
+ buck_volt_range1, 0x7f, MT6358_BUCK_VMODEM_DBG0, 0x7f,
+ 0, MT6358_VMODEM_ANA_CON0, 8),
+ MT6358_BUCK("buck_vs1", VS1, 1000000, 2587500, 12500,
+ buck_volt_range4, 0x7f, MT6358_BUCK_VS1_DBG0, 0x7f, 0,
+ MT6358_VS1_ANA_CON0, 8),
+ MT6358_REG_FIXED("ldo_vrf12", VRF12,
+ MT6358_LDO_VRF12_CON0, 0, 1200000),
+ MT6358_REG_FIXED("ldo_vio18", VIO18,
+ MT6358_LDO_VIO18_CON0, 0, 1800000),
+ MT6358_REG_FIXED("ldo_vcamio", VCAMIO,
+ MT6358_LDO_VCAMIO_CON0, 0, 1800000),
+ MT6358_REG_FIXED("ldo_vcn18", VCN18, MT6358_LDO_VCN18_CON0, 0, 1800000),
+ MT6358_REG_FIXED("ldo_vfe28", VFE28, MT6358_LDO_VFE28_CON0, 0, 2800000),
+ MT6358_REG_FIXED("ldo_vcn28", VCN28, MT6358_LDO_VCN28_CON0, 0, 2800000),
+ MT6358_REG_FIXED("ldo_vxo22", VXO22, MT6358_LDO_VXO22_CON0, 0, 2200000),
+ MT6358_REG_FIXED("ldo_vaux18", VAUX18,
+ MT6358_LDO_VAUX18_CON0, 0, 1800000),
+ MT6358_REG_FIXED("ldo_vbif28", VBIF28,
+ MT6358_LDO_VBIF28_CON0, 0, 2800000),
+ MT6358_REG_FIXED("ldo_vio28", VIO28, MT6358_LDO_VIO28_CON0, 0, 2800000),
+ MT6358_REG_FIXED("ldo_va12", VA12, MT6358_LDO_VA12_CON0, 0, 1200000),
+ MT6358_REG_FIXED("ldo_vrf18", VRF18, MT6358_LDO_VRF18_CON0, 0, 1800000),
+ MT6358_REG_FIXED("ldo_vaud28", VAUD28,
+ MT6358_LDO_VAUD28_CON0, 0, 2800000),
+ MT6358_LDO("ldo_vdram2", VDRAM2, vdram2_voltages, vdram2_idx,
+ MT6358_LDO_VDRAM2_CON0, 0, MT6358_LDO_VDRAM2_ELR0, 0x10, 0),
+ MT6358_LDO("ldo_vsim1", VSIM1, vsim1_voltages, vsim1_idx,
+ MT6358_LDO_VSIM1_CON0, 0, MT6358_VSIM1_ANA_CON0, 0xf00, 8),
+ MT6358_LDO("ldo_vibr", VIBR, vibr_voltages, vibr_idx,
+ MT6358_LDO_VIBR_CON0, 0, MT6358_VIBR_ANA_CON0, 0xf00, 8),
+ MT6358_LDO("ldo_vusb", VUSB, vusb_voltages, vusb_idx,
+ MT6358_LDO_VUSB_CON0_0, 0, MT6358_VUSB_ANA_CON0, 0x700, 8),
+ MT6358_LDO("ldo_vcamd", VCAMD, vcamd_voltages, vcamd_idx,
+ MT6358_LDO_VCAMD_CON0, 0, MT6358_VCAMD_ANA_CON0, 0xf00, 8),
+ MT6358_LDO("ldo_vefuse", VEFUSE, vefuse_voltages, vefuse_idx,
+ MT6358_LDO_VEFUSE_CON0, 0, MT6358_VEFUSE_ANA_CON0, 0xf00, 8),
+ MT6358_LDO("ldo_vmch", VMCH, vmch_voltages, vmch_idx,
+ MT6358_LDO_VMCH_CON0, 0, MT6358_VMCH_ANA_CON0, 0x700, 8),
+ MT6358_LDO("ldo_vcama1", VCAMA1, vcama1_voltages, vcama1_idx,
+ MT6358_LDO_VCAMA1_CON0, 0, MT6358_VCAMA1_ANA_CON0, 0xf00, 8),
+ MT6358_LDO("ldo_vemc", VEMC, vemc_voltages, vemc_idx,
+ MT6358_LDO_VEMC_CON0, 0, MT6358_VEMC_ANA_CON0, 0x700, 8),
+ MT6358_LDO("ldo_vcn33_bt", VCN33_BT, vcn33_bt_wifi_voltages,
+ vcn33_bt_wifi_idx, MT6358_LDO_VCN33_CON0_0,
+ 0, MT6358_VCN33_ANA_CON0, 0x300, 8),
+ MT6358_LDO("ldo_vcn33_wifi", VCN33_WIFI, vcn33_bt_wifi_voltages,
+ vcn33_bt_wifi_idx, MT6358_LDO_VCN33_CON0_1,
+ 0, MT6358_VCN33_ANA_CON0, 0x300, 8),
+ MT6358_LDO("ldo_vcama2", VCAMA2, vcama2_voltages, vcama2_idx,
+ MT6358_LDO_VCAMA2_CON0, 0, MT6358_VCAMA2_ANA_CON0, 0xf00, 8),
+ MT6358_LDO("ldo_vmc", VMC, vmc_voltages, vmc_idx,
+ MT6358_LDO_VMC_CON0, 0, MT6358_VMC_ANA_CON0, 0xf00, 8),
+ MT6358_LDO("ldo_vldo28", VLDO28, vldo28_voltages, vldo28_idx,
+ MT6358_LDO_VLDO28_CON0_0, 0,
+ MT6358_VLDO28_ANA_CON0, 0x300, 8),
+ MT6358_LDO("ldo_vsim2", VSIM2, vsim2_voltages, vsim2_idx,
+ MT6358_LDO_VSIM2_CON0, 0, MT6358_VSIM2_ANA_CON0, 0xf00, 8),
+ MT6358_LDO1("ldo_vsram_proc11", VSRAM_PROC11, 500000, 1293750, 6250,
+ buck_volt_range1, MT6358_LDO_VSRAM_PROC11_DBG0, 0x7f, 8,
+ MT6358_LDO_VSRAM_CON0, 0x7f),
+ MT6358_LDO1("ldo_vsram_others", VSRAM_OTHERS, 500000, 1293750, 6250,
+ buck_volt_range1, MT6358_LDO_VSRAM_OTHERS_DBG0, 0x7f, 8,
+ MT6358_LDO_VSRAM_CON2, 0x7f),
+ MT6358_LDO1("ldo_vsram_gpu", VSRAM_GPU, 500000, 1293750, 6250,
+ buck_volt_range1, MT6358_LDO_VSRAM_GPU_DBG0, 0x7f, 8,
+ MT6358_LDO_VSRAM_CON3, 0x7f),
+ MT6358_LDO1("ldo_vsram_proc12", VSRAM_PROC12, 500000, 1293750, 6250,
+ buck_volt_range1, MT6358_LDO_VSRAM_PROC12_DBG0, 0x7f, 8,
+ MT6358_LDO_VSRAM_CON1, 0x7f),
+};
+
+static int mt6358_regulator_probe(struct platform_device *pdev)
+{
+ struct mt6397_chip *mt6397 = dev_get_drvdata(pdev->dev.parent);
+ struct regulator_config config = {};
+ struct regulator_dev *rdev;
+ int i;
+
+ for (i = 0; i < MT6358_MAX_REGULATOR; i++) {
+ config.dev = &pdev->dev;
+ config.driver_data = &mt6358_regulators[i];
+ config.regmap = mt6397->regmap;
+
+ rdev = devm_regulator_register(&pdev->dev,
+ &mt6358_regulators[i].desc,
+ &config);
+ if (IS_ERR(rdev)) {
+ dev_err(&pdev->dev, "failed to register %s\n",
+ mt6358_regulators[i].desc.name);
+ return PTR_ERR(rdev);
+ }
+ }
+
+ return 0;
+}
+
+static const struct platform_device_id mt6358_platform_ids[] = {
+ {"mt6358-regulator", 0},
+ { /* sentinel */ },
+};
+MODULE_DEVICE_TABLE(platform, mt6358_platform_ids);
+
+static struct platform_driver mt6358_regulator_driver = {
+ .driver = {
+ .name = "mt6358-regulator",
+ },
+ .probe = mt6358_regulator_probe,
+ .id_table = mt6358_platform_ids,
+};
+
+module_platform_driver(mt6358_regulator_driver);
+
+MODULE_AUTHOR("Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>");
+MODULE_DESCRIPTION("Regulator Driver for MediaTek MT6358 PMIC");
+MODULE_LICENSE("GPL");
diff --git a/include/linux/regulator/mt6358-regulator.h b/include/linux/regulator/mt6358-regulator.h
new file mode 100644
index 000000000000..1cc304946d09
--- /dev/null
+++ b/include/linux/regulator/mt6358-regulator.h
@@ -0,0 +1,56 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ */
+
+#ifndef __LINUX_REGULATOR_MT6358_H
+#define __LINUX_REGULATOR_MT6358_H
+
+enum {
+ MT6358_ID_VDRAM1 = 0,
+ MT6358_ID_VCORE,
+ MT6358_ID_VPA,
+ MT6358_ID_VPROC11,
+ MT6358_ID_VPROC12,
+ MT6358_ID_VGPU,
+ MT6358_ID_VS2,
+ MT6358_ID_VMODEM,
+ MT6358_ID_VS1,
+ MT6358_ID_VDRAM2 = 9,
+ MT6358_ID_VSIM1,
+ MT6358_ID_VIBR,
+ MT6358_ID_VRF12,
+ MT6358_ID_VIO18,
+ MT6358_ID_VUSB,
+ MT6358_ID_VCAMIO,
+ MT6358_ID_VCAMD,
+ MT6358_ID_VCN18,
+ MT6358_ID_VFE28,
+ MT6358_ID_VSRAM_PROC11,
+ MT6358_ID_VCN28,
+ MT6358_ID_VSRAM_OTHERS,
+ MT6358_ID_VSRAM_GPU,
+ MT6358_ID_VXO22,
+ MT6358_ID_VEFUSE,
+ MT6358_ID_VAUX18,
+ MT6358_ID_VMCH,
+ MT6358_ID_VBIF28,
+ MT6358_ID_VSRAM_PROC12,
+ MT6358_ID_VCAMA1,
+ MT6358_ID_VEMC,
+ MT6358_ID_VIO28,
+ MT6358_ID_VA12,
+ MT6358_ID_VRF18,
+ MT6358_ID_VCN33_BT,
+ MT6358_ID_VCN33_WIFI,
+ MT6358_ID_VCAMA2,
+ MT6358_ID_VMC,
+ MT6358_ID_VLDO28,
+ MT6358_ID_VAUD28,
+ MT6358_ID_VSIM2,
+ MT6358_ID_RG_MAX,
+};
+
+#define MT6358_MAX_REGULATOR MT6358_ID_RG_MAX
+
+#endif /* __LINUX_REGULATOR_MT6358_H */
--
2.18.0
^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [PATCH v3 07/10] regulator: mt6358: Add support for MT6358 regulator
2019-05-03 9:31 ` [PATCH v3 07/10] regulator: mt6358: Add support for MT6358 regulator Hsin-Hsiung Wang
@ 2019-05-06 3:37 ` Mark Brown
2019-05-07 5:40 ` Nicolas Boichat
1 sibling, 0 replies; 22+ messages in thread
From: Mark Brown @ 2019-05-06 3:37 UTC (permalink / raw)
To: Hsin-Hsiung Wang
Cc: Lee Jones, Rob Herring, Matthias Brugger, Liam Girdwood,
Mark Rutland, Eddie Huang, Sean Wang, Alessandro Zummo,
Alexandre Belloni, devicetree, linux-arm-kernel, linux-mediatek,
linux-kernel, linux-rtc, srv_heupstream
[-- Attachment #1: Type: text/plain, Size: 1918 bytes --]
On Fri, May 03, 2019 at 05:31:14PM +0800, Hsin-Hsiung Wang wrote:
A few fairly minor things but mostly this looks good.
> +static const u32 vcama1_voltages[] = {
> + 1800000, 2500000, 2700000,
> + 2800000, 2900000, 3000000,
> +};
> +static const u32 vcama2_voltages[] = {
> + 1800000, 2500000, 2700000,
> + 2800000, 2900000, 3000000,
> +};
> +
These two tables look the same?
> +static int mt6358_get_voltage_sel(struct regulator_dev *rdev)
> +{
> + int idx, ret;
> + u32 selector;
> + struct mt6358_regulator_info *info = rdev_get_drvdata(rdev);
> + const u32 *pvol;
> +
> + ret = regmap_read(rdev->regmap, info->desc.vsel_reg, &selector);
> + if (ret != 0) {
> + dev_info(&rdev->dev,
> + "Failed to get mt6358 %s vsel reg: %d\n",
> + info->desc.name, ret);
> + return ret;
> + }
> +
> + selector = (selector & info->desc.vsel_mask) >> info->vsel_shift;
> + pvol = (const u32 *)info->index_table;
> + ret = -1;
> + for (idx = 0; idx < info->desc.n_voltages; idx++) {
> + if (pvol[idx] == selector) {
> + ret = idx;
> + break;
> + }
> + }
> +
> + return ret;
> +}
I don't entirely understand what this is intended to do which suggests
it could use some comments. As far as I can tell it's looking up the
hardware selector in a table and then using the index of the entry in
that table as the selector in order to deal with a sparse set of
selectors, is that right? You should be able to handle this by having
_list_voltage() return an error code for the invalid selectors though we
don't have helpers for that yet as it's an unusual design.
Also -1 is not a good return value in the case where you fail to do a
mapping, use -EINVAL.
> + ret = regmap_read(rdev->regmap, info->da_vsel_reg, ®val);
> + if (ret != 0) {
> + dev_info(&rdev->dev,
> + "Failed to get mt6358 Buck %s vsel reg: %d\n",
> + info->desc.name, ret);
> + return ret;
> + }
These error messages should be dev_err().
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^ permalink raw reply [flat|nested] 22+ messages in thread* Re: [PATCH v3 07/10] regulator: mt6358: Add support for MT6358 regulator
2019-05-03 9:31 ` [PATCH v3 07/10] regulator: mt6358: Add support for MT6358 regulator Hsin-Hsiung Wang
2019-05-06 3:37 ` Mark Brown
@ 2019-05-07 5:40 ` Nicolas Boichat
1 sibling, 0 replies; 22+ messages in thread
From: Nicolas Boichat @ 2019-05-07 5:40 UTC (permalink / raw)
To: Hsin-Hsiung Wang
Cc: Lee Jones, Rob Herring, Mark Brown, Matthias Brugger,
Mark Rutland, Alessandro Zummo, Alexandre Belloni,
srv_heupstream, devicetree, Sean Wang, Liam Girdwood, lkml,
moderated list:ARM/Mediatek SoC support, linux-arm Mailing List,
Eddie Huang, linux-rtc, Claire Chang
On Fri, May 3, 2019 at 6:34 PM Hsin-Hsiung Wang
<hsin-hsiung.wang@mediatek.com> wrote:
>
> The MT6358 is a regulator found on boards based on MediaTek MT8183 and
> probably other SoCs. It is a so called pmic and connects as a slave to
> SoC using SPI, wrapped inside the pmic-wrapper.
>
> Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>
> ---
> drivers/regulator/Kconfig | 9 +
> drivers/regulator/Makefile | 1 +
> drivers/regulator/mt6358-regulator.c | 586 +++++++++++++++++++++
> include/linux/regulator/mt6358-regulator.h | 56 ++
> 4 files changed, 652 insertions(+)
> create mode 100644 drivers/regulator/mt6358-regulator.c
> create mode 100644 include/linux/regulator/mt6358-regulator.h
>
> diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig
> index b7f249ee5e68..668e9716558c 100644
> --- a/drivers/regulator/Kconfig
> +++ b/drivers/regulator/Kconfig
> @@ -615,6 +615,15 @@ config REGULATOR_MT6323
> This driver supports the control of different power rails of device
> through regulator interface.
>
> +config REGULATOR_MT6358
> + tristate "MediaTek MT6358 PMIC"
> + depends on MFD_MT6397
> + help
> + Say y here to select this option to enable the power regulator of
> + MediaTek MT6358 PMIC.
> + This driver supports the control of different power rails of device
> + through regulator interface.
> +
> config REGULATOR_MT6380
> tristate "MediaTek MT6380 PMIC"
> depends on MTK_PMIC_WRAP
> diff --git a/drivers/regulator/Makefile b/drivers/regulator/Makefile
> index 1169f8a27d91..eeb60395c692 100644
> --- a/drivers/regulator/Makefile
> +++ b/drivers/regulator/Makefile
> @@ -79,6 +79,7 @@ obj-$(CONFIG_REGULATOR_MC13XXX_CORE) += mc13xxx-regulator-core.o
> obj-$(CONFIG_REGULATOR_MCP16502) += mcp16502.o
> obj-$(CONFIG_REGULATOR_MT6311) += mt6311-regulator.o
> obj-$(CONFIG_REGULATOR_MT6323) += mt6323-regulator.o
> +obj-$(CONFIG_REGULATOR_MT6358) += mt6358-regulator.o
> obj-$(CONFIG_REGULATOR_MT6380) += mt6380-regulator.o
> obj-$(CONFIG_REGULATOR_MT6397) += mt6397-regulator.o
> obj-$(CONFIG_REGULATOR_QCOM_RPM) += qcom_rpm-regulator.o
> diff --git a/drivers/regulator/mt6358-regulator.c b/drivers/regulator/mt6358-regulator.c
> new file mode 100644
> index 000000000000..fd528a3e55fd
> --- /dev/null
> +++ b/drivers/regulator/mt6358-regulator.c
> @@ -0,0 +1,586 @@
> +// SPDX-License-Identifier: GPL-2.0
> +//
> +// Copyright (c) 2019 MediaTek Inc.
> +
> +#include <linux/mfd/mt6358/registers.h>
> +#include <linux/mfd/mt6397/core.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/platform_device.h>
> +#include <linux/regmap.h>
> +#include <linux/regulator/driver.h>
> +#include <linux/regulator/machine.h>
> +#include <linux/regulator/mt6358-regulator.h>
> +#include <linux/regulator/of_regulator.h>
> +
> +#define MT6358_BUCK_MODE_AUTO 0
> +#define MT6358_BUCK_MODE_FORCE_PWM 1
> +
> +/*
> + * MT6358 regulators' information
> + *
> + * @desc: standard fields of regulator description.
> + * @qi: Mask for query enable signal status of regulators
> + */
> +struct mt6358_regulator_info {
> + struct regulator_desc desc;
> + u32 status_reg;
> + u32 qi;
> + const u32 *index_table;
> + unsigned int n_table;
> + u32 vsel_shift;
> + u32 da_vsel_reg;
> + u32 da_vsel_mask;
> + u32 da_vsel_shift;
> + u32 modeset_reg;
> + u32 modeset_mask;
> + u32 modeset_shift;
> +};
> +
> +#define MT6358_BUCK(match, vreg, min, max, step, \
> + volt_ranges, vosel_mask, _da_vsel_reg, _da_vsel_mask, \
> + _da_vsel_shift, _modeset_reg, _modeset_shift) \
> +[MT6358_ID_##vreg] = { \
> + .desc = { \
> + .name = #vreg, \
> + .of_match = of_match_ptr(match), \
> + .ops = &mt6358_volt_range_ops, \
> + .type = REGULATOR_VOLTAGE, \
> + .id = MT6358_ID_##vreg, \
> + .owner = THIS_MODULE, \
> + .n_voltages = ((max) - (min)) / (step) + 1, \
> + .linear_ranges = volt_ranges, \
> + .n_linear_ranges = ARRAY_SIZE(volt_ranges), \
> + .vsel_reg = MT6358_BUCK_##vreg##_ELR0, \
> + .vsel_mask = vosel_mask, \
> + .enable_reg = MT6358_BUCK_##vreg##_CON0, \
> + .enable_mask = BIT(0), \
> + .of_map_mode = mt6358_map_mode, \
> + }, \
> + .status_reg = MT6358_BUCK_##vreg##_DBG1, \
> + .qi = BIT(0), \
> + .da_vsel_reg = _da_vsel_reg, \
> + .da_vsel_mask = _da_vsel_mask, \
> + .da_vsel_shift = _da_vsel_shift, \
> + .modeset_reg = _modeset_reg, \
> + .modeset_mask = BIT(_modeset_shift), \
> + .modeset_shift = _modeset_shift \
> +}
> +
> +#define MT6358_LDO(match, vreg, ldo_volt_table, \
> + ldo_index_table, enreg, enbit, vosel, \
> + vosel_mask, vosel_shift) \
> +[MT6358_ID_##vreg] = { \
> + .desc = { \
> + .name = #vreg, \
> + .of_match = of_match_ptr(match), \
> + .ops = &mt6358_volt_table_ops, \
> + .type = REGULATOR_VOLTAGE, \
> + .id = MT6358_ID_##vreg, \
> + .owner = THIS_MODULE, \
> + .n_voltages = ARRAY_SIZE(ldo_volt_table), \
> + .volt_table = ldo_volt_table, \
> + .vsel_reg = vosel, \
> + .vsel_mask = vosel_mask, \
> + .enable_reg = enreg, \
> + .enable_mask = BIT(enbit), \
> + }, \
> + .status_reg = MT6358_LDO_##vreg##_CON1, \
> + .qi = BIT(15), \
> + .index_table = ldo_index_table, \
> + .n_table = ARRAY_SIZE(ldo_index_table), \
> + .vsel_shift = vosel_shift, \
> +}
> +
> +#define MT6358_LDO1(match, vreg, min, max, step, \
> + volt_ranges, _da_vsel_reg, _da_vsel_mask, \
> + _da_vsel_shift, vosel, vosel_mask) \
> +[MT6358_ID_##vreg] = { \
> + .desc = { \
> + .name = #vreg, \
> + .of_match = of_match_ptr(match), \
> + .ops = &mt6358_volt_range_ops, \
> + .type = REGULATOR_VOLTAGE, \
> + .id = MT6358_ID_##vreg, \
> + .owner = THIS_MODULE, \
> + .n_voltages = ((max) - (min)) / (step) + 1, \
> + .linear_ranges = volt_ranges, \
> + .n_linear_ranges = ARRAY_SIZE(volt_ranges), \
> + .vsel_reg = vosel, \
> + .vsel_mask = vosel_mask, \
> + .enable_reg = MT6358_LDO_##vreg##_CON0, \
> + .enable_mask = BIT(0), \
> + }, \
> + .da_vsel_reg = _da_vsel_reg, \
> + .da_vsel_mask = _da_vsel_mask, \
> + .da_vsel_shift = _da_vsel_shift, \
> + .status_reg = MT6358_LDO_##vreg##_DBG1, \
> + .qi = BIT(0), \
> +}
> +
> +#define MT6358_REG_FIXED(match, vreg, \
> + enreg, enbit, volt) \
> +[MT6358_ID_##vreg] = { \
> + .desc = { \
> + .name = #vreg, \
> + .of_match = of_match_ptr(match), \
> + .ops = &mt6358_volt_fixed_ops, \
> + .type = REGULATOR_VOLTAGE, \
> + .id = MT6358_ID_##vreg, \
> + .owner = THIS_MODULE, \
> + .n_voltages = 1, \
> + .enable_reg = enreg, \
> + .enable_mask = BIT(enbit), \
> + .min_uV = volt, \
> + }, \
> + .status_reg = MT6358_LDO_##vreg##_CON1, \
> + .qi = BIT(15), \
> +}
> +
> +static const struct regulator_linear_range buck_volt_range1[] = {
> + REGULATOR_LINEAR_RANGE(500000, 0, 0x7f, 6250),
> +};
> +
> +static const struct regulator_linear_range buck_volt_range2[] = {
> + REGULATOR_LINEAR_RANGE(500000, 0, 0x7f, 12500),
> +};
> +
> +static const struct regulator_linear_range buck_volt_range3[] = {
> + REGULATOR_LINEAR_RANGE(500000, 0, 0x3f, 50000),
> +};
> +
> +static const struct regulator_linear_range buck_volt_range4[] = {
> + REGULATOR_LINEAR_RANGE(1000000, 0, 0x7f, 12500),
> +};
> +
> +static const u32 vdram2_voltages[] = {
> + 600000, 1800000,
> +};
> +
> +static const u32 vsim1_voltages[] = {
> + 1700000, 1800000, 2700000, 3000000, 3100000,
> +};
> +
> +static const u32 vibr_voltages[] = {
> + 1200000, 1300000, 1500000, 1800000,
> + 2000000, 2800000, 3000000, 3300000,
> +};
> +
> +static const u32 vusb_voltages[] = {
> + 3000000, 3100000,
> +};
> +
> +static const u32 vcamd_voltages[] = {
> + 900000, 1000000, 1100000, 1200000,
> + 1300000, 1500000, 1800000,
> +};
> +
> +static const u32 vefuse_voltages[] = {
> + 1700000, 1800000, 1900000,
> +};
> +
> +static const u32 vmch_voltages[] = {
> + 2900000, 3000000, 3300000,
> +};
> +
> +static const u32 vcama1_voltages[] = {
> + 1800000, 2500000, 2700000,
> + 2800000, 2900000, 3000000,
> +};
> +
> +static const u32 vemc_voltages[] = {
> + 2900000, 3000000, 3300000,
> +};
> +
> +static const u32 vcn33_bt_wifi_voltages[] = {
> + 3300000, 3400000, 3500000,
> +};
> +
> +static const u32 vcama2_voltages[] = {
> + 1800000, 2500000, 2700000,
> + 2800000, 2900000, 3000000,
> +};
> +
> +static const u32 vmc_voltages[] = {
> + 1800000, 2900000, 3000000, 3300000,
> +};
> +
> +static const u32 vldo28_voltages[] = {
> + 2800000, 3000000,
> +};
> +
> +static const u32 vsim2_voltages[] = {
> + 1700000, 1800000, 2700000,
> + 3000000, 3100000,
> +};
> +
> +static const u32 vdram2_idx[] = {
> + 0, 12,
> +};
> +
> +static const u32 vsim1_idx[] = {
> + 3, 4, 8, 11, 12,
> +};
> +
> +static const u32 vibr_idx[] = {
> + 0, 1, 2, 4, 5, 9, 11, 13,
> +};
> +
> +static const u32 vusb_idx[] = {
> + 3, 4,
> +};
> +
> +static const u32 vcamd_idx[] = {
> + 3, 4, 5, 6, 7, 9, 12,
> +};
> +
> +static const u32 vefuse_idx[] = {
> + 11, 12, 13,
> +};
> +
> +static const u32 vmch_idx[] = {
> + 2, 3, 5,
> +};
> +
> +static const u32 vcama1_idx[] = {
> + 0, 7, 9, 10, 11, 12,
> +};
> +
> +static const u32 vemc_idx[] = {
> + 2, 3, 5,
> +};
> +
> +static const u32 vcn33_bt_wifi_idx[] = {
> + 1, 2, 3,
> +};
> +
> +static const u32 vcama2_idx[] = {
> + 0, 7, 9, 10, 11, 12,
> +};
> +
> +static const u32 vmc_idx[] = {
> + 4, 10, 11, 13,
> +};
> +
> +static const u32 vldo28_idx[] = {
> + 1, 3,
> +};
> +
> +static const u32 vsim2_idx[] = {
> + 3, 4, 8, 11, 12,
> +};
> +
> +static inline unsigned int mt6358_map_mode(unsigned int mode)
> +{
> + return mode == MT6358_BUCK_MODE_AUTO ?
> + REGULATOR_MODE_NORMAL : REGULATOR_MODE_FAST;
> +}
> +
> +static int mt6358_set_voltage_sel(struct regulator_dev *rdev,
> + unsigned int selector)
> +{
> + int idx, ret;
> + const u32 *pvol;
> + struct mt6358_regulator_info *info = rdev_get_drvdata(rdev);
> +
> + pvol = (const u32 *)info->index_table;
Why do you need that cast? I think info->index_table is already the right type.
> +
> + idx = pvol[selector];
> + ret = regmap_update_bits(rdev->regmap, info->desc.vsel_reg,
> + info->desc.vsel_mask,
> + idx << info->vsel_shift);
> +
> + return ret;
> +}
> +
> +static int mt6358_get_voltage_sel(struct regulator_dev *rdev)
> +{
> + int idx, ret;
> + u32 selector;
> + struct mt6358_regulator_info *info = rdev_get_drvdata(rdev);
> + const u32 *pvol;
> +
> + ret = regmap_read(rdev->regmap, info->desc.vsel_reg, &selector);
> + if (ret != 0) {
> + dev_info(&rdev->dev,
> + "Failed to get mt6358 %s vsel reg: %d\n",
> + info->desc.name, ret);
> + return ret;
> + }
> +
> + selector = (selector & info->desc.vsel_mask) >> info->vsel_shift;
> + pvol = (const u32 *)info->index_table;
> + ret = -1;
> + for (idx = 0; idx < info->desc.n_voltages; idx++) {
> + if (pvol[idx] == selector) {
> + ret = idx;
> + break;
On top of Mark's comment, I'd just return idx; here.
> + }
> + }
> +
> + return ret;
And return -1 here (or whatever better error code we should return).
> +}
> +
> +static int mt6358_get_buck_voltage_sel(struct regulator_dev *rdev)
> +{
> + int ret, regval;
> + struct mt6358_regulator_info *info = rdev_get_drvdata(rdev);
> +
> + ret = regmap_read(rdev->regmap, info->da_vsel_reg, ®val);
> + if (ret != 0) {
> + dev_info(&rdev->dev,
> + "Failed to get mt6358 Buck %s vsel reg: %d\n",
> + info->desc.name, ret);
> + return ret;
> + }
> +
> + ret = (regval >> info->da_vsel_shift) & info->da_vsel_mask;
> +
> + return ret;
> +}
> +
> +static int mt6358_get_status(struct regulator_dev *rdev)
> +{
> + int ret;
> + u32 regval;
> + struct mt6358_regulator_info *info = rdev_get_drvdata(rdev);
> +
> + ret = regmap_read(rdev->regmap, info->status_reg, ®val);
> + if (ret != 0) {
> + dev_info(&rdev->dev, "Failed to get enable reg: %d\n", ret);
> + return ret;
> + }
> +
> + return (regval & info->qi) ? REGULATOR_STATUS_ON : REGULATOR_STATUS_OFF;
> +}
> +
> +static int mt6358_regulator_set_mode(struct regulator_dev *rdev,
> + unsigned int mode)
> +{
> + struct mt6358_regulator_info *info = rdev_get_drvdata(rdev);
> + int ret, val;
> +
> + switch (mode) {
> + case REGULATOR_MODE_FAST:
> + val = MT6358_BUCK_MODE_FORCE_PWM;
> + break;
> + case REGULATOR_MODE_NORMAL:
> + val = MT6358_BUCK_MODE_AUTO;
> + break;
> + default:
> + ret = -EINVAL;
> + goto err_mode;
> + }
> +
> + dev_dbg(&rdev->dev, "mt6358 buck set_mode %#x, %#x, %#x, %#x\n",
> + info->modeset_reg, info->modeset_mask,
> + info->modeset_shift, val);
> +
> + val <<= info->modeset_shift;
> + ret = regmap_update_bits(rdev->regmap, info->modeset_reg,
> + info->modeset_mask, val);
> +err_mode:
> + if (ret != 0) {
> + dev_err(&rdev->dev,
> + "Failed to set mt6358 buck mode: %d\n", ret);
> + return ret;
Drop this line, and just do return ret below.
> + }
> +
> + return 0;
> +}
> +
> +static unsigned int mt6358_regulator_get_mode(struct regulator_dev *rdev)
> +{
> + struct mt6358_regulator_info *info = rdev_get_drvdata(rdev);
> + int ret, regval;
> +
> + ret = regmap_read(rdev->regmap, info->modeset_reg, ®val);
> + if (ret != 0) {
> + dev_err(&rdev->dev,
> + "Failed to get mt6358 buck mode: %d\n", ret);
> + return ret;
> + }
> +
> + switch ((regval & info->modeset_mask) >> info->modeset_shift) {
> + case MT6358_BUCK_MODE_AUTO:
> + return REGULATOR_MODE_NORMAL;
> + case MT6358_BUCK_MODE_FORCE_PWM:
> + return REGULATOR_MODE_FAST;
> + default:
> + return -EINVAL;
> + }
> +}
> +
> +static const struct regulator_ops mt6358_volt_range_ops = {
> + .list_voltage = regulator_list_voltage_linear_range,
> + .map_voltage = regulator_map_voltage_linear_range,
> + .set_voltage_sel = regulator_set_voltage_sel_regmap,
> + .get_voltage_sel = mt6358_get_buck_voltage_sel,
> + .set_voltage_time_sel = regulator_set_voltage_time_sel,
> + .enable = regulator_enable_regmap,
> + .disable = regulator_disable_regmap,
> + .is_enabled = regulator_is_enabled_regmap,
> + .get_status = mt6358_get_status,
> + .set_mode = mt6358_regulator_set_mode,
> + .get_mode = mt6358_regulator_get_mode,
> +};
> +
> +static const struct regulator_ops mt6358_volt_table_ops = {
> + .list_voltage = regulator_list_voltage_table,
> + .map_voltage = regulator_map_voltage_iterate,
> + .set_voltage_sel = mt6358_set_voltage_sel,
> + .get_voltage_sel = mt6358_get_voltage_sel,
> + .set_voltage_time_sel = regulator_set_voltage_time_sel,
> + .enable = regulator_enable_regmap,
> + .disable = regulator_disable_regmap,
> + .is_enabled = regulator_is_enabled_regmap,
> + .get_status = mt6358_get_status,
> +};
> +
> +static const struct regulator_ops mt6358_volt_fixed_ops = {
> + .list_voltage = regulator_list_voltage_linear,
> + .enable = regulator_enable_regmap,
> + .disable = regulator_disable_regmap,
> + .is_enabled = regulator_is_enabled_regmap,
> + .get_status = mt6358_get_status,
> +};
> +
> +/* The array is indexed by id(MT6358_ID_XXX) */
> +static struct mt6358_regulator_info mt6358_regulators[] = {
> + MT6358_BUCK("buck_vdram1", VDRAM1, 500000, 2087500, 12500,
> + buck_volt_range2, 0x7f, MT6358_BUCK_VDRAM1_DBG0, 0x7f,
> + 0, MT6358_VDRAM1_ANA_CON0, 8),
> + MT6358_BUCK("buck_vcore", VCORE, 500000, 1293750, 6250,
> + buck_volt_range1, 0x7f, MT6358_BUCK_VCORE_DBG0, 0x7f,
> + 0, MT6358_VCORE_VGPU_ANA_CON0, 1),
> + MT6358_BUCK("buck_vpa", VPA, 500000, 3650000, 50000,
> + buck_volt_range3, 0x3f, MT6358_BUCK_VPA_DBG0, 0x3f, 0,
> + MT6358_VPA_ANA_CON0, 3),
> + MT6358_BUCK("buck_vproc11", VPROC11, 500000, 1293750, 6250,
> + buck_volt_range1, 0x7f, MT6358_BUCK_VPROC11_DBG0, 0x7f,
> + 0, MT6358_VPROC_ANA_CON0, 1),
> + MT6358_BUCK("buck_vproc12", VPROC12, 500000, 1293750, 6250,
> + buck_volt_range1, 0x7f, MT6358_BUCK_VPROC12_DBG0, 0x7f,
> + 0, MT6358_VPROC_ANA_CON0, 2),
> + MT6358_BUCK("buck_vgpu", VGPU, 500000, 1293750, 6250,
> + buck_volt_range1, 0x7f, MT6358_BUCK_VGPU_DBG0, 0x7f, 0,
> + MT6358_VCORE_VGPU_ANA_CON0, 2),
> + MT6358_BUCK("buck_vs2", VS2, 500000, 2087500, 12500,
> + buck_volt_range2, 0x7f, MT6358_BUCK_VS2_DBG0, 0x7f, 0,
> + MT6358_VS2_ANA_CON0, 8),
> + MT6358_BUCK("buck_vmodem", VMODEM, 500000, 1293750, 6250,
> + buck_volt_range1, 0x7f, MT6358_BUCK_VMODEM_DBG0, 0x7f,
> + 0, MT6358_VMODEM_ANA_CON0, 8),
> + MT6358_BUCK("buck_vs1", VS1, 1000000, 2587500, 12500,
> + buck_volt_range4, 0x7f, MT6358_BUCK_VS1_DBG0, 0x7f, 0,
> + MT6358_VS1_ANA_CON0, 8),
> + MT6358_REG_FIXED("ldo_vrf12", VRF12,
> + MT6358_LDO_VRF12_CON0, 0, 1200000),
> + MT6358_REG_FIXED("ldo_vio18", VIO18,
> + MT6358_LDO_VIO18_CON0, 0, 1800000),
> + MT6358_REG_FIXED("ldo_vcamio", VCAMIO,
> + MT6358_LDO_VCAMIO_CON0, 0, 1800000),
> + MT6358_REG_FIXED("ldo_vcn18", VCN18, MT6358_LDO_VCN18_CON0, 0, 1800000),
> + MT6358_REG_FIXED("ldo_vfe28", VFE28, MT6358_LDO_VFE28_CON0, 0, 2800000),
> + MT6358_REG_FIXED("ldo_vcn28", VCN28, MT6358_LDO_VCN28_CON0, 0, 2800000),
> + MT6358_REG_FIXED("ldo_vxo22", VXO22, MT6358_LDO_VXO22_CON0, 0, 2200000),
> + MT6358_REG_FIXED("ldo_vaux18", VAUX18,
> + MT6358_LDO_VAUX18_CON0, 0, 1800000),
> + MT6358_REG_FIXED("ldo_vbif28", VBIF28,
> + MT6358_LDO_VBIF28_CON0, 0, 2800000),
> + MT6358_REG_FIXED("ldo_vio28", VIO28, MT6358_LDO_VIO28_CON0, 0, 2800000),
> + MT6358_REG_FIXED("ldo_va12", VA12, MT6358_LDO_VA12_CON0, 0, 1200000),
> + MT6358_REG_FIXED("ldo_vrf18", VRF18, MT6358_LDO_VRF18_CON0, 0, 1800000),
> + MT6358_REG_FIXED("ldo_vaud28", VAUD28,
> + MT6358_LDO_VAUD28_CON0, 0, 2800000),
> + MT6358_LDO("ldo_vdram2", VDRAM2, vdram2_voltages, vdram2_idx,
> + MT6358_LDO_VDRAM2_CON0, 0, MT6358_LDO_VDRAM2_ELR0, 0x10, 0),
> + MT6358_LDO("ldo_vsim1", VSIM1, vsim1_voltages, vsim1_idx,
> + MT6358_LDO_VSIM1_CON0, 0, MT6358_VSIM1_ANA_CON0, 0xf00, 8),
> + MT6358_LDO("ldo_vibr", VIBR, vibr_voltages, vibr_idx,
> + MT6358_LDO_VIBR_CON0, 0, MT6358_VIBR_ANA_CON0, 0xf00, 8),
> + MT6358_LDO("ldo_vusb", VUSB, vusb_voltages, vusb_idx,
> + MT6358_LDO_VUSB_CON0_0, 0, MT6358_VUSB_ANA_CON0, 0x700, 8),
> + MT6358_LDO("ldo_vcamd", VCAMD, vcamd_voltages, vcamd_idx,
> + MT6358_LDO_VCAMD_CON0, 0, MT6358_VCAMD_ANA_CON0, 0xf00, 8),
> + MT6358_LDO("ldo_vefuse", VEFUSE, vefuse_voltages, vefuse_idx,
> + MT6358_LDO_VEFUSE_CON0, 0, MT6358_VEFUSE_ANA_CON0, 0xf00, 8),
> + MT6358_LDO("ldo_vmch", VMCH, vmch_voltages, vmch_idx,
> + MT6358_LDO_VMCH_CON0, 0, MT6358_VMCH_ANA_CON0, 0x700, 8),
> + MT6358_LDO("ldo_vcama1", VCAMA1, vcama1_voltages, vcama1_idx,
> + MT6358_LDO_VCAMA1_CON0, 0, MT6358_VCAMA1_ANA_CON0, 0xf00, 8),
> + MT6358_LDO("ldo_vemc", VEMC, vemc_voltages, vemc_idx,
> + MT6358_LDO_VEMC_CON0, 0, MT6358_VEMC_ANA_CON0, 0x700, 8),
> + MT6358_LDO("ldo_vcn33_bt", VCN33_BT, vcn33_bt_wifi_voltages,
> + vcn33_bt_wifi_idx, MT6358_LDO_VCN33_CON0_0,
> + 0, MT6358_VCN33_ANA_CON0, 0x300, 8),
> + MT6358_LDO("ldo_vcn33_wifi", VCN33_WIFI, vcn33_bt_wifi_voltages,
> + vcn33_bt_wifi_idx, MT6358_LDO_VCN33_CON0_1,
> + 0, MT6358_VCN33_ANA_CON0, 0x300, 8),
> + MT6358_LDO("ldo_vcama2", VCAMA2, vcama2_voltages, vcama2_idx,
> + MT6358_LDO_VCAMA2_CON0, 0, MT6358_VCAMA2_ANA_CON0, 0xf00, 8),
> + MT6358_LDO("ldo_vmc", VMC, vmc_voltages, vmc_idx,
> + MT6358_LDO_VMC_CON0, 0, MT6358_VMC_ANA_CON0, 0xf00, 8),
> + MT6358_LDO("ldo_vldo28", VLDO28, vldo28_voltages, vldo28_idx,
> + MT6358_LDO_VLDO28_CON0_0, 0,
> + MT6358_VLDO28_ANA_CON0, 0x300, 8),
> + MT6358_LDO("ldo_vsim2", VSIM2, vsim2_voltages, vsim2_idx,
> + MT6358_LDO_VSIM2_CON0, 0, MT6358_VSIM2_ANA_CON0, 0xf00, 8),
> + MT6358_LDO1("ldo_vsram_proc11", VSRAM_PROC11, 500000, 1293750, 6250,
> + buck_volt_range1, MT6358_LDO_VSRAM_PROC11_DBG0, 0x7f, 8,
> + MT6358_LDO_VSRAM_CON0, 0x7f),
> + MT6358_LDO1("ldo_vsram_others", VSRAM_OTHERS, 500000, 1293750, 6250,
> + buck_volt_range1, MT6358_LDO_VSRAM_OTHERS_DBG0, 0x7f, 8,
> + MT6358_LDO_VSRAM_CON2, 0x7f),
> + MT6358_LDO1("ldo_vsram_gpu", VSRAM_GPU, 500000, 1293750, 6250,
> + buck_volt_range1, MT6358_LDO_VSRAM_GPU_DBG0, 0x7f, 8,
> + MT6358_LDO_VSRAM_CON3, 0x7f),
> + MT6358_LDO1("ldo_vsram_proc12", VSRAM_PROC12, 500000, 1293750, 6250,
> + buck_volt_range1, MT6358_LDO_VSRAM_PROC12_DBG0, 0x7f, 8,
> + MT6358_LDO_VSRAM_CON1, 0x7f),
> +};
> +
> +static int mt6358_regulator_probe(struct platform_device *pdev)
> +{
> + struct mt6397_chip *mt6397 = dev_get_drvdata(pdev->dev.parent);
> + struct regulator_config config = {};
> + struct regulator_dev *rdev;
> + int i;
> +
> + for (i = 0; i < MT6358_MAX_REGULATOR; i++) {
> + config.dev = &pdev->dev;
> + config.driver_data = &mt6358_regulators[i];
> + config.regmap = mt6397->regmap;
> +
> + rdev = devm_regulator_register(&pdev->dev,
> + &mt6358_regulators[i].desc,
> + &config);
> + if (IS_ERR(rdev)) {
> + dev_err(&pdev->dev, "failed to register %s\n",
> + mt6358_regulators[i].desc.name);
> + return PTR_ERR(rdev);
> + }
> + }
> +
> + return 0;
> +}
> +
> +static const struct platform_device_id mt6358_platform_ids[] = {
> + {"mt6358-regulator", 0},
> + { /* sentinel */ },
> +};
> +MODULE_DEVICE_TABLE(platform, mt6358_platform_ids);
> +
> +static struct platform_driver mt6358_regulator_driver = {
> + .driver = {
> + .name = "mt6358-regulator",
> + },
> + .probe = mt6358_regulator_probe,
> + .id_table = mt6358_platform_ids,
> +};
> +
> +module_platform_driver(mt6358_regulator_driver);
> +
> +MODULE_AUTHOR("Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>");
> +MODULE_DESCRIPTION("Regulator Driver for MediaTek MT6358 PMIC");
> +MODULE_LICENSE("GPL");
> diff --git a/include/linux/regulator/mt6358-regulator.h b/include/linux/regulator/mt6358-regulator.h
> new file mode 100644
> index 000000000000..1cc304946d09
> --- /dev/null
> +++ b/include/linux/regulator/mt6358-regulator.h
> @@ -0,0 +1,56 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Copyright (c) 2019 MediaTek Inc.
> + */
> +
> +#ifndef __LINUX_REGULATOR_MT6358_H
> +#define __LINUX_REGULATOR_MT6358_H
> +
> +enum {
> + MT6358_ID_VDRAM1 = 0,
> + MT6358_ID_VCORE,
> + MT6358_ID_VPA,
> + MT6358_ID_VPROC11,
> + MT6358_ID_VPROC12,
> + MT6358_ID_VGPU,
> + MT6358_ID_VS2,
> + MT6358_ID_VMODEM,
> + MT6358_ID_VS1,
> + MT6358_ID_VDRAM2 = 9,
> + MT6358_ID_VSIM1,
> + MT6358_ID_VIBR,
> + MT6358_ID_VRF12,
> + MT6358_ID_VIO18,
> + MT6358_ID_VUSB,
> + MT6358_ID_VCAMIO,
> + MT6358_ID_VCAMD,
> + MT6358_ID_VCN18,
> + MT6358_ID_VFE28,
> + MT6358_ID_VSRAM_PROC11,
> + MT6358_ID_VCN28,
> + MT6358_ID_VSRAM_OTHERS,
> + MT6358_ID_VSRAM_GPU,
> + MT6358_ID_VXO22,
> + MT6358_ID_VEFUSE,
> + MT6358_ID_VAUX18,
> + MT6358_ID_VMCH,
> + MT6358_ID_VBIF28,
> + MT6358_ID_VSRAM_PROC12,
> + MT6358_ID_VCAMA1,
> + MT6358_ID_VEMC,
> + MT6358_ID_VIO28,
> + MT6358_ID_VA12,
> + MT6358_ID_VRF18,
> + MT6358_ID_VCN33_BT,
> + MT6358_ID_VCN33_WIFI,
> + MT6358_ID_VCAMA2,
> + MT6358_ID_VMC,
> + MT6358_ID_VLDO28,
> + MT6358_ID_VAUD28,
> + MT6358_ID_VSIM2,
> + MT6358_ID_RG_MAX,
> +};
> +
> +#define MT6358_MAX_REGULATOR MT6358_ID_RG_MAX
> +
> +#endif /* __LINUX_REGULATOR_MT6358_H */
> --
> 2.18.0
>
>
> _______________________________________________
> Linux-mediatek mailing list
> Linux-mediatek@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH v3 08/10] arm64: dts: mt6358: add PMIC MT6358 related nodes
2019-05-03 9:31 [PATCH v3 00/10] Add Support for MediaTek PMIC MT6358 Hsin-Hsiung Wang
` (6 preceding siblings ...)
2019-05-03 9:31 ` [PATCH v3 07/10] regulator: mt6358: Add support for MT6358 regulator Hsin-Hsiung Wang
@ 2019-05-03 9:31 ` Hsin-Hsiung Wang
2019-05-08 8:00 ` Ran Bi
2019-05-03 9:31 ` [PATCH v3 09/10] rtc: mt6397: fix alarm register overwrite Hsin-Hsiung Wang
2019-05-03 9:31 ` [PATCH v3 10/10] rtc: Add support for the MediaTek MT6358 RTC Hsin-Hsiung Wang
9 siblings, 1 reply; 22+ messages in thread
From: Hsin-Hsiung Wang @ 2019-05-03 9:31 UTC (permalink / raw)
To: Lee Jones, Rob Herring, Mark Brown, Matthias Brugger
Cc: Liam Girdwood, Mark Rutland, Eddie Huang, Sean Wang,
Alessandro Zummo, Alexandre Belloni, Hsin-Hsiung Wang,
devicetree, linux-arm-kernel, linux-mediatek, linux-kernel,
linux-rtc, srv_heupstream
add PMIC MT6358 related nodes which is for MT8183 platform
Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt6358.dtsi | 358 +++++++++++++++++++++++
1 file changed, 358 insertions(+)
create mode 100644 arch/arm64/boot/dts/mediatek/mt6358.dtsi
diff --git a/arch/arm64/boot/dts/mediatek/mt6358.dtsi b/arch/arm64/boot/dts/mediatek/mt6358.dtsi
new file mode 100644
index 000000000000..74da59de3794
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt6358.dtsi
@@ -0,0 +1,358 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ */
+
+&pwrap {
+ pmic: mt6358 {
+ compatible = "mediatek,mt6358";
+ interrupt-controller;
+ interrupt-parent = <&pio>;
+ interrupts = <182 IRQ_TYPE_LEVEL_HIGH>;
+ #interrupt-cells = <2>;
+
+ mt6358codec: mt6358codec {
+ compatible = "mediatek,mt6358-sound";
+ };
+
+ mt6358regulator: mt6358regulator {
+ compatible = "mediatek,mt6358-regulator";
+
+ mt6358_vdram1_reg: buck_vdram1 {
+ regulator-compatible = "buck_vdram1";
+ regulator-name = "vdram1";
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <2087500>;
+ regulator-ramp-delay = <12500>;
+ regulator-enable-ramp-delay = <0>;
+ regulator-always-on;
+ regulator-allowed-modes = <0 1>;
+ };
+
+ mt6358_vcore_reg: buck_vcore {
+ regulator-name = "vcore";
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1293750>;
+ regulator-ramp-delay = <6250>;
+ regulator-enable-ramp-delay = <200>;
+ regulator-always-on;
+ regulator-allowed-modes = <0 1>;
+ };
+
+ mt6358_vpa_reg: buck_vpa {
+ regulator-name = "vpa";
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <3650000>;
+ regulator-ramp-delay = <50000>;
+ regulator-enable-ramp-delay = <250>;
+ regulator-allowed-modes = <0 1>;
+ };
+
+ mt6358_vproc11_reg: buck_vproc11 {
+ regulator-name = "vproc11";
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1293750>;
+ regulator-ramp-delay = <6250>;
+ regulator-enable-ramp-delay = <200>;
+ regulator-always-on;
+ regulator-allowed-modes = <0 1>;
+ };
+
+ mt6358_vproc12_reg: buck_vproc12 {
+ regulator-name = "vproc12";
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1293750>;
+ regulator-ramp-delay = <6250>;
+ regulator-enable-ramp-delay = <200>;
+ regulator-always-on;
+ regulator-allowed-modes = <0 1>;
+ };
+
+ mt6358_vgpu_reg: buck_vgpu {
+ regulator-name = "vgpu";
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1293750>;
+ regulator-ramp-delay = <6250>;
+ regulator-enable-ramp-delay = <200>;
+ regulator-allowed-modes = <0 1>;
+ };
+
+ mt6358_vs2_reg: buck_vs2 {
+ regulator-name = "vs2";
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <2087500>;
+ regulator-ramp-delay = <12500>;
+ regulator-enable-ramp-delay = <0>;
+ regulator-always-on;
+ };
+
+ mt6358_vmodem_reg: buck_vmodem {
+ regulator-name = "vmodem";
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1293750>;
+ regulator-ramp-delay = <6250>;
+ regulator-enable-ramp-delay = <900>;
+ regulator-always-on;
+ regulator-allowed-modes = <0 1>;
+ };
+
+ mt6358_vs1_reg: buck_vs1 {
+ regulator-name = "vs1";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <2587500>;
+ regulator-ramp-delay = <12500>;
+ regulator-enable-ramp-delay = <0>;
+ regulator-always-on;
+ };
+
+ mt6358_vdram2_reg: ldo_vdram2 {
+ regulator-name = "vdram2";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-enable-ramp-delay = <3300>;
+ };
+
+ mt6358_vsim1_reg: ldo_vsim1 {
+ regulator-name = "vsim1";
+ regulator-min-microvolt = <1700000>;
+ regulator-max-microvolt = <3100000>;
+ regulator-enable-ramp-delay = <540>;
+ };
+
+ mt6358_vibr_reg: ldo_vibr {
+ regulator-name = "vibr";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-enable-ramp-delay = <60>;
+ };
+
+ mt6358_vrf12_reg: ldo_vrf12 {
+ compatible = "regulator-fixed";
+ regulator-name = "vrf12";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-enable-ramp-delay = <120>;
+ };
+
+ mt6358_vio18_reg: ldo_vio18 {
+ compatible = "regulator-fixed";
+ regulator-name = "vio18";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-enable-ramp-delay = <2700>;
+ regulator-always-on;
+ };
+
+ mt6358_vusb_reg: ldo_vusb {
+ regulator-name = "vusb";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3100000>;
+ regulator-enable-ramp-delay = <270>;
+ regulator-always-on;
+ };
+
+ mt6358_vcamio_reg: ldo_vcamio {
+ compatible = "regulator-fixed";
+ regulator-name = "vcamio";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-enable-ramp-delay = <270>;
+ };
+
+ mt6358_vcamd_reg: ldo_vcamd {
+ regulator-name = "vcamd";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-enable-ramp-delay = <270>;
+ };
+
+ mt6358_vcn18_reg: ldo_vcn18 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcn18";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-enable-ramp-delay = <270>;
+ };
+
+ mt6358_vfe28_reg: ldo_vfe28 {
+ compatible = "regulator-fixed";
+ regulator-name = "vfe28";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-enable-ramp-delay = <270>;
+ };
+
+ mt6358_vsram_proc11_reg: ldo_vsram_proc11 {
+ regulator-name = "vsram_proc11";
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1293750>;
+ regulator-ramp-delay = <6250>;
+ regulator-enable-ramp-delay = <240>;
+ regulator-always-on;
+ };
+
+ mt6358_vcn28_reg: ldo_vcn28 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcn28";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-enable-ramp-delay = <270>;
+ };
+
+ mt6358_vsram_others_reg: ldo_vsram_others {
+ regulator-name = "vsram_others";
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1293750>;
+ regulator-ramp-delay = <6250>;
+ regulator-enable-ramp-delay = <240>;
+ regulator-always-on;
+ };
+
+ mt6358_vsram_gpu_reg: ldo_vsram_gpu {
+ regulator-name = "vsram_gpu";
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1293750>;
+ regulator-ramp-delay = <6250>;
+ regulator-enable-ramp-delay = <240>;
+ };
+
+ mt6358_vxo22_reg: ldo_vxo22 {
+ compatible = "regulator-fixed";
+ regulator-name = "vxo22";
+ regulator-min-microvolt = <2200000>;
+ regulator-max-microvolt = <2200000>;
+ regulator-enable-ramp-delay = <120>;
+ regulator-always-on;
+ };
+
+ mt6358_vefuse_reg: ldo_vefuse {
+ regulator-name = "vefuse";
+ regulator-min-microvolt = <1700000>;
+ regulator-max-microvolt = <1900000>;
+ regulator-enable-ramp-delay = <270>;
+ };
+
+ mt6358_vaux18_reg: ldo_vaux18 {
+ compatible = "regulator-fixed";
+ regulator-name = "vaux18";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-enable-ramp-delay = <270>;
+ };
+
+ mt6358_vmch_reg: ldo_vmch {
+ regulator-name = "vmch";
+ regulator-min-microvolt = <2900000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-enable-ramp-delay = <60>;
+ };
+
+ mt6358_vbif28_reg: ldo_vbif28 {
+ compatible = "regulator-fixed";
+ regulator-name = "vbif28";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-enable-ramp-delay = <270>;
+ };
+
+ mt6358_vsram_proc12_reg: ldo_vsram_proc12 {
+ regulator-name = "vsram_proc12";
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1293750>;
+ regulator-ramp-delay = <6250>;
+ regulator-enable-ramp-delay = <240>;
+ regulator-always-on;
+ };
+
+ mt6358_vcama1_reg: ldo_vcama1 {
+ regulator-name = "vcama1";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-enable-ramp-delay = <270>;
+ };
+
+ mt6358_vemc_reg: ldo_vemc {
+ regulator-name = "vemc";
+ regulator-min-microvolt = <2900000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-enable-ramp-delay = <60>;
+ regulator-always-on;
+ };
+
+ mt6358_vio28_reg: ldo_vio28 {
+ compatible = "regulator-fixed";
+ regulator-name = "vio28";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-enable-ramp-delay = <270>;
+ };
+
+ mt6358_va12_reg: ldo_va12 {
+ compatible = "regulator-fixed";
+ regulator-name = "va12";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-enable-ramp-delay = <270>;
+ regulator-always-on;
+ };
+
+ mt6358_vrf18_reg: ldo_vrf18 {
+ compatible = "regulator-fixed";
+ regulator-name = "vrf18";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-enable-ramp-delay = <120>;
+ };
+
+ mt6358_vcn33_bt_reg: ldo_vcn33_bt {
+ regulator-name = "vcn33_bt";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3500000>;
+ regulator-enable-ramp-delay = <270>;
+ };
+
+ mt6358_vcn33_wifi_reg: ldo_vcn33_wifi {
+ regulator-name = "vcn33_wifi";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3500000>;
+ regulator-enable-ramp-delay = <270>;
+ };
+
+ mt6358_vcama2_reg: ldo_vcama2 {
+ regulator-name = "vcama2";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-enable-ramp-delay = <270>;
+ };
+
+ mt6358_vmc_reg: ldo_vmc {
+ regulator-name = "vmc";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-enable-ramp-delay = <60>;
+ };
+
+ mt6358_vldo28_reg: ldo_vldo28 {
+ regulator-name = "vldo28";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-enable-ramp-delay = <270>;
+ };
+
+ mt6358_vaud28_reg: ldo_vaud28 {
+ compatible = "regulator-fixed";
+ regulator-name = "vaud28";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-enable-ramp-delay = <270>;
+ };
+
+ mt6358_vsim2_reg: ldo_vsim2 {
+ regulator-name = "vsim2";
+ regulator-min-microvolt = <1700000>;
+ regulator-max-microvolt = <3100000>;
+ regulator-enable-ramp-delay = <540>;
+ };
+ };
+ };
+};
--
2.18.0
^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [PATCH v3 08/10] arm64: dts: mt6358: add PMIC MT6358 related nodes
2019-05-03 9:31 ` [PATCH v3 08/10] arm64: dts: mt6358: add PMIC MT6358 related nodes Hsin-Hsiung Wang
@ 2019-05-08 8:00 ` Ran Bi
0 siblings, 0 replies; 22+ messages in thread
From: Ran Bi @ 2019-05-08 8:00 UTC (permalink / raw)
To: Hsin-Hsiung Wang
Cc: Lee Jones, Rob Herring, Mark Brown, Matthias Brugger,
Mark Rutland, Alessandro Zummo, Alexandre Belloni,
srv_heupstream, devicetree, Sean Wang, Liam Girdwood,
linux-kernel, linux-mediatek, linux-arm-kernel, Eddie Huang,
linux-rtc
On Fri, 2019-05-03 at 17:31 +0800, Hsin-Hsiung Wang wrote:
> add PMIC MT6358 related nodes which is for MT8183 platform
>
> Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>
> ---
> arch/arm64/boot/dts/mediatek/mt6358.dtsi | 358 +++++++++++++++++++++++
> 1 file changed, 358 insertions(+)
> create mode 100644 arch/arm64/boot/dts/mediatek/mt6358.dtsi
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt6358.dtsi b/arch/arm64/boot/dts/mediatek/mt6358.dtsi
> new file mode 100644
> index 000000000000..74da59de3794
> --- /dev/null
> +++ b/arch/arm64/boot/dts/mediatek/mt6358.dtsi
> @@ -0,0 +1,358 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +/*
> + * Copyright (c) 2019 MediaTek Inc.
> + */
> +
> +&pwrap {
> + pmic: mt6358 {
> + compatible = "mediatek,mt6358";
> + interrupt-controller;
> + interrupt-parent = <&pio>;
> + interrupts = <182 IRQ_TYPE_LEVEL_HIGH>;
> + #interrupt-cells = <2>;
> +
> + mt6358codec: mt6358codec {
> + compatible = "mediatek,mt6358-sound";
> + };
> +
> + mt6358regulator: mt6358regulator {
> + compatible = "mediatek,mt6358-regulator";
> +
> + mt6358_vdram1_reg: buck_vdram1 {
> + regulator-compatible = "buck_vdram1";
> + regulator-name = "vdram1";
> + regulator-min-microvolt = <500000>;
> + regulator-max-microvolt = <2087500>;
> + regulator-ramp-delay = <12500>;
> + regulator-enable-ramp-delay = <0>;
> + regulator-always-on;
> + regulator-allowed-modes = <0 1>;
> + };
> +
> + mt6358_vcore_reg: buck_vcore {
> + regulator-name = "vcore";
> + regulator-min-microvolt = <500000>;
> + regulator-max-microvolt = <1293750>;
> + regulator-ramp-delay = <6250>;
> + regulator-enable-ramp-delay = <200>;
> + regulator-always-on;
> + regulator-allowed-modes = <0 1>;
> + };
> +
> + mt6358_vpa_reg: buck_vpa {
> + regulator-name = "vpa";
> + regulator-min-microvolt = <500000>;
> + regulator-max-microvolt = <3650000>;
> + regulator-ramp-delay = <50000>;
> + regulator-enable-ramp-delay = <250>;
> + regulator-allowed-modes = <0 1>;
> + };
> +
> + mt6358_vproc11_reg: buck_vproc11 {
> + regulator-name = "vproc11";
> + regulator-min-microvolt = <500000>;
> + regulator-max-microvolt = <1293750>;
> + regulator-ramp-delay = <6250>;
> + regulator-enable-ramp-delay = <200>;
> + regulator-always-on;
> + regulator-allowed-modes = <0 1>;
> + };
> +
> + mt6358_vproc12_reg: buck_vproc12 {
> + regulator-name = "vproc12";
> + regulator-min-microvolt = <500000>;
> + regulator-max-microvolt = <1293750>;
> + regulator-ramp-delay = <6250>;
> + regulator-enable-ramp-delay = <200>;
> + regulator-always-on;
> + regulator-allowed-modes = <0 1>;
> + };
> +
> + mt6358_vgpu_reg: buck_vgpu {
> + regulator-name = "vgpu";
> + regulator-min-microvolt = <500000>;
> + regulator-max-microvolt = <1293750>;
> + regulator-ramp-delay = <6250>;
> + regulator-enable-ramp-delay = <200>;
> + regulator-allowed-modes = <0 1>;
> + };
> +
> + mt6358_vs2_reg: buck_vs2 {
> + regulator-name = "vs2";
> + regulator-min-microvolt = <500000>;
> + regulator-max-microvolt = <2087500>;
> + regulator-ramp-delay = <12500>;
> + regulator-enable-ramp-delay = <0>;
> + regulator-always-on;
> + };
> +
> + mt6358_vmodem_reg: buck_vmodem {
> + regulator-name = "vmodem";
> + regulator-min-microvolt = <500000>;
> + regulator-max-microvolt = <1293750>;
> + regulator-ramp-delay = <6250>;
> + regulator-enable-ramp-delay = <900>;
> + regulator-always-on;
> + regulator-allowed-modes = <0 1>;
> + };
> +
> + mt6358_vs1_reg: buck_vs1 {
> + regulator-name = "vs1";
> + regulator-min-microvolt = <1000000>;
> + regulator-max-microvolt = <2587500>;
> + regulator-ramp-delay = <12500>;
> + regulator-enable-ramp-delay = <0>;
> + regulator-always-on;
> + };
> +
> + mt6358_vdram2_reg: ldo_vdram2 {
> + regulator-name = "vdram2";
> + regulator-min-microvolt = <600000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-enable-ramp-delay = <3300>;
> + };
> +
> + mt6358_vsim1_reg: ldo_vsim1 {
> + regulator-name = "vsim1";
> + regulator-min-microvolt = <1700000>;
> + regulator-max-microvolt = <3100000>;
> + regulator-enable-ramp-delay = <540>;
> + };
> +
> + mt6358_vibr_reg: ldo_vibr {
> + regulator-name = "vibr";
> + regulator-min-microvolt = <1200000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-enable-ramp-delay = <60>;
> + };
> +
> + mt6358_vrf12_reg: ldo_vrf12 {
> + compatible = "regulator-fixed";
> + regulator-name = "vrf12";
> + regulator-min-microvolt = <1200000>;
> + regulator-max-microvolt = <1200000>;
> + regulator-enable-ramp-delay = <120>;
> + };
> +
> + mt6358_vio18_reg: ldo_vio18 {
> + compatible = "regulator-fixed";
> + regulator-name = "vio18";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-enable-ramp-delay = <2700>;
> + regulator-always-on;
> + };
> +
> + mt6358_vusb_reg: ldo_vusb {
> + regulator-name = "vusb";
> + regulator-min-microvolt = <3000000>;
> + regulator-max-microvolt = <3100000>;
> + regulator-enable-ramp-delay = <270>;
> + regulator-always-on;
> + };
> +
> + mt6358_vcamio_reg: ldo_vcamio {
> + compatible = "regulator-fixed";
> + regulator-name = "vcamio";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-enable-ramp-delay = <270>;
> + };
> +
> + mt6358_vcamd_reg: ldo_vcamd {
> + regulator-name = "vcamd";
> + regulator-min-microvolt = <900000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-enable-ramp-delay = <270>;
> + };
> +
> + mt6358_vcn18_reg: ldo_vcn18 {
> + compatible = "regulator-fixed";
> + regulator-name = "vcn18";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-enable-ramp-delay = <270>;
> + };
> +
> + mt6358_vfe28_reg: ldo_vfe28 {
> + compatible = "regulator-fixed";
> + regulator-name = "vfe28";
> + regulator-min-microvolt = <2800000>;
> + regulator-max-microvolt = <2800000>;
> + regulator-enable-ramp-delay = <270>;
> + };
> +
> + mt6358_vsram_proc11_reg: ldo_vsram_proc11 {
> + regulator-name = "vsram_proc11";
> + regulator-min-microvolt = <500000>;
> + regulator-max-microvolt = <1293750>;
> + regulator-ramp-delay = <6250>;
> + regulator-enable-ramp-delay = <240>;
> + regulator-always-on;
> + };
> +
> + mt6358_vcn28_reg: ldo_vcn28 {
> + compatible = "regulator-fixed";
> + regulator-name = "vcn28";
> + regulator-min-microvolt = <2800000>;
> + regulator-max-microvolt = <2800000>;
> + regulator-enable-ramp-delay = <270>;
> + };
> +
> + mt6358_vsram_others_reg: ldo_vsram_others {
> + regulator-name = "vsram_others";
> + regulator-min-microvolt = <500000>;
> + regulator-max-microvolt = <1293750>;
> + regulator-ramp-delay = <6250>;
> + regulator-enable-ramp-delay = <240>;
> + regulator-always-on;
> + };
> +
> + mt6358_vsram_gpu_reg: ldo_vsram_gpu {
> + regulator-name = "vsram_gpu";
> + regulator-min-microvolt = <500000>;
> + regulator-max-microvolt = <1293750>;
> + regulator-ramp-delay = <6250>;
> + regulator-enable-ramp-delay = <240>;
> + };
> +
> + mt6358_vxo22_reg: ldo_vxo22 {
> + compatible = "regulator-fixed";
> + regulator-name = "vxo22";
> + regulator-min-microvolt = <2200000>;
> + regulator-max-microvolt = <2200000>;
> + regulator-enable-ramp-delay = <120>;
> + regulator-always-on;
> + };
> +
> + mt6358_vefuse_reg: ldo_vefuse {
> + regulator-name = "vefuse";
> + regulator-min-microvolt = <1700000>;
> + regulator-max-microvolt = <1900000>;
> + regulator-enable-ramp-delay = <270>;
> + };
> +
> + mt6358_vaux18_reg: ldo_vaux18 {
> + compatible = "regulator-fixed";
> + regulator-name = "vaux18";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-enable-ramp-delay = <270>;
> + };
> +
> + mt6358_vmch_reg: ldo_vmch {
> + regulator-name = "vmch";
> + regulator-min-microvolt = <2900000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-enable-ramp-delay = <60>;
> + };
> +
> + mt6358_vbif28_reg: ldo_vbif28 {
> + compatible = "regulator-fixed";
> + regulator-name = "vbif28";
> + regulator-min-microvolt = <2800000>;
> + regulator-max-microvolt = <2800000>;
> + regulator-enable-ramp-delay = <270>;
> + };
> +
> + mt6358_vsram_proc12_reg: ldo_vsram_proc12 {
> + regulator-name = "vsram_proc12";
> + regulator-min-microvolt = <500000>;
> + regulator-max-microvolt = <1293750>;
> + regulator-ramp-delay = <6250>;
> + regulator-enable-ramp-delay = <240>;
> + regulator-always-on;
> + };
> +
> + mt6358_vcama1_reg: ldo_vcama1 {
> + regulator-name = "vcama1";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <3000000>;
> + regulator-enable-ramp-delay = <270>;
> + };
> +
> + mt6358_vemc_reg: ldo_vemc {
> + regulator-name = "vemc";
> + regulator-min-microvolt = <2900000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-enable-ramp-delay = <60>;
> + regulator-always-on;
> + };
> +
> + mt6358_vio28_reg: ldo_vio28 {
> + compatible = "regulator-fixed";
> + regulator-name = "vio28";
> + regulator-min-microvolt = <2800000>;
> + regulator-max-microvolt = <2800000>;
> + regulator-enable-ramp-delay = <270>;
> + };
> +
> + mt6358_va12_reg: ldo_va12 {
> + compatible = "regulator-fixed";
> + regulator-name = "va12";
> + regulator-min-microvolt = <1200000>;
> + regulator-max-microvolt = <1200000>;
> + regulator-enable-ramp-delay = <270>;
> + regulator-always-on;
> + };
> +
> + mt6358_vrf18_reg: ldo_vrf18 {
> + compatible = "regulator-fixed";
> + regulator-name = "vrf18";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-enable-ramp-delay = <120>;
> + };
> +
> + mt6358_vcn33_bt_reg: ldo_vcn33_bt {
> + regulator-name = "vcn33_bt";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3500000>;
> + regulator-enable-ramp-delay = <270>;
> + };
> +
> + mt6358_vcn33_wifi_reg: ldo_vcn33_wifi {
> + regulator-name = "vcn33_wifi";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3500000>;
> + regulator-enable-ramp-delay = <270>;
> + };
> +
> + mt6358_vcama2_reg: ldo_vcama2 {
> + regulator-name = "vcama2";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <3000000>;
> + regulator-enable-ramp-delay = <270>;
> + };
> +
> + mt6358_vmc_reg: ldo_vmc {
> + regulator-name = "vmc";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-enable-ramp-delay = <60>;
> + };
> +
> + mt6358_vldo28_reg: ldo_vldo28 {
> + regulator-name = "vldo28";
> + regulator-min-microvolt = <2800000>;
> + regulator-max-microvolt = <3000000>;
> + regulator-enable-ramp-delay = <270>;
> + };
> +
> + mt6358_vaud28_reg: ldo_vaud28 {
> + compatible = "regulator-fixed";
> + regulator-name = "vaud28";
> + regulator-min-microvolt = <2800000>;
> + regulator-max-microvolt = <2800000>;
> + regulator-enable-ramp-delay = <270>;
> + };
> +
> + mt6358_vsim2_reg: ldo_vsim2 {
> + regulator-name = "vsim2";
> + regulator-min-microvolt = <1700000>;
> + regulator-max-microvolt = <3100000>;
> + regulator-enable-ramp-delay = <540>;
> + };
> + };
Missing mt6358 rtc node here:
+ mt6358rtc: mt6358rtc {
+ compatible = "mediatek,mt6358-rtc";
+ };
> + };
> +};
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH v3 09/10] rtc: mt6397: fix alarm register overwrite
2019-05-03 9:31 [PATCH v3 00/10] Add Support for MediaTek PMIC MT6358 Hsin-Hsiung Wang
` (7 preceding siblings ...)
2019-05-03 9:31 ` [PATCH v3 08/10] arm64: dts: mt6358: add PMIC MT6358 related nodes Hsin-Hsiung Wang
@ 2019-05-03 9:31 ` Hsin-Hsiung Wang
2019-05-03 9:31 ` [PATCH v3 10/10] rtc: Add support for the MediaTek MT6358 RTC Hsin-Hsiung Wang
9 siblings, 0 replies; 22+ messages in thread
From: Hsin-Hsiung Wang @ 2019-05-03 9:31 UTC (permalink / raw)
To: Lee Jones, Rob Herring, Mark Brown, Matthias Brugger
Cc: Liam Girdwood, Mark Rutland, Eddie Huang, Sean Wang,
Alessandro Zummo, Alexandre Belloni, Hsin-Hsiung Wang,
devicetree, linux-arm-kernel, linux-mediatek, linux-kernel,
linux-rtc, srv_heupstream, Ran Bi
From: Ran Bi <ran.bi@mediatek.com>
Alarm registers high byte was reserved for other functions.
This add mask in alarm registers operation functions.
This also fix error condition in interrupt handler.
Fixes: fc2979118f3f ("rtc: mediatek: Add MT6397 RTC driver")
Signed-off-by: Ran Bi <ran.bi@mediatek.com>
---
drivers/rtc/rtc-mt6397.c | 47 ++++++++++++++++++++++++++++------------
1 file changed, 33 insertions(+), 14 deletions(-)
diff --git a/drivers/rtc/rtc-mt6397.c b/drivers/rtc/rtc-mt6397.c
index e9a25ec4d434..f85f1fc29e32 100644
--- a/drivers/rtc/rtc-mt6397.c
+++ b/drivers/rtc/rtc-mt6397.c
@@ -55,6 +55,14 @@
#define RTC_AL_SEC 0x0018
+#define RTC_AL_SEC_MASK 0x003f
+#define RTC_AL_MIN_MASK 0x003f
+#define RTC_AL_HOU_MASK 0x001f
+#define RTC_AL_DOM_MASK 0x001f
+#define RTC_AL_DOW_MASK 0x0007
+#define RTC_AL_MTH_MASK 0x000f
+#define RTC_AL_YEA_MASK 0x007f
+
#define RTC_PDN2 0x002e
#define RTC_PDN2_PWRON_ALARM BIT(4)
@@ -111,7 +119,7 @@ static irqreturn_t mtk_rtc_irq_handler_thread(int irq, void *data)
irqen = irqsta & ~RTC_IRQ_EN_AL;
mutex_lock(&rtc->lock);
if (regmap_write(rtc->regmap, rtc->addr_base + RTC_IRQ_EN,
- irqen) < 0)
+ irqen) == 0)
mtk_rtc_write_trigger(rtc);
mutex_unlock(&rtc->lock);
@@ -233,12 +241,12 @@ static int mtk_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alm)
alm->pending = !!(pdn2 & RTC_PDN2_PWRON_ALARM);
mutex_unlock(&rtc->lock);
- tm->tm_sec = data[RTC_OFFSET_SEC];
- tm->tm_min = data[RTC_OFFSET_MIN];
- tm->tm_hour = data[RTC_OFFSET_HOUR];
- tm->tm_mday = data[RTC_OFFSET_DOM];
- tm->tm_mon = data[RTC_OFFSET_MTH];
- tm->tm_year = data[RTC_OFFSET_YEAR];
+ tm->tm_sec = data[RTC_OFFSET_SEC] & RTC_AL_SEC_MASK;
+ tm->tm_min = data[RTC_OFFSET_MIN] & RTC_AL_MIN_MASK;
+ tm->tm_hour = data[RTC_OFFSET_HOUR] & RTC_AL_HOU_MASK;
+ tm->tm_mday = data[RTC_OFFSET_DOM] & RTC_AL_DOM_MASK;
+ tm->tm_mon = data[RTC_OFFSET_MTH] & RTC_AL_MTH_MASK;
+ tm->tm_year = data[RTC_OFFSET_YEAR] & RTC_AL_YEA_MASK;
tm->tm_year += RTC_MIN_YEAR_OFFSET;
tm->tm_mon--;
@@ -259,14 +267,25 @@ static int mtk_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alm)
tm->tm_year -= RTC_MIN_YEAR_OFFSET;
tm->tm_mon++;
- data[RTC_OFFSET_SEC] = tm->tm_sec;
- data[RTC_OFFSET_MIN] = tm->tm_min;
- data[RTC_OFFSET_HOUR] = tm->tm_hour;
- data[RTC_OFFSET_DOM] = tm->tm_mday;
- data[RTC_OFFSET_MTH] = tm->tm_mon;
- data[RTC_OFFSET_YEAR] = tm->tm_year;
-
mutex_lock(&rtc->lock);
+ ret = regmap_bulk_read(rtc->regmap, rtc->addr_base + RTC_AL_SEC,
+ data, RTC_OFFSET_COUNT);
+ if (ret < 0)
+ goto exit;
+
+ data[RTC_OFFSET_SEC] = ((data[RTC_OFFSET_SEC] & ~(RTC_AL_SEC_MASK)) |
+ (tm->tm_sec & RTC_AL_SEC_MASK));
+ data[RTC_OFFSET_MIN] = ((data[RTC_OFFSET_MIN] & ~(RTC_AL_MIN_MASK)) |
+ (tm->tm_min & RTC_AL_MIN_MASK));
+ data[RTC_OFFSET_HOUR] = ((data[RTC_OFFSET_HOUR] & ~(RTC_AL_HOU_MASK)) |
+ (tm->tm_hour & RTC_AL_HOU_MASK));
+ data[RTC_OFFSET_DOM] = ((data[RTC_OFFSET_DOM] & ~(RTC_AL_DOM_MASK)) |
+ (tm->tm_mday & RTC_AL_DOM_MASK));
+ data[RTC_OFFSET_MTH] = ((data[RTC_OFFSET_MTH] & ~(RTC_AL_MTH_MASK)) |
+ (tm->tm_mon & RTC_AL_MTH_MASK));
+ data[RTC_OFFSET_YEAR] = ((data[RTC_OFFSET_YEAR] & ~(RTC_AL_YEA_MASK)) |
+ (tm->tm_year & RTC_AL_YEA_MASK));
+
if (alm->enabled) {
ret = regmap_bulk_write(rtc->regmap,
rtc->addr_base + RTC_AL_SEC,
--
2.18.0
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH v3 10/10] rtc: Add support for the MediaTek MT6358 RTC
2019-05-03 9:31 [PATCH v3 00/10] Add Support for MediaTek PMIC MT6358 Hsin-Hsiung Wang
` (8 preceding siblings ...)
2019-05-03 9:31 ` [PATCH v3 09/10] rtc: mt6397: fix alarm register overwrite Hsin-Hsiung Wang
@ 2019-05-03 9:31 ` Hsin-Hsiung Wang
2019-05-04 14:04 ` Yingjoe Chen
9 siblings, 1 reply; 22+ messages in thread
From: Hsin-Hsiung Wang @ 2019-05-03 9:31 UTC (permalink / raw)
To: Lee Jones, Rob Herring, Mark Brown, Matthias Brugger
Cc: Liam Girdwood, Mark Rutland, Eddie Huang, Sean Wang,
Alessandro Zummo, Alexandre Belloni, Hsin-Hsiung Wang,
devicetree, linux-arm-kernel, linux-mediatek, linux-kernel,
linux-rtc, srv_heupstream, Ran Bi
From: Ran Bi <ran.bi@mediatek.com>
This add support for the MediaTek MT6358 RTC. Driver using
compatible data to store different RTC_WRTGR address offset.
Signed-off-by: Ran Bi <ran.bi@mediatek.com>
---
drivers/rtc/rtc-mt6397.c | 43 ++++++++++++++++++++++++++++++++--------
1 file changed, 35 insertions(+), 8 deletions(-)
diff --git a/drivers/rtc/rtc-mt6397.c b/drivers/rtc/rtc-mt6397.c
index f85f1fc29e32..3476e29db87c 100644
--- a/drivers/rtc/rtc-mt6397.c
+++ b/drivers/rtc/rtc-mt6397.c
@@ -20,6 +20,7 @@
#include <linux/irqdomain.h>
#include <linux/platform_device.h>
#include <linux/of_address.h>
+#include <linux/of_device.h>
#include <linux/of_irq.h>
#include <linux/io.h>
#include <linux/mfd/mt6397/core.h>
@@ -27,7 +28,8 @@
#define RTC_BBPU 0x0000
#define RTC_BBPU_CBUSY BIT(6)
-#define RTC_WRTGR 0x003c
+#define RTC_WRTGR_MT6358 0x3a
+#define RTC_WRTGR_MT6397 0x3c
#define RTC_IRQ_STA 0x0002
#define RTC_IRQ_STA_AL BIT(0)
@@ -71,6 +73,10 @@
#define RTC_NUM_YEARS 128
#define RTC_MIN_YEAR_OFFSET (RTC_MIN_YEAR - RTC_BASE_YEAR)
+struct mtk_rtc_compatible {
+ u32 wrtgr_addr;
+};
+
struct mt6397_rtc {
struct device *dev;
struct rtc_device *rtc_dev;
@@ -78,7 +84,25 @@ struct mt6397_rtc {
struct regmap *regmap;
int irq;
u32 addr_base;
+ const struct mtk_rtc_compatible *dev_comp;
+};
+
+static const struct mtk_rtc_compatible mt6358_rtc_compat = {
+ .wrtgr_addr = RTC_WRTGR_MT6358,
+};
+
+static const struct mtk_rtc_compatible mt6397_rtc_compat = {
+ .wrtgr_addr = RTC_WRTGR_MT6397,
+};
+
+static const struct of_device_id mt6397_rtc_of_match[] = {
+ { .compatible = "mediatek,mt6358-rtc",
+ .data = (void *)&mt6358_rtc_compat, },
+ { .compatible = "mediatek,mt6397-rtc",
+ .data = (void *)&mt6397_rtc_compat, },
+ {}
};
+MODULE_DEVICE_TABLE(of, mt6397_rtc_of_match);
static int mtk_rtc_write_trigger(struct mt6397_rtc *rtc)
{
@@ -86,7 +110,8 @@ static int mtk_rtc_write_trigger(struct mt6397_rtc *rtc)
int ret;
u32 data;
- ret = regmap_write(rtc->regmap, rtc->addr_base + RTC_WRTGR, 1);
+ ret = regmap_write(rtc->regmap,
+ rtc->addr_base + rtc->dev_comp->wrtgr_addr, 1);
if (ret < 0)
return ret;
@@ -332,6 +357,7 @@ static int mtk_rtc_probe(struct platform_device *pdev)
struct resource *res;
struct mt6397_chip *mt6397_chip = dev_get_drvdata(pdev->dev.parent);
struct mt6397_rtc *rtc;
+ const struct of_device_id *of_id;
int ret;
rtc = devm_kzalloc(&pdev->dev, sizeof(struct mt6397_rtc), GFP_KERNEL);
@@ -341,6 +367,13 @@ static int mtk_rtc_probe(struct platform_device *pdev)
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
rtc->addr_base = res->start;
+ of_id = of_match_device(mt6397_rtc_of_match, &pdev->dev);
+ if (!of_id) {
+ dev_err(&pdev->dev, "Failed to probe of_node\n");
+ return -EINVAL;
+ }
+ rtc->dev_comp = of_id->data;
+
rtc->irq = platform_get_irq(pdev, 0);
if (rtc->irq < 0)
return rtc->irq;
@@ -419,12 +452,6 @@ static int mt6397_rtc_resume(struct device *dev)
static SIMPLE_DEV_PM_OPS(mt6397_pm_ops, mt6397_rtc_suspend,
mt6397_rtc_resume);
-static const struct of_device_id mt6397_rtc_of_match[] = {
- { .compatible = "mediatek,mt6397-rtc", },
- { }
-};
-MODULE_DEVICE_TABLE(of, mt6397_rtc_of_match);
-
static struct platform_driver mtk_rtc_driver = {
.driver = {
.name = "mt6397-rtc",
--
2.18.0
^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [PATCH v3 10/10] rtc: Add support for the MediaTek MT6358 RTC
2019-05-03 9:31 ` [PATCH v3 10/10] rtc: Add support for the MediaTek MT6358 RTC Hsin-Hsiung Wang
@ 2019-05-04 14:04 ` Yingjoe Chen
0 siblings, 0 replies; 22+ messages in thread
From: Yingjoe Chen @ 2019-05-04 14:04 UTC (permalink / raw)
To: Hsin-Hsiung Wang
Cc: Lee Jones, Rob Herring, Mark Brown, Matthias Brugger,
Mark Rutland, Alessandro Zummo, Alexandre Belloni,
srv_heupstream, devicetree, Ran Bi, Sean Wang, Liam Girdwood,
linux-kernel, linux-mediatek, linux-arm-kernel, Eddie Huang,
linux-rtc
On Fri, 2019-05-03 at 17:31 +0800, Hsin-Hsiung Wang wrote:
> From: Ran Bi <ran.bi@mediatek.com>
>
> This add support for the MediaTek MT6358 RTC. Driver using
> compatible data to store different RTC_WRTGR address offset.
>
> Signed-off-by: Ran Bi <ran.bi@mediatek.com>
> ---
> drivers/rtc/rtc-mt6397.c | 43 ++++++++++++++++++++++++++++++++--------
> 1 file changed, 35 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/rtc/rtc-mt6397.c b/drivers/rtc/rtc-mt6397.c
> index f85f1fc29e32..3476e29db87c 100644
> --- a/drivers/rtc/rtc-mt6397.c
> +++ b/drivers/rtc/rtc-mt6397.c
> @@ -20,6 +20,7 @@
> #include <linux/irqdomain.h>
> #include <linux/platform_device.h>
> #include <linux/of_address.h>
> +#include <linux/of_device.h>
> #include <linux/of_irq.h>
> #include <linux/io.h>
> #include <linux/mfd/mt6397/core.h>
> @@ -27,7 +28,8 @@
> #define RTC_BBPU 0x0000
> #define RTC_BBPU_CBUSY BIT(6)
>
> -#define RTC_WRTGR 0x003c
> +#define RTC_WRTGR_MT6358 0x3a
> +#define RTC_WRTGR_MT6397 0x3c
>
> #define RTC_IRQ_STA 0x0002
> #define RTC_IRQ_STA_AL BIT(0)
> @@ -71,6 +73,10 @@
> #define RTC_NUM_YEARS 128
> #define RTC_MIN_YEAR_OFFSET (RTC_MIN_YEAR - RTC_BASE_YEAR)
>
> +struct mtk_rtc_compatible {
> + u32 wrtgr_addr;
> +};
> +
> struct mt6397_rtc {
> struct device *dev;
> struct rtc_device *rtc_dev;
> @@ -78,7 +84,25 @@ struct mt6397_rtc {
> struct regmap *regmap;
> int irq;
> u32 addr_base;
> + const struct mtk_rtc_compatible *dev_comp;
> +};
> +
> +static const struct mtk_rtc_compatible mt6358_rtc_compat = {
> + .wrtgr_addr = RTC_WRTGR_MT6358,
> +};
> +
> +static const struct mtk_rtc_compatible mt6397_rtc_compat = {
> + .wrtgr_addr = RTC_WRTGR_MT6397,
> +};
> +
> +static const struct of_device_id mt6397_rtc_of_match[] = {
> + { .compatible = "mediatek,mt6358-rtc",
> + .data = (void *)&mt6358_rtc_compat, },
> + { .compatible = "mediatek,mt6397-rtc",
> + .data = (void *)&mt6397_rtc_compat, },
> + {}
> };
> +MODULE_DEVICE_TABLE(of, mt6397_rtc_of_match);
>
> static int mtk_rtc_write_trigger(struct mt6397_rtc *rtc)
> {
> @@ -86,7 +110,8 @@ static int mtk_rtc_write_trigger(struct mt6397_rtc *rtc)
> int ret;
> u32 data;
>
> - ret = regmap_write(rtc->regmap, rtc->addr_base + RTC_WRTGR, 1);
> + ret = regmap_write(rtc->regmap,
> + rtc->addr_base + rtc->dev_comp->wrtgr_addr, 1);
> if (ret < 0)
> return ret;
>
> @@ -332,6 +357,7 @@ static int mtk_rtc_probe(struct platform_device *pdev)
> struct resource *res;
> struct mt6397_chip *mt6397_chip = dev_get_drvdata(pdev->dev.parent);
> struct mt6397_rtc *rtc;
> + const struct of_device_id *of_id;
> int ret;
>
> rtc = devm_kzalloc(&pdev->dev, sizeof(struct mt6397_rtc), GFP_KERNEL);
> @@ -341,6 +367,13 @@ static int mtk_rtc_probe(struct platform_device *pdev)
> res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> rtc->addr_base = res->start;
>
> + of_id = of_match_device(mt6397_rtc_of_match, &pdev->dev);
> + if (!of_id) {
This will never happens, but I'm fine with it.
Review-by: Yingjoe Chen <yingjoe.chen@mediatek.com>
Joe.C
^ permalink raw reply [flat|nested] 22+ messages in thread