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[62.107.28.193]) by smtp.googlemail.com with ESMTPSA id k9sm34057068wrd.7.2019.09.10.07.40.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Sep 2019 07:40:11 -0700 (PDT) From: Bruno Thomsen To: linux-rtc@vger.kernel.org Cc: alexandre.belloni@bootlin.com, a.zummo@towertech.it, u.kleine-koenig@pengutronix.de, bth@kamstrup.com, Bruno Thomsen Subject: [PATCH] rtc: pcf2127: default power management mode Date: Tue, 10 Sep 2019 16:39:45 +0200 Message-Id: <20190910143945.9364-1-bruno.thomsen@gmail.com> X-Mailer: git-send-email 2.21.0 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: linux-rtc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-rtc@vger.kernel.org This improves the rtc driver robustness by ensuring that the chip power management functions are operating in default mode. As out-of-tree drivers could have changed mode thus resulting in subtle differences that isn't immediately revealed on upgraded System-on-Modules (SoM). This happens since chip configuration is unchanged during reboot and power-cycle of the SoM. Signed-off-by: Bruno Thomsen --- drivers/rtc/rtc-pcf2127.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/drivers/rtc/rtc-pcf2127.c b/drivers/rtc/rtc-pcf2127.c index 02b069caffd5..694ec8eefea5 100644 --- a/drivers/rtc/rtc-pcf2127.c +++ b/drivers/rtc/rtc-pcf2127.c @@ -37,6 +37,9 @@ #define PCF2127_BIT_CTRL3_BLF BIT(2) #define PCF2127_BIT_CTRL3_BF BIT(3) #define PCF2127_BIT_CTRL3_BTSE BIT(4) +#define PCF2127_BIT_CTRL3_PWRMNG0 BIT(5) +#define PCF2127_BIT_CTRL3_PWRMNG1 BIT(6) +#define PCF2127_BIT_CTRL3_PWRMNG2 BIT(7) /* Time and date registers */ #define PCF2127_REG_SC 0x03 #define PCF2127_BIT_SC_OSF BIT(7) @@ -484,10 +487,22 @@ static int pcf2127_probe(struct device *dev, struct regmap *regmap, /* * Disable battery low/switch-over timestamp and interrupts. * Clear battery interrupt flags which can block new trigger events. + * Power management configuration: + * - Battery switch-over function is operating in standard mode. + * Hardware has to ensure VDD drops slower than 0.7 V/ms otherwise + * oscillator stop can occur. Since switch-over threshold is typical + * 2.5 V and sampled every 1 ms with a power management operating + * limit of 1.8 V. See NXP AN11186 for more info. + * - Battery low detection function is enabled. + * - Extra power fail detection function is enabled. + * * Note: This is the default chip behaviour but added to ensure * correct tamper timestamp and interrupt function. */ ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL3, + PCF2127_BIT_CTRL3_PWRMNG2 | + PCF2127_BIT_CTRL3_PWRMNG1 | + PCF2127_BIT_CTRL3_PWRMNG0 | PCF2127_BIT_CTRL3_BTSE | PCF2127_BIT_CTRL3_BF | PCF2127_BIT_CTRL3_BIE | -- 2.21.0