From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id EA90FC10F14 for ; Tue, 8 Oct 2019 11:37:43 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id CC83220673 for ; Tue, 8 Oct 2019 11:37:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730118AbfJHLhn (ORCPT ); Tue, 8 Oct 2019 07:37:43 -0400 Received: from spam01.hygon.cn ([110.188.70.11]:46016 "EHLO spam2.hygon.cn" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1730316AbfJHLhn (ORCPT ); Tue, 8 Oct 2019 07:37:43 -0400 Received: from MK-DB.hygon.cn ([172.23.18.60]) by spam2.hygon.cn with ESMTP id x98Bai4T009785; Tue, 8 Oct 2019 19:36:45 +0800 (GMT-8) (envelope-from fanjinke@hygon.cn) Received: from cncheex01.Hygon.cn ([172.23.18.10]) by MK-DB.hygon.cn with ESMTP id x98BaTN1019959; Tue, 8 Oct 2019 19:36:29 +0800 (GMT-8) (envelope-from fanjinke@hygon.cn) Received: from bogon.higon.com (172.23.18.44) by cncheex01.Hygon.cn (172.23.18.10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1466.3; Tue, 8 Oct 2019 19:36:41 +0800 From: Jinke Fan To: , , , , CC: , , Jinke Fan Subject: [PATCH v3] rtc: Fix the AltCentury value on AMD/Hygon platform Date: Tue, 8 Oct 2019 19:36:16 +0800 Message-ID: <20191008113616.103734-1-fanjinke@hygon.cn> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [172.23.18.44] X-ClientProxiedBy: cncheex01.Hygon.cn (172.23.18.10) To cncheex01.Hygon.cn (172.23.18.10) X-MAIL: spam2.hygon.cn x98Bai4T009785 X-DNSRBL: Sender: linux-rtc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-rtc@vger.kernel.org When using following operations: date -s "21190910 19:20:00" hwclock -w to change date from 2019 to 2119 for test, it will fail on Hygon Dhyana and AMD Zen CPUs, while the same operations run ok on Intel i7 platform. MC146818 driver use function mc146818_set_time() to set register RTC_FREQ_SELECT(RTC_REG_A)'s bit4-bit6 field which means divider stage reset value on Intel platform to 0x7. While AMD/Hygon RTC_REG_A(0Ah)'s bit4 is defined as DV0 [Reference]: DV0 = 0 selects Bank 0, DV0 = 1 selects Bank 1. Bit5-bit6 is defined as reserved. DV0 is set to 1, it will select Bank 1, which will disable AltCentury register(0x32) access. As UEFI pass acpi_gbl_FADT.century 0x32 (AltCentury), the CMOS write will be failed on code: CMOS_WRITE(century, acpi_gbl_FADT.century). Correct RTC_REG_A bank select bit(DV0) to 0 on AMD/Hygon CPUs, it will enable AltCentury(0x32) register writing and finally setup century as expected. Test results on AMD/Hygon machine show that it works as expected. Reference: https://www.amd.com/system/files/TechDocs/51192_Bolton_FCH_RRG.pdf section: 3.13 Real Time Clock (RTC) Reported-by: kbuild test robot Signed-off-by: Jinke Fan --- v2->v3: - Make the changes only relevant to AMD/Hygon. v1->v2: - Fix the compile errors on sparc64/alpha platform. drivers/rtc/rtc-mc146818-lib.c | 11 ++++++++++- include/linux/mc146818rtc.h | 6 ++++++ 2 files changed, 16 insertions(+), 1 deletion(-) diff --git a/drivers/rtc/rtc-mc146818-lib.c b/drivers/rtc/rtc-mc146818-lib.c index 2ecd8752b088..70502881785d 100644 --- a/drivers/rtc/rtc-mc146818-lib.c +++ b/drivers/rtc/rtc-mc146818-lib.c @@ -172,7 +172,16 @@ int mc146818_set_time(struct rtc_time *time) save_control = CMOS_READ(RTC_CONTROL); CMOS_WRITE((save_control|RTC_SET), RTC_CONTROL); save_freq_select = CMOS_READ(RTC_FREQ_SELECT); - CMOS_WRITE((save_freq_select|RTC_DIV_RESET2), RTC_FREQ_SELECT); + +#ifdef CONFIG_X86 + if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD || + boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) + CMOS_WRITE((save_freq_select & (~RTC_DV0)), RTC_FREQ_SELECT); + else + CMOS_WRITE((save_freq_select | RTC_DIV_RESET2), RTC_FREQ_SELECT); +#else + CMOS_WRITE((save_freq_select | RTC_DIV_RESET2), RTC_FREQ_SELECT); +#endif #ifdef CONFIG_MACH_DECSTATION CMOS_WRITE(real_yrs, RTC_DEC_YEAR); diff --git a/include/linux/mc146818rtc.h b/include/linux/mc146818rtc.h index 0661af17a758..7066a7bced61 100644 --- a/include/linux/mc146818rtc.h +++ b/include/linux/mc146818rtc.h @@ -86,6 +86,12 @@ struct cmos_rtc_board_info { /* 2 values for divider stage reset, others for "testing purposes only" */ # define RTC_DIV_RESET1 0x60 # define RTC_DIV_RESET2 0x70 + +#ifdef CONFIG_X86 + /* DV0 = 0 selects Bank 0, DV0 = 1 selects Bank 1 on AMD/Hygon platform */ +# define RTC_DV0 0x10 +#endif + /* Periodic intr. / Square wave rate select. 0=none, 1=32.8kHz,... 15=2Hz */ # define RTC_RATE_SELECT 0x0F -- 2.17.1