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Fri, 27 Mar 2020 12:03:07 -0700 (PDT) Received: from rob-hp-laptop ([64.188.179.250]) by smtp.gmail.com with ESMTPSA id i6sm2148350ila.20.2020.03.27.12.03.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Mar 2020 12:03:06 -0700 (PDT) Received: (nullmailer pid 28795 invoked by uid 1000); Fri, 27 Mar 2020 19:03:04 -0000 Date: Fri, 27 Mar 2020 13:03:04 -0600 From: Rob Herring To: Lubomir Rintel Cc: Linus Walleij , Bartosz Golaszewski , Thomas Gleixner , Jason Cooper , Marc Zyngier , Mauro Carvalho Chehab , Ulf Hansson , Kishon Vijay Abraham I , Alessandro Zummo , Alexandre Belloni , Greg Kroah-Hartman , Mark Brown , Daniel Lezcano , Andrew Lunn , Gregory Clement , Daniel Mack , Haojian Zhuang , Robert Jarzmik , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-i2c@vger.kernel.org, linux-media@vger.kernel.org, linux-mmc@vger.kernel.org, linux-rtc@vger.kernel.org, linux-serial@vger.kernel.org, linux-spi@vger.kernel.org, linux-usb@vger.kernel.org Subject: Re: [PATCH 14/28] dt-bindings: arm: l2x0: Tauros 3 is PL310 compatible Message-ID: <20200327190304.GA27639@bogus> References: <20200317093922.20785-1-lkundrak@v3.sk> <20200317093922.20785-15-lkundrak@v3.sk> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20200317093922.20785-15-lkundrak@v3.sk> User-Agent: Mutt/1.10.1 (2018-07-13) Sender: linux-rtc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-rtc@vger.kernel.org On Tue, Mar 17, 2020 at 10:39:08AM +0100, Lubomir Rintel wrote: > The validation is unhappy about mmp3-dell-ariel declaring its > marvell,tauros3-cache node to be compatible with arm,pl310-cache: > > mmp3-dell-ariel.dt.yaml: cache-controller@d0020000: compatible: > Additional items are not allowed ('arm,pl310-cache' was unexpected) > mmp3-dell-ariel.dt.yaml: cache-controller@d0020000: compatible: > ['marvell,tauros3-cache', 'arm,pl310-cache'] is too long > > Let's allow this -- Tauros 3 is designed to be compatible with PL310. > > Signed-off-by: Lubomir Rintel > --- > .../devicetree/bindings/arm/l2c2x0.yaml | 45 ++++++++++--------- > 1 file changed, 24 insertions(+), 21 deletions(-) > > diff --git a/Documentation/devicetree/bindings/arm/l2c2x0.yaml b/Documentation/devicetree/bindings/arm/l2c2x0.yaml > index 913a8cd8b2c00..7e39088a9bed2 100644 > --- a/Documentation/devicetree/bindings/arm/l2c2x0.yaml > +++ b/Documentation/devicetree/bindings/arm/l2c2x0.yaml > @@ -29,27 +29,30 @@ allOf: > > properties: > compatible: > - enum: > - - arm,pl310-cache > - - arm,l220-cache > - - arm,l210-cache > - # DEPRECATED by "brcm,bcm11351-a2-pl310-cache" > - - bcm,bcm11351-a2-pl310-cache > - # For Broadcom bcm11351 chipset where an > - # offset needs to be added to the address before passing down to the L2 > - # cache controller > - - brcm,bcm11351-a2-pl310-cache > - # Marvell Controller designed to be > - # compatible with the ARM one, with system cache mode (meaning > - # maintenance operations on L1 are broadcasted to the L2 and L2 > - # performs the same operation). > - - marvell,aurora-system-cache > - # Marvell Controller designed to be > - # compatible with the ARM one with outer cache mode. > - - marvell,aurora-outer-cache > - # Marvell Tauros3 cache controller, compatible > - # with arm,pl310-cache controller. > - - marvell,tauros3-cache > + oneOf: > + - enum: > + - arm,pl310-cache The list should be indented 2 more spaces. I'll fixup when applying. > + - arm,l220-cache > + - arm,l210-cache > + # DEPRECATED by "brcm,bcm11351-a2-pl310-cache" > + - bcm,bcm11351-a2-pl310-cache > + # For Broadcom bcm11351 chipset where an > + # offset needs to be added to the address before passing down to the L2 > + # cache controller > + - brcm,bcm11351-a2-pl310-cache > + # Marvell Controller designed to be > + # compatible with the ARM one, with system cache mode (meaning > + # maintenance operations on L1 are broadcasted to the L2 and L2 > + # performs the same operation). > + - marvell,aurora-system-cache > + # Marvell Controller designed to be > + # compatible with the ARM one with outer cache mode. > + - marvell,aurora-outer-cache > + - items: > + # Marvell Tauros3 cache controller, compatible > + # with arm,pl310-cache controller. > + - const: marvell,tauros3-cache > + - const: arm,pl310-cache > > cache-level: > const: 2 > -- > 2.25.1 >