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* [PATCH v2] rtc: Fix the AltCentury value on AMD/Hygon platform
@ 2019-10-08  9:37 Jinke Fan
  2019-10-08  9:44 ` Alexandre Belloni
  0 siblings, 1 reply; 3+ messages in thread
From: Jinke Fan @ 2019-10-08  9:37 UTC (permalink / raw)
  To: a.zummo, alexandre.belloni, puwen, thomas.lendacky, kim.phillips
  Cc: linux-rtc, linux-kernel, Jinke Fan

When using following operations:
date -s "21190910 19:20:00"
hwclock -w
to change date from 2019 to 2119 for test, it will fail on Hygon
Dhyana and AMD Zen CPUs, while the same operations run ok on Intel i7
platform.

MC146818 driver use function mc146818_set_time() to set register
RTC_FREQ_SELECT(RTC_REG_A)'s bit4-bit6 field which means divider stage
reset value on Intel platform to 0x7.

While AMD/Hygon RTC_REG_A(0Ah)'s bit4 is defined as DV0 [Reference]:
DV0 = 0 selects Bank 0, DV0 = 1 selects Bank 1. Bit5-bit6 is defined
as reserved.

DV0 is set to 1, it will select Bank 1, which will disable AltCentury
register(0x32) access. As UEFI pass acpi_gbl_FADT.century 0x32
(AltCentury), the CMOS write will be failed on code:
CMOS_WRITE(century, acpi_gbl_FADT.century).

Correct RTC_REG_A bank select bit(DV0) to 0 on AMD/Hygon CPUs, it will
enable AltCentury(0x32) register writing and finally setup century as
expected.

Test results on AMD/Hygon machine show that it works as expected.

Reference:
https://www.amd.com/system/files/TechDocs/51192_Bolton_FCH_RRG.pdf
section: 3.13 Real Time Clock (RTC)

Reported-by: kbuild test robot <lkp@intel.com>
Signed-off-by: Jinke Fan <fanjinke@hygon.cn>
---
 drivers/rtc/rtc-mc146818-lib.c | 9 +++++++--
 include/linux/mc146818rtc.h    | 6 ++++++
 2 files changed, 13 insertions(+), 2 deletions(-)

diff --git a/drivers/rtc/rtc-mc146818-lib.c b/drivers/rtc/rtc-mc146818-lib.c
index 2ecd8752b088..a821dbe215d3 100644
--- a/drivers/rtc/rtc-mc146818-lib.c
+++ b/drivers/rtc/rtc-mc146818-lib.c
@@ -170,9 +170,14 @@ int mc146818_set_time(struct rtc_time *time)
 	}
 
 	save_control = CMOS_READ(RTC_CONTROL);
-	CMOS_WRITE((save_control|RTC_SET), RTC_CONTROL);
+	CMOS_WRITE((save_control | RTC_SET), RTC_CONTROL);
 	save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
-	CMOS_WRITE((save_freq_select|RTC_DIV_RESET2), RTC_FREQ_SELECT);
+
+#if defined(CONFIG_CPU_SUP_AMD) || defined(CONFIG_CPU_SUP_HYGON)
+	CMOS_WRITE((save_freq_select & (~RTC_DV0)), RTC_FREQ_SELECT);
+#else
+	CMOS_WRITE((save_freq_select | RTC_DIV_RESET2), RTC_FREQ_SELECT);
+#endif
 
 #ifdef CONFIG_MACH_DECSTATION
 	CMOS_WRITE(real_yrs, RTC_DEC_YEAR);
diff --git a/include/linux/mc146818rtc.h b/include/linux/mc146818rtc.h
index 0661af17a758..590ac7849c78 100644
--- a/include/linux/mc146818rtc.h
+++ b/include/linux/mc146818rtc.h
@@ -86,6 +86,12 @@ struct cmos_rtc_board_info {
    /* 2 values for divider stage reset, others for "testing purposes only" */
 #  define RTC_DIV_RESET1	0x60
 #  define RTC_DIV_RESET2	0x70
+
+#if defined(CONFIG_CPU_SUP_AMD) || defined(CONFIG_CPU_SUP_HYGON)
+   /* DV0 = 0 selects Bank 0, DV0 = 1 selects Bank 1 on AMD/Hygon platform */
+#  define RTC_DV0		0x10
+#endif
+
   /* Periodic intr. / Square wave rate select. 0=none, 1=32.8kHz,... 15=2Hz */
 # define RTC_RATE_SELECT 	0x0F
 
-- 
2.17.1


^ permalink raw reply	[flat|nested] 3+ messages in thread

* Re: [PATCH v2] rtc: Fix the AltCentury value on AMD/Hygon platform
  2019-10-08  9:37 [PATCH v2] rtc: Fix the AltCentury value on AMD/Hygon platform Jinke Fan
@ 2019-10-08  9:44 ` Alexandre Belloni
  2019-10-09  3:18   ` Jinke Fan
  0 siblings, 1 reply; 3+ messages in thread
From: Alexandre Belloni @ 2019-10-08  9:44 UTC (permalink / raw)
  To: Jinke Fan
  Cc: a.zummo, puwen, thomas.lendacky, kim.phillips, linux-rtc, linux-kernel

On 08/10/2019 17:37:12+0800, Jinke Fan wrote:
> When using following operations:
> date -s "21190910 19:20:00"
> hwclock -w
> to change date from 2019 to 2119 for test, it will fail on Hygon
> Dhyana and AMD Zen CPUs, while the same operations run ok on Intel i7
> platform.
> 
> MC146818 driver use function mc146818_set_time() to set register
> RTC_FREQ_SELECT(RTC_REG_A)'s bit4-bit6 field which means divider stage
> reset value on Intel platform to 0x7.
> 
> While AMD/Hygon RTC_REG_A(0Ah)'s bit4 is defined as DV0 [Reference]:
> DV0 = 0 selects Bank 0, DV0 = 1 selects Bank 1. Bit5-bit6 is defined
> as reserved.
> 
> DV0 is set to 1, it will select Bank 1, which will disable AltCentury
> register(0x32) access. As UEFI pass acpi_gbl_FADT.century 0x32
> (AltCentury), the CMOS write will be failed on code:
> CMOS_WRITE(century, acpi_gbl_FADT.century).
> 
> Correct RTC_REG_A bank select bit(DV0) to 0 on AMD/Hygon CPUs, it will
> enable AltCentury(0x32) register writing and finally setup century as
> expected.
> 
> Test results on AMD/Hygon machine show that it works as expected.
> 
> Reference:
> https://www.amd.com/system/files/TechDocs/51192_Bolton_FCH_RRG.pdf
> section: 3.13 Real Time Clock (RTC)
> 
> Reported-by: kbuild test robot <lkp@intel.com>
> Signed-off-by: Jinke Fan <fanjinke@hygon.cn>
> ---
>  drivers/rtc/rtc-mc146818-lib.c | 9 +++++++--
>  include/linux/mc146818rtc.h    | 6 ++++++
>  2 files changed, 13 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/rtc/rtc-mc146818-lib.c b/drivers/rtc/rtc-mc146818-lib.c
> index 2ecd8752b088..a821dbe215d3 100644
> --- a/drivers/rtc/rtc-mc146818-lib.c
> +++ b/drivers/rtc/rtc-mc146818-lib.c
> @@ -170,9 +170,14 @@ int mc146818_set_time(struct rtc_time *time)
>  	}
>  
>  	save_control = CMOS_READ(RTC_CONTROL);
> -	CMOS_WRITE((save_control|RTC_SET), RTC_CONTROL);
> +	CMOS_WRITE((save_control | RTC_SET), RTC_CONTROL);

Unrelated change.

>  	save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
> -	CMOS_WRITE((save_freq_select|RTC_DIV_RESET2), RTC_FREQ_SELECT);
> +
> +#if defined(CONFIG_CPU_SUP_AMD) || defined(CONFIG_CPU_SUP_HYGON)
> +	CMOS_WRITE((save_freq_select & (~RTC_DV0)), RTC_FREQ_SELECT);

That does break all the other x86 platforms.

> +#else
> +	CMOS_WRITE((save_freq_select | RTC_DIV_RESET2), RTC_FREQ_SELECT);
> +#endif
>  
>  #ifdef CONFIG_MACH_DECSTATION
>  	CMOS_WRITE(real_yrs, RTC_DEC_YEAR);
> diff --git a/include/linux/mc146818rtc.h b/include/linux/mc146818rtc.h
> index 0661af17a758..590ac7849c78 100644
> --- a/include/linux/mc146818rtc.h
> +++ b/include/linux/mc146818rtc.h
> @@ -86,6 +86,12 @@ struct cmos_rtc_board_info {
>     /* 2 values for divider stage reset, others for "testing purposes only" */
>  #  define RTC_DIV_RESET1	0x60
>  #  define RTC_DIV_RESET2	0x70
> +
> +#if defined(CONFIG_CPU_SUP_AMD) || defined(CONFIG_CPU_SUP_HYGON)
> +   /* DV0 = 0 selects Bank 0, DV0 = 1 selects Bank 1 on AMD/Hygon platform */
> +#  define RTC_DV0		0x10
> +#endif
> +
>    /* Periodic intr. / Square wave rate select. 0=none, 1=32.8kHz,... 15=2Hz */
>  # define RTC_RATE_SELECT 	0x0F
>  
> -- 
> 2.17.1
> 

-- 
Alexandre Belloni, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com

^ permalink raw reply	[flat|nested] 3+ messages in thread

* Re: [PATCH v2] rtc: Fix the AltCentury value on AMD/Hygon platform
  2019-10-08  9:44 ` Alexandre Belloni
@ 2019-10-09  3:18   ` Jinke Fan
  0 siblings, 0 replies; 3+ messages in thread
From: Jinke Fan @ 2019-10-09  3:18 UTC (permalink / raw)
  To: Alexandre Belloni
  Cc: a.zummo, Wen Pu, thomas.lendacky, kim.phillips, linux-rtc, linux-kernel

On 2019/10/8 17:44, Alexandre Belloni wrote:
> On 08/10/2019 17:37:12+0800, Jinke Fan wrote:
>> When using following operations:
>>   	save_control = CMOS_READ(RTC_CONTROL);
>> -	CMOS_WRITE((save_control|RTC_SET), RTC_CONTROL);
>> +	CMOS_WRITE((save_control | RTC_SET), RTC_CONTROL);
> 
> Unrelated change.

OK, this line change will be cancelled in the patch v3.

>>   	save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
>> -	CMOS_WRITE((save_freq_select|RTC_DIV_RESET2), RTC_FREQ_SELECT);
>> +
>> +#if defined(CONFIG_CPU_SUP_AMD) || defined(CONFIG_CPU_SUP_HYGON)
>> +	CMOS_WRITE((save_freq_select & (~RTC_DV0)), RTC_FREQ_SELECT);
> 
> That does break all the other x86 platforms.

Yes, it's a mistake. In the patch v3, the modifications will be
limited to AMD/Hygon vendor id.

-- 
Best Regards,
Jinke Fan

^ permalink raw reply	[flat|nested] 3+ messages in thread

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2019-10-08  9:37 [PATCH v2] rtc: Fix the AltCentury value on AMD/Hygon platform Jinke Fan
2019-10-08  9:44 ` Alexandre Belloni
2019-10-09  3:18   ` Jinke Fan

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