From: "Maciej W. Rozycki" <macro@wdc.com>
To: Mikulas Patocka <mpatocka@redhat.com>
Cc: Ivan Kokshaysky <ink@jurassic.park.msu.ru>,
"Maciej W. Rozycki" <macro@linux-mips.org>,
Arnd Bergmann <arnd@arndb.de>,
Richard Henderson <rth@twiddle.net>,
Matt Turner <mattst88@gmail.com>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
alpha <linux-alpha@vger.kernel.org>,
linux-serial@vger.kernel.org, linux-rtc@vger.kernel.org
Subject: Re: [PATCH 1/2 v3] alpha: add a delay to inb_p, inb_w and inb_l
Date: Fri, 22 May 2020 14:37:05 +0100 (BST) [thread overview]
Message-ID: <alpine.LFD.2.21.2005221414510.21168@redsun52.ssa.fujisawa.hgst.com> (raw)
In-Reply-To: <alpine.LRH.2.02.2005201403480.24885@file01.intranet.prod.int.rdu2.redhat.com>
On Fri, 22 May 2020, Mikulas Patocka wrote:
> > Hmm, having barriers *afterwards* across all the MMIO accessors, even
> > ones that do not have such a requirement according to memory-barriers.txt,
> > does hurt performance unnecessarily however. What I think has to be done
> > is adding barriers beforehand, and then only add barriers afterwards where
> > necessary. Commit 92d7223a74 did a part of that, but did not consistently
> > update all the remaining accessors.
> >
> > So I don't think reverting 92d7223a74 permanently is the right way to go,
> > however it certainly makes sense to do that temporarily to get rid of the
> > fatal regression, sort all the corner cases and then apply the resulting
> > replacement fix.
>
> See Documentation/memory-barriers.txt, the section "KERNEL I/O BARRIER
> EFFECTS"
>
> According to the specification, there must be a barrier before a write to
> the MMIO space (paragraph 3) and after a read from MMIO space (parahraph
> 4) - if this causes unnecessary slowdown, the driver should use
> readX_relaxed or writeX_relaxed functions - the *_relaxed functions are
> ordered with each other (see the paragraph "(*) readX_relaxed(),
> writeX_relaxed()"), but they are not ordered with respect to memory
> access.
The specification doesn't require a barrier *after* a write however,
which is what I have been concerned about as it may cost hundreds of
cycles wasted. I'm not concerned about a barrier after a read (and one
beforehand is of course also required).
> The commit 92d7223a74 fixes that requirement (although there is no real
> driver that was fixed by this), so I don't think it should be reverted.
> The proper fix should be to add delays to the serial port and readltime
> clock (or perhaps to all IO-port accesses).
Adding artificial delays will only paper over the real problem I'm
afraid.
> > I think ultimately we do want the barriers beforehand, just like the
> > MIPS port has (and survives) in arch/mips/include/asm/io.h. Observe
>
> If the MIPS port doesn't have MMIO barrier after read[bwl], then it is
> violating the specification. Perhaps there is no existing driver that is
> hurt by this violation, so this violation survived.
It does have a barrier, see:
/* prevent prefetching of coherent DMA data prematurely */ \
if (!relax) \
rmb(); \
In the light of #5 however:
5. A readX() by a CPU thread from the peripheral will complete before
any subsequent delay() loop can begin execution on the same thread.
I think it may have to be replaced with a completion barrier however, and
that will be tricky because you cannot just issue a second read to the
resource accessed after the `rmb' to make the first read complete, as a
MMIO read may have side effects (e.g. clearing an interrupt request). So
the read would have to happen to a different location.
Some architectures have a hardware completion barrier instruction, such
as the modern MIPS ISA, which makes life sweet and easy (as much as life
can be sweet and easy with a weakly ordered bus model) as no dummy read is
then required, but surely not all do (including older MIPS ISA revisions).
Maciej
next prev parent reply other threads:[~2020-05-22 13:37 UTC|newest]
Thread overview: 45+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-06 11:21 [PATCH 1/2] alpha: add a delay between RTC port write and read Mikulas Patocka
2020-05-06 14:20 ` Arnd Bergmann
2020-05-06 17:12 ` [PATCH 1/2 v2] alpha: add a delay to inb_p, inb_w and inb_l Mikulas Patocka
2020-05-07 8:06 ` [PATCH 1/2 v3] " Mikulas Patocka
2020-05-07 8:20 ` Greg Kroah-Hartman
2020-05-07 10:53 ` Mikulas Patocka
2020-05-07 13:30 ` Arnd Bergmann
2020-05-07 14:09 ` Mikulas Patocka
2020-05-07 15:08 ` Arnd Bergmann
2020-05-07 15:45 ` Mikulas Patocka
2020-05-07 15:46 ` [PATCH v4] alpha: add a barrier after outb, outw and outl Mikulas Patocka
2020-05-07 19:12 ` Arnd Bergmann
2020-05-10 1:27 ` Maciej W. Rozycki
2020-05-10 1:25 ` [PATCH 1/2 v3] alpha: add a delay to inb_p, inb_w and inb_l Maciej W. Rozycki
2020-05-10 18:50 ` Mikulas Patocka
2020-05-11 14:58 ` Maciej W. Rozycki
2020-05-12 19:35 ` Mikulas Patocka
2020-05-13 14:41 ` Ivan Kokshaysky
2020-05-13 16:13 ` Greg Kroah-Hartman
2020-05-13 17:17 ` Maciej W. Rozycki
2020-05-22 13:03 ` Mikulas Patocka
2020-05-22 13:37 ` Maciej W. Rozycki [this message]
2020-05-22 13:26 ` Mikulas Patocka
2020-05-22 20:00 ` Mikulas Patocka
2020-05-23 10:26 ` [PATCH v4] alpha: fix memory barriers so that they conform to the specification Mikulas Patocka
2020-05-23 15:10 ` Ivan Kokshaysky
2020-05-23 15:34 ` Mikulas Patocka
2020-05-23 15:37 ` [PATCH v5] " Mikulas Patocka
2020-05-24 14:54 ` Maciej W. Rozycki
2020-05-25 13:56 ` Mikulas Patocka
2020-05-25 14:07 ` Arnd Bergmann
2020-05-25 14:45 ` Maciej W. Rozycki
2020-05-25 15:53 ` [PATCH v6] " Mikulas Patocka
2020-05-26 14:47 ` [PATCH v7] " Mikulas Patocka
2020-05-27 0:18 ` Maciej W. Rozycki
2020-06-08 6:58 ` Mikulas Patocka
2020-06-08 23:49 ` Matt Turner
2020-05-25 15:54 ` [PATCH v5] " Mikulas Patocka
2020-05-25 16:39 ` Maciej W. Rozycki
2020-05-26 14:48 ` Mikulas Patocka
2020-05-27 0:23 ` Maciej W. Rozycki
2020-05-23 16:44 ` [PATCH v4] " Maciej W. Rozycki
2020-05-23 17:09 ` Mikulas Patocka
2020-05-23 19:27 ` Maciej W. Rozycki
2020-05-23 20:11 ` Mikulas Patocka
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