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Wed, 23 Oct 2019 07:41:40 +0000 (GMT) From: Marek Szyprowski To: linux-clk@vger.kernel.org, linux-samsung-soc@vger.kernel.org Cc: Marek Szyprowski , Sylwester Nawrocki , Chanwoo Choi , Krzysztof Kozlowski , Bartlomiej Zolnierkiewicz , Marian Mihailescu Subject: [PATCH] clk: samsung: exynos542x: Move G3D subsystem clocks to its sub-CMU Date: Wed, 23 Oct 2019 09:41:18 +0200 Message-Id: <20191023074118.3012-1-m.szyprowski@samsung.com> X-Mailer: git-send-email 2.17.1 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrPIsWRmVeSWpSXmKPExsWy7djPc7qmLBtiDeYfFbPYOGM9q8X1L89Z Lc6f38Bu8bHnHqvFjPP7mCzWHrnLbrF+2k9Wi/anL5kdODx2zrrL7rFpVSebR9+WVYwenzfJ BbBEcdmkpOZklqUW6dslcGUsPXyMteCIVMWlq7PYGhjPiHUxcnJICJhI/O+Yx9jFyMUhJLCC UeLk3HNMEM4XRonNx3eyQTifGSUa7j9mh2lp29LCDGILCSxnlLg1RwKu48qjmSwgCTYBQ4mu t11sILaIgIPE50+vwXYwC/QzSfT1XQXrFhYIlVhwdB9YEYuAqsSbrXeBijg4eAVsJGatYoJY Ji+xesMBZpBeCYHbbBJnp35ihUi4SHw58JENwhaWeHV8C9R1MhL/d85ngmhoZpR4eG4tO4TT wyhxuWkGI0SVtcTh4xdZQbYxC2hKrN+lDxF2lDh75D0LSFhCgE/ixltBkDAzkDlp23RmiDCv REebEES1msSs4+vg1h68cIkZwvaQeH7jJiskgGIlPs9fxzKBUW4Wwq4FjIyrGMVTS4tz01OL jfJSy/WKE3OLS/PS9ZLzczcxApPB6X/Hv+xg3PUn6RCjAAejEg+vw/t1sUKsiWXFlbmHGCU4 mJVEeO8YrI0V4k1JrKxKLcqPLyrNSS0+xCjNwaIkzlvN8CBaSCA9sSQ1OzW1ILUIJsvEwSnV wCjfPf3CBObgNr8PDJZNy3zUstd9yOO5WH4j1E7xTNeLpwnufg8Npaoca16+L/554Zq/7JSS 71/PV6rxMX7S/fO+3GTJeYtyd3XtT6Y6v54z1965bzrtkzzXdEVZ9obwlgXtn6dqe5z/96Tx vccd/tvuG4KTEgUdD1zIrUlW75ho/dstWf5kuxJLcUaioRZzUXEiAIG/z+UCAwAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrKLMWRmVeSWpSXmKPExsVy+t/xe7omLBtiDeYcMbbYOGM9q8X1L89Z Lc6f38Bu8bHnHqvFjPP7mCzWHrnLbrF+2k9Wi/anL5kdODx2zrrL7rFpVSebR9+WVYwenzfJ BbBE6dkU5ZeWpCpk5BeX2CpFG1oY6RlaWugZmVjqGRqbx1oZmSrp29mkpOZklqUW6dsl6GUs PXyMteCIVMWlq7PYGhjPiHUxcnJICJhItG1pYe5i5OIQEljKKNH/6hQjREJG4uS0BlYIW1ji z7UuNoiiT4wShw6uYAFJsAkYSnS9BUlwcogIOEk8WPeGHaSIWWAyk8T2pqVgRcICwRLXH79m BrFZBFQl3my9C7SBg4NXwEZi1iomiAXyEqs3HGCewMizgJFhFaNIamlxbnpusaFecWJucWle ul5yfu4mRmAQbjv2c/MOxksbgw8xCnAwKvHwzvi4LlaINbGsuDL3EKMEB7OSCO8dg7WxQrwp iZVVqUX58UWlOanFhxhNgXZPZJYSTc4HRkheSbyhqaG5haWhubG5sZmFkjhvh8DBGCGB9MSS 1OzU1ILUIpg+Jg5OqQZG/l1Hr6QpSyQblLcvmdXNu0dp7fJVIS/2L77i9i7w2xP1aTMreOyO Fis2n0qxs1jGZHIzjm21hI+J3JJvy0JcYssP3V4lvK1v90J553lZPM137K5OXHv7Q6jinYSy I1q26btXS32RSTxhOuPNo6igw9Gn7/4vfH4q+ddHsZAWhlan3wx6BeJPlFiKMxINtZiLihMB Adc7AlgCAAA= X-CMS-MailID: 20191023074140eucas1p2c236bde672f33d4fe32ed61545515cc3 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-RootMTR: 20191023074140eucas1p2c236bde672f33d4fe32ed61545515cc3 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20191023074140eucas1p2c236bde672f33d4fe32ed61545515cc3 References: Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org G3D clocks require special handling of their parent bus clock during power domain on/off sequences. Those clocks were not initially added to the sub-CMU handler, because that time there was no open-source driver for the G3D (MALI Panfrost) hardware module and it was not possible to test it. This patch fixes this issue. Parent clock for G3D hardware block is now properly preserved during G3D power domain on/off sequence. This restores proper MALI Panfrost performance broken by commit 8686764fc071 ("ARM: dts: exynos: Add G3D power domain to Exynos542x"). Reported-by: Marian Mihailescu Fixes: b06a532bf1fa ("clk: samsung: Add Exynos5 sub-CMU clock driver") Signed-off-by: Marek Szyprowski Tested-by: Marian Mihailescu --- drivers/clk/samsung/clk-exynos5420.c | 21 +++++++++++++++++++-- 1 file changed, 19 insertions(+), 2 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c index 7670cc596c74..dfa862d55246 100644 --- a/drivers/clk/samsung/clk-exynos5420.c +++ b/drivers/clk/samsung/clk-exynos5420.c @@ -1172,8 +1172,6 @@ static const struct samsung_gate_clock exynos5x_gate_clks[] __initconst = { GATE(CLK_SCLK_ISP_SENSOR2, "sclk_isp_sensor2", "dout_isp_sensor2", GATE_TOP_SCLK_ISP, 12, CLK_SET_RATE_PARENT, 0), - GATE(CLK_G3D, "g3d", "mout_user_aclk_g3d", GATE_IP_G3D, 9, 0, 0), - /* CDREX */ GATE(CLK_CLKM_PHY0, "clkm_phy0", "dout_sclk_cdrex", GATE_BUS_CDREX0, 0, 0, 0), @@ -1248,6 +1246,15 @@ static struct exynos5_subcmu_reg_dump exynos5x_gsc_suspend_regs[] = { { DIV2_RATIO0, 0, 0x30 }, /* DIV dout_gscl_blk_300 */ }; +static const struct samsung_gate_clock exynos5x_g3d_gate_clks[] __initconst = { + GATE(CLK_G3D, "g3d", "mout_user_aclk_g3d", GATE_IP_G3D, 9, 0, 0), +}; + +static struct exynos5_subcmu_reg_dump exynos5x_g3d_suspend_regs[] = { + { GATE_IP_G3D, 0x3ff, 0x3ff }, /* G3D gates */ + { SRC_TOP5, 0, BIT(16) }, /* MUX mout_user_aclk_g3d */ +}; + static const struct samsung_div_clock exynos5x_mfc_div_clks[] __initconst = { DIV(0, "dout_mfc_blk", "mout_user_aclk333", DIV4_RATIO, 0, 2), }; @@ -1320,6 +1327,14 @@ static const struct exynos5_subcmu_info exynos5x_gsc_subcmu = { .pd_name = "GSC", }; +static const struct exynos5_subcmu_info exynos5x_g3d_subcmu = { + .gate_clks = exynos5x_g3d_gate_clks, + .nr_gate_clks = ARRAY_SIZE(exynos5x_g3d_gate_clks), + .suspend_regs = exynos5x_g3d_suspend_regs, + .nr_suspend_regs = ARRAY_SIZE(exynos5x_g3d_suspend_regs), + .pd_name = "G3D", +}; + static const struct exynos5_subcmu_info exynos5x_mfc_subcmu = { .div_clks = exynos5x_mfc_div_clks, .nr_div_clks = ARRAY_SIZE(exynos5x_mfc_div_clks), @@ -1351,6 +1366,7 @@ static const struct exynos5_subcmu_info exynos5800_mau_subcmu = { static const struct exynos5_subcmu_info *exynos5x_subcmus[] = { &exynos5x_disp_subcmu, &exynos5x_gsc_subcmu, + &exynos5x_g3d_subcmu, &exynos5x_mfc_subcmu, &exynos5x_mscl_subcmu, }; @@ -1358,6 +1374,7 @@ static const struct exynos5_subcmu_info *exynos5x_subcmus[] = { static const struct exynos5_subcmu_info *exynos5800_subcmus[] = { &exynos5x_disp_subcmu, &exynos5x_gsc_subcmu, + &exynos5x_g3d_subcmu, &exynos5x_mfc_subcmu, &exynos5x_mscl_subcmu, &exynos5800_mau_subcmu, -- 2.17.1