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From: Stephen Boyd <sboyd@kernel.org>
To: Marek Szyprowski <m.szyprowski@samsung.com>,
	Sylwester Nawrocki <s.nawrocki@samsung.com>,
	linux-clk@vger.kernel.org
Cc: linux-samsung-soc@vger.kernel.org,
	Sylwester Nawrocki <snawrocki@kernel.org>,
	Chanwoo Choi <cw00.choi@samsung.com>,
	Krzysztof Kozlowski <krzk@kernel.org>,
	Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>,
	Marian Mihailescu <mihailescu2m@gmail.com>
Subject: Re: [PATCH v2] clk: samsung: exynos5420: Keep top G3D clocks enabled
Date: Mon, 23 Dec 2019 23:53:06 -0800	[thread overview]
Message-ID: <20191224075307.6BBAA2071A@mail.kernel.org> (raw)
In-Reply-To: <f4f23b53-4eae-de3e-c8b2-099909522ce2@samsung.com>

Quoting Sylwester Nawrocki (2019-12-19 02:05:04)
> On 12/16/19 14:14, Marek Szyprowski wrote:
> > In Exynos542x/5800 SoCs, the G3D leaf clocks are located in the G3D power
> > domain. This is similar to the other hardware modules and their power
> > domains. However there is one thing specific to G3D clocks hierarchy.
> > Unlike other hardware modules, the G3D clocks hierarchy doesn't have any
> > gate clock between the TOP part of the hierarchy and the part located in
> > the power domain and some SoC internal busses are sourced directly from
> > the TOP muxes. The consequence of this design if the fact that the TOP
> > part of the hierarchy has to be enabled permanently to ensure proper
> > operation of the SoC power related components (G3D power domain and
> > Exynos Power Management Unit for system suspend/resume).
> > 
> > This patch adds an explicit call to clk_prepare_enable() on the last MUX
> > in the TOP part of G3D clock hierarchy to keep it enabled permanently to
> > ensure that the internal busses get their clock regardless of the main
> > G3D clock enablement status.
> 
> > ---
> > diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
> > index 3a991ca1ee36..c9e5a1fb6653 100644
> > --- a/drivers/clk/samsung/clk-exynos5420.c
> > +++ b/drivers/clk/samsung/clk-exynos5420.c
> 
> > @@ -1646,6 +1647,13 @@ static void __init exynos5x_clk_init(struct device_node *np,
> >                                    exynos5x_subcmus);
> >       }
> >  
> > +     /*
> > +      * Keep top part of G3D clock path enabled permanently to ensure
> > +      * that the internal busses get their clock regardless of the
> > +      * main G3D clock enablement status.
> > +      */
> > +     clk_prepare_enable(__clk_lookup("mout_sw_aclk_g3d"));
> > +
> >       samsung_clk_of_add_provider(np, ctx);
> >  }
> 
> It's a bit unfortunate we don't store that clock in the driver internally,
> which would let us avoid the __clk_lookup() call. I can't come up with any
> simple alternative though so let's apply it for now.

Yes it would be better to not use __clk_lookup(). I'll apply it for now
but please avoid it somehow in a future patch.


  reply	other threads:[~2019-12-24  7:53 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
     [not found] <CGME20191216131423eucas1p2162d6bf0a870357be9f0ab308641015b@eucas1p2.samsung.com>
2019-12-16 13:14 ` [PATCH v2] clk: samsung: exynos5420: Keep top G3D clocks enabled Marek Szyprowski
2019-12-18  9:44   ` Krzysztof Kozlowski
2019-12-19  2:26   ` Chanwoo Choi
2019-12-19 10:05   ` Sylwester Nawrocki
2019-12-24  7:53     ` Stephen Boyd [this message]
2019-12-24  7:53   ` Stephen Boyd

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