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From: Krzysztof Kozlowski <krzk@kernel.org>
To: Lukasz Luba <lukasz.luba@arm.com>,
	Krzysztof Kozlowski <krzk@kernel.org>,
	Kukjin Kim <kgene@kernel.org>,
	linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org,
	linux-kernel@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org
Subject: [PATCH 2/3] memory: samsung: exynos5422-dmc: remove unused exynos5_dmc members
Date: Sat, 22 Aug 2020 18:32:17 +0200	[thread overview]
Message-ID: <20200822163218.21857-2-krzk@kernel.org> (raw)
In-Reply-To: <20200822163218.21857-1-krzk@kernel.org>

The struct exynos5_dmc members bypass_rate, mx_mspll_ccore_phy,
mout_mx_mspll_ccore_phy and opp_bypass are not actually used.

Apparently there was a plan to store the OPP for the bypass mode in
opp_bypass member, but drivers fails to do it and instead always sets
target voltage during bypass mode.

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
---
 drivers/memory/samsung/exynos5422-dmc.c | 9 ---------
 1 file changed, 9 deletions(-)

diff --git a/drivers/memory/samsung/exynos5422-dmc.c b/drivers/memory/samsung/exynos5422-dmc.c
index 31864ce59b25..df02afa8aa90 100644
--- a/drivers/memory/samsung/exynos5422-dmc.c
+++ b/drivers/memory/samsung/exynos5422-dmc.c
@@ -123,9 +123,7 @@ struct exynos5_dmc {
 	struct mutex lock;
 	unsigned long curr_rate;
 	unsigned long curr_volt;
-	unsigned long bypass_rate;
 	struct dmc_opp_table *opp;
-	struct dmc_opp_table opp_bypass;
 	int opp_count;
 	u32 timings_arr_size;
 	u32 *timing_row;
@@ -143,8 +141,6 @@ struct exynos5_dmc {
 	struct clk *mout_bpll;
 	struct clk *mout_mclk_cdrex;
 	struct clk *mout_mx_mspll_ccore;
-	struct clk *mx_mspll_ccore_phy;
-	struct clk *mout_mx_mspll_ccore_phy;
 	struct devfreq_event_dev **counter;
 	int num_counters;
 	u64 last_overflow_ts[2];
@@ -455,9 +451,6 @@ static int exynos5_dmc_align_bypass_voltage(struct exynos5_dmc *dmc,
 					    unsigned long target_volt)
 {
 	int ret = 0;
-	unsigned long bypass_volt = dmc->opp_bypass.volt_uv;
-
-	target_volt = max(bypass_volt, target_volt);
 
 	if (dmc->curr_volt >= target_volt)
 		return 0;
@@ -1268,8 +1261,6 @@ static int exynos5_dmc_init_clks(struct exynos5_dmc *dmc)
 
 	clk_set_parent(dmc->mout_mx_mspll_ccore, dmc->mout_spll);
 
-	dmc->bypass_rate = clk_get_rate(dmc->mout_mx_mspll_ccore);
-
 	clk_prepare_enable(dmc->fout_bpll);
 	clk_prepare_enable(dmc->mout_bpll);
 
-- 
2.17.1


  reply	other threads:[~2020-08-22 16:32 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-08-22 16:32 [PATCH 1/3] memory: samsung: exynos5422-dmc: rename timing register fields variables Krzysztof Kozlowski
2020-08-22 16:32 ` Krzysztof Kozlowski [this message]
2020-08-24 11:43   ` [PATCH 2/3] memory: samsung: exynos5422-dmc: remove unused exynos5_dmc members Lukasz Luba
2020-08-24 12:01     ` Krzysztof Kozlowski
2020-08-22 16:32 ` [PATCH 3/3] memory: samsung: exynos5422-dmc: add missing and fix kerneldoc Krzysztof Kozlowski
2020-08-24 11:01   ` Lukasz Luba
2020-08-24 10:59 ` [PATCH 1/3] memory: samsung: exynos5422-dmc: rename timing register fields variables Lukasz Luba

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