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* [PATCH v3 0/7] Add minimal support for Exynos850 SoC
@ 2021-08-11 11:48 Sam Protsenko
  2021-08-11 11:48 ` [PATCH v3 1/7] dt-bindings: pinctrl: samsung: Add Exynos850 doc Sam Protsenko
                   ` (7 more replies)
  0 siblings, 8 replies; 17+ messages in thread
From: Sam Protsenko @ 2021-08-11 11:48 UTC (permalink / raw)
  To: Krzysztof Kozlowski, Sylwester Nawrocki, Paweł Chmiel, Chanwoo Choi
  Cc: Linus Walleij, Tomasz Figa, Marc Zyngier, Rob Herring,
	Stephen Boyd, Michael Turquette, Jiri Slaby, Greg Kroah-Hartman,
	Charles Keepax, Ryu Euiyoul, Tom Gall, Sumit Semwal, John Stultz,
	Amit Pundir, devicetree, linux-arm-kernel, linux-gpio,
	linux-kernel, linux-samsung-soc, linux-serial

This patch series adds initial platform support for Samsung Exynos850
SoC [1]. With this patchset it's possible to run the kernel with BusyBox
rootfs as a RAM disk. More advanced platform support (like MMC driver
additions) will be added later. The idea is to keep the first submission
minimal to ease the review, and then build up on top of that.

[1] https://www.samsung.com/semiconductor/minisite/exynos/products/mobileprocessor/exynos-850/

Changes in v3:
 * Removed the stub clock driver; uart clock is modeled as generic fixed
   clock in dts for now
 * See also changes in each particular patch

Changes in v2:
 * Rebased on top of current linux-mainline
 * Removed patch ("pinctrl: samsung: Fix pinctrl bank pin count"); it
   was sent separately, as it's an independent fix
 * Made the patch ("dt-bindings: pinctrl: samsung: Add Exynos850 doc")
   to be the first in series
 * Removed patch ("MAINTAINERS: Changes in v2"); will add that later,
   when proper clock driver is implemented
 * Removed patch ("dt-bindings: clock: Add bindings for Exynos850 clock
   controller"); will add clock bindings later, when proper clock driver
   is implemented
 * Removed patch ("dt-bindings: interrupt-controller: Add IRQ constants
   for Exynos850"), and used hard-coded IRQ numbers in dts instead
 * See also changes in each particular patch

Sam Protsenko (7):
  dt-bindings: pinctrl: samsung: Add Exynos850 doc
  pinctrl: samsung: Add Exynos850 SoC specific data
  dt-bindings: serial: samsung: Add Exynos850 doc
  tty: serial: samsung: Init USI to keep clocks running
  tty: serial: samsung: Fix driver data macros style
  tty: serial: samsung: Add Exynos850 SoC data
  arm64: dts: exynos: Add Exynos850 SoC support

 .../bindings/pinctrl/samsung-pinctrl.txt      |   1 +
 .../bindings/serial/samsung_uart.yaml         |   1 +
 .../boot/dts/exynos/exynos850-pinctrl.dtsi    | 748 ++++++++++++++++++
 arch/arm64/boot/dts/exynos/exynos850.dtsi     | 261 ++++++
 .../pinctrl/samsung/pinctrl-exynos-arm64.c    | 116 +++
 drivers/pinctrl/samsung/pinctrl-exynos.h      |  29 +
 drivers/pinctrl/samsung/pinctrl-samsung.c     |   2 +
 drivers/pinctrl/samsung/pinctrl-samsung.h     |   1 +
 drivers/tty/serial/samsung_tty.c              |  49 +-
 include/linux/serial_s3c.h                    |   9 +
 10 files changed, 1214 insertions(+), 3 deletions(-)
 create mode 100644 arch/arm64/boot/dts/exynos/exynos850-pinctrl.dtsi
 create mode 100644 arch/arm64/boot/dts/exynos/exynos850.dtsi

-- 
2.30.2


^ permalink raw reply	[flat|nested] 17+ messages in thread

* [PATCH v3 1/7] dt-bindings: pinctrl: samsung: Add Exynos850 doc
  2021-08-11 11:48 [PATCH v3 0/7] Add minimal support for Exynos850 SoC Sam Protsenko
@ 2021-08-11 11:48 ` Sam Protsenko
  2021-08-11 11:48 ` [PATCH v3 2/7] pinctrl: samsung: Add Exynos850 SoC specific data Sam Protsenko
                   ` (6 subsequent siblings)
  7 siblings, 0 replies; 17+ messages in thread
From: Sam Protsenko @ 2021-08-11 11:48 UTC (permalink / raw)
  To: Krzysztof Kozlowski, Sylwester Nawrocki, Paweł Chmiel, Chanwoo Choi
  Cc: Linus Walleij, Tomasz Figa, Marc Zyngier, Rob Herring,
	Stephen Boyd, Michael Turquette, Jiri Slaby, Greg Kroah-Hartman,
	Charles Keepax, Ryu Euiyoul, Tom Gall, Sumit Semwal, John Stultz,
	Amit Pundir, devicetree, linux-arm-kernel, linux-gpio,
	linux-kernel, linux-samsung-soc, linux-serial

Document compatible string for Exynos850 SoC. Nothing else is changed,
as Exynos850 SoC uses already existing samsung pinctrl driver.

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
---
Changes in v3:
  - None

Changes in v2:
  - This patch was made the first in the series

 Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
index 38a1416fd2cd..e7a1b1880375 100644
--- a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
@@ -22,6 +22,7 @@ Required Properties:
   - "samsung,exynos5420-pinctrl": for Exynos5420 compatible pin-controller.
   - "samsung,exynos5433-pinctrl": for Exynos5433 compatible pin-controller.
   - "samsung,exynos7-pinctrl": for Exynos7 compatible pin-controller.
+  - "samsung,exynos850-pinctrl": for Exynos850 compatible pin-controller.
 
 - reg: Base address of the pin controller hardware module and length of
   the address space it occupies.
-- 
2.30.2


^ permalink raw reply	[flat|nested] 17+ messages in thread

* [PATCH v3 2/7] pinctrl: samsung: Add Exynos850 SoC specific data
  2021-08-11 11:48 [PATCH v3 0/7] Add minimal support for Exynos850 SoC Sam Protsenko
  2021-08-11 11:48 ` [PATCH v3 1/7] dt-bindings: pinctrl: samsung: Add Exynos850 doc Sam Protsenko
@ 2021-08-11 11:48 ` Sam Protsenko
  2021-08-11 11:48 ` [PATCH v3 3/7] dt-bindings: serial: samsung: Add Exynos850 doc Sam Protsenko
                   ` (5 subsequent siblings)
  7 siblings, 0 replies; 17+ messages in thread
From: Sam Protsenko @ 2021-08-11 11:48 UTC (permalink / raw)
  To: Krzysztof Kozlowski, Sylwester Nawrocki, Paweł Chmiel, Chanwoo Choi
  Cc: Linus Walleij, Tomasz Figa, Marc Zyngier, Rob Herring,
	Stephen Boyd, Michael Turquette, Jiri Slaby, Greg Kroah-Hartman,
	Charles Keepax, Ryu Euiyoul, Tom Gall, Sumit Semwal, John Stultz,
	Amit Pundir, devicetree, linux-arm-kernel, linux-gpio,
	linux-kernel, linux-samsung-soc, linux-serial

Add Samsung Exynos850 SoC specific data to enable pinctrl support for
all platforms based on Exynos850.

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
---
Changes in v3:
  - Added const qualifier to exynos850_bank_type_* structs
  - Added const and __initconst qualifiers to exynos850_pin_banks*[]
    arrays
  - Renamed EXYNOS9_* mactos to EXYNOS850_*

Changes in v2:
  - Removed .suspend/.resume callbacks, as retention registers are not
    implemented yet for Exynos850
  - Removed .eint_gpio_init for AUD domain, as there are no external
    interrupts available for that domain

 .../pinctrl/samsung/pinctrl-exynos-arm64.c    | 116 ++++++++++++++++++
 drivers/pinctrl/samsung/pinctrl-exynos.h      |  29 +++++
 drivers/pinctrl/samsung/pinctrl-samsung.c     |   2 +
 drivers/pinctrl/samsung/pinctrl-samsung.h     |   1 +
 4 files changed, 148 insertions(+)

diff --git a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c
index b6e56422a700..616c7840927f 100644
--- a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c
+++ b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c
@@ -40,6 +40,24 @@ static const struct samsung_pin_bank_type exynos5433_bank_type_alive = {
 	.reg_offset = { 0x00, 0x04, 0x08, 0x0c, },
 };
 
+/*
+ * Bank type for non-alive type. Bit fields:
+ * CON: 4, DAT: 1, PUD: 4, DRV: 4, CONPDN: 2, PUDPDN: 4
+ */
+static const struct samsung_pin_bank_type exynos850_bank_type_off  = {
+	.fld_width = { 4, 1, 4, 4, 2, 4, },
+	.reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, },
+};
+
+/*
+ * Bank type for alive type. Bit fields:
+ * CON: 4, DAT: 1, PUD: 4, DRV: 4
+ */
+static const struct samsung_pin_bank_type exynos850_bank_type_alive = {
+	.fld_width = { 4, 1, 4, 4, },
+	.reg_offset = { 0x00, 0x04, 0x08, 0x0c, },
+};
+
 /* Pad retention control code for accessing PMU regmap */
 static atomic_t exynos_shared_retention_refcnt;
 
@@ -422,3 +440,101 @@ const struct samsung_pinctrl_of_match_data exynos7_of_data __initconst = {
 	.ctrl		= exynos7_pin_ctrl,
 	.num_ctrl	= ARRAY_SIZE(exynos7_pin_ctrl),
 };
+
+/* pin banks of exynos850 pin-controller 0 (ALIVE) */
+static const struct samsung_pin_bank_data exynos850_pin_banks0[] __initconst = {
+	/* Must start with EINTG banks, ordered by EINT group number. */
+	EXYNOS850_PIN_BANK_EINTW(8, 0x000, "gpa0", 0x00),
+	EXYNOS850_PIN_BANK_EINTW(8, 0x020, "gpa1", 0x04),
+	EXYNOS850_PIN_BANK_EINTW(8, 0x040, "gpa2", 0x08),
+	EXYNOS850_PIN_BANK_EINTW(8, 0x060, "gpa3", 0x0c),
+	EXYNOS850_PIN_BANK_EINTW(4, 0x080, "gpa4", 0x10),
+	EXYNOS850_PIN_BANK_EINTN(3, 0x0A0, "gpq0"),
+};
+
+/* pin banks of exynos850 pin-controller 1 (CMGP) */
+static const struct samsung_pin_bank_data exynos850_pin_banks1[] __initconst = {
+	/* Must start with EINTG banks, ordered by EINT group number. */
+	EXYNOS850_PIN_BANK_EINTW(1, 0x000, "gpm0", 0x00),
+	EXYNOS850_PIN_BANK_EINTW(1, 0x020, "gpm1", 0x04),
+	EXYNOS850_PIN_BANK_EINTW(1, 0x040, "gpm2", 0x08),
+	EXYNOS850_PIN_BANK_EINTW(1, 0x060, "gpm3", 0x0C),
+	EXYNOS850_PIN_BANK_EINTW(1, 0x080, "gpm4", 0x10),
+	EXYNOS850_PIN_BANK_EINTW(1, 0x0A0, "gpm5", 0x14),
+	EXYNOS850_PIN_BANK_EINTW(1, 0x0C0, "gpm6", 0x18),
+	EXYNOS850_PIN_BANK_EINTW(1, 0x0E0, "gpm7", 0x1C),
+};
+
+/* pin banks of exynos850 pin-controller 2 (AUD) */
+static const struct samsung_pin_bank_data exynos850_pin_banks2[] __initconst = {
+	/* Must start with EINTG banks, ordered by EINT group number. */
+	EXYNOS850_PIN_BANK_EINTG(5, 0x000, "gpb0", 0x00),
+	EXYNOS850_PIN_BANK_EINTG(5, 0x020, "gpb1", 0x04),
+};
+
+/* pin banks of exynos850 pin-controller 3 (HSI) */
+static const struct samsung_pin_bank_data exynos850_pin_banks3[] __initconst = {
+	/* Must start with EINTG banks, ordered by EINT group number. */
+	EXYNOS850_PIN_BANK_EINTG(6, 0x000, "gpf2", 0x00),
+};
+
+/* pin banks of exynos850 pin-controller 4 (CORE) */
+static const struct samsung_pin_bank_data exynos850_pin_banks4[] __initconst = {
+	/* Must start with EINTG banks, ordered by EINT group number. */
+	EXYNOS850_PIN_BANK_EINTG(4, 0x000, "gpf0", 0x00),
+	EXYNOS850_PIN_BANK_EINTG(8, 0x020, "gpf1", 0x04),
+};
+
+/* pin banks of exynos850 pin-controller 5 (PERI) */
+static const struct samsung_pin_bank_data exynos850_pin_banks5[] __initconst = {
+	/* Must start with EINTG banks, ordered by EINT group number. */
+	EXYNOS850_PIN_BANK_EINTG(2, 0x000, "gpg0", 0x00),
+	EXYNOS850_PIN_BANK_EINTG(6, 0x020, "gpp0", 0x04),
+	EXYNOS850_PIN_BANK_EINTG(4, 0x040, "gpp1", 0x08),
+	EXYNOS850_PIN_BANK_EINTG(4, 0x060, "gpp2", 0x0C),
+	EXYNOS850_PIN_BANK_EINTG(8, 0x080, "gpg1", 0x10),
+	EXYNOS850_PIN_BANK_EINTG(8, 0x0A0, "gpg2", 0x14),
+	EXYNOS850_PIN_BANK_EINTG(1, 0x0C0, "gpg3", 0x18),
+	EXYNOS850_PIN_BANK_EINTG(3, 0x0E0, "gpc0", 0x1C),
+	EXYNOS850_PIN_BANK_EINTG(6, 0x100, "gpc1", 0x20),
+};
+
+static const struct samsung_pin_ctrl exynos850_pin_ctrl[] __initconst = {
+	{
+		/* pin-controller instance 0 ALIVE data */
+		.pin_banks	= exynos850_pin_banks0,
+		.nr_banks	= ARRAY_SIZE(exynos850_pin_banks0),
+		.eint_gpio_init = exynos_eint_gpio_init,
+		.eint_wkup_init = exynos_eint_wkup_init,
+	}, {
+		/* pin-controller instance 1 CMGP data */
+		.pin_banks	= exynos850_pin_banks1,
+		.nr_banks	= ARRAY_SIZE(exynos850_pin_banks1),
+		.eint_gpio_init = exynos_eint_gpio_init,
+		.eint_wkup_init = exynos_eint_wkup_init,
+	}, {
+		/* pin-controller instance 2 AUD data */
+		.pin_banks	= exynos850_pin_banks2,
+		.nr_banks	= ARRAY_SIZE(exynos850_pin_banks2),
+	}, {
+		/* pin-controller instance 3 HSI data */
+		.pin_banks	= exynos850_pin_banks3,
+		.nr_banks	= ARRAY_SIZE(exynos850_pin_banks3),
+		.eint_gpio_init = exynos_eint_gpio_init,
+	}, {
+		/* pin-controller instance 4 CORE data */
+		.pin_banks	= exynos850_pin_banks4,
+		.nr_banks	= ARRAY_SIZE(exynos850_pin_banks4),
+		.eint_gpio_init = exynos_eint_gpio_init,
+	}, {
+		/* pin-controller instance 5 PERI data */
+		.pin_banks	= exynos850_pin_banks5,
+		.nr_banks	= ARRAY_SIZE(exynos850_pin_banks5),
+		.eint_gpio_init = exynos_eint_gpio_init,
+	},
+};
+
+const struct samsung_pinctrl_of_match_data exynos850_of_data __initconst = {
+	.ctrl		= exynos850_pin_ctrl,
+	.num_ctrl	= ARRAY_SIZE(exynos850_pin_ctrl),
+};
diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.h b/drivers/pinctrl/samsung/pinctrl-exynos.h
index da1ec13697e7..bfad1ced8017 100644
--- a/drivers/pinctrl/samsung/pinctrl-exynos.h
+++ b/drivers/pinctrl/samsung/pinctrl-exynos.h
@@ -108,6 +108,35 @@
 		.pctl_res_idx   = pctl_idx,			\
 	}							\
 
+#define EXYNOS850_PIN_BANK_EINTN(pins, reg, id)			\
+	{							\
+		.type		= &exynos850_bank_type_alive,	\
+		.pctl_offset	= reg,				\
+		.nr_pins	= pins,				\
+		.eint_type	= EINT_TYPE_NONE,		\
+		.name		= id				\
+	}
+
+#define EXYNOS850_PIN_BANK_EINTG(pins, reg, id, offs)		\
+	{							\
+		.type		= &exynos850_bank_type_off,	\
+		.pctl_offset	= reg,				\
+		.nr_pins	= pins,				\
+		.eint_type	= EINT_TYPE_GPIO,		\
+		.eint_offset	= offs,				\
+		.name		= id				\
+	}
+
+#define EXYNOS850_PIN_BANK_EINTW(pins, reg, id, offs)		\
+	{							\
+		.type		= &exynos850_bank_type_alive,	\
+		.pctl_offset	= reg,				\
+		.nr_pins	= pins,				\
+		.eint_type	= EINT_TYPE_WKUP,		\
+		.eint_offset	= offs,				\
+		.name		= id				\
+	}
+
 /**
  * struct exynos_weint_data: irq specific data for all the wakeup interrupts
  * generated by the external wakeup interrupt controller.
diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.c b/drivers/pinctrl/samsung/pinctrl-samsung.c
index 2975b4369f32..2a0fc63516f1 100644
--- a/drivers/pinctrl/samsung/pinctrl-samsung.c
+++ b/drivers/pinctrl/samsung/pinctrl-samsung.c
@@ -1264,6 +1264,8 @@ static const struct of_device_id samsung_pinctrl_dt_match[] = {
 		.data = &exynos5433_of_data },
 	{ .compatible = "samsung,exynos7-pinctrl",
 		.data = &exynos7_of_data },
+	{ .compatible = "samsung,exynos850-pinctrl",
+		.data = &exynos850_of_data },
 #endif
 #ifdef CONFIG_PINCTRL_S3C64XX
 	{ .compatible = "samsung,s3c64xx-pinctrl",
diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.h b/drivers/pinctrl/samsung/pinctrl-samsung.h
index de44f8ec330b..4c2149e9c544 100644
--- a/drivers/pinctrl/samsung/pinctrl-samsung.h
+++ b/drivers/pinctrl/samsung/pinctrl-samsung.h
@@ -339,6 +339,7 @@ extern const struct samsung_pinctrl_of_match_data exynos5410_of_data;
 extern const struct samsung_pinctrl_of_match_data exynos5420_of_data;
 extern const struct samsung_pinctrl_of_match_data exynos5433_of_data;
 extern const struct samsung_pinctrl_of_match_data exynos7_of_data;
+extern const struct samsung_pinctrl_of_match_data exynos850_of_data;
 extern const struct samsung_pinctrl_of_match_data s3c64xx_of_data;
 extern const struct samsung_pinctrl_of_match_data s3c2412_of_data;
 extern const struct samsung_pinctrl_of_match_data s3c2416_of_data;
-- 
2.30.2


^ permalink raw reply	[flat|nested] 17+ messages in thread

* [PATCH v3 3/7] dt-bindings: serial: samsung: Add Exynos850 doc
  2021-08-11 11:48 [PATCH v3 0/7] Add minimal support for Exynos850 SoC Sam Protsenko
  2021-08-11 11:48 ` [PATCH v3 1/7] dt-bindings: pinctrl: samsung: Add Exynos850 doc Sam Protsenko
  2021-08-11 11:48 ` [PATCH v3 2/7] pinctrl: samsung: Add Exynos850 SoC specific data Sam Protsenko
@ 2021-08-11 11:48 ` Sam Protsenko
  2021-08-17 21:21   ` Rob Herring
  2021-08-11 11:48 ` [PATCH v3 4/7] tty: serial: samsung: Init USI to keep clocks running Sam Protsenko
                   ` (4 subsequent siblings)
  7 siblings, 1 reply; 17+ messages in thread
From: Sam Protsenko @ 2021-08-11 11:48 UTC (permalink / raw)
  To: Krzysztof Kozlowski, Sylwester Nawrocki, Paweł Chmiel, Chanwoo Choi
  Cc: Linus Walleij, Tomasz Figa, Marc Zyngier, Rob Herring,
	Stephen Boyd, Michael Turquette, Jiri Slaby, Greg Kroah-Hartman,
	Charles Keepax, Ryu Euiyoul, Tom Gall, Sumit Semwal, John Stultz,
	Amit Pundir, devicetree, linux-arm-kernel, linux-gpio,
	linux-kernel, linux-samsung-soc, linux-serial

Add compatible string for Exynos850 SoC.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
---
Changes in v3:
  - None

Changes in v2:
  - None

 Documentation/devicetree/bindings/serial/samsung_uart.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/serial/samsung_uart.yaml b/Documentation/devicetree/bindings/serial/samsung_uart.yaml
index f064e5b76cf1..2940afb874b3 100644
--- a/Documentation/devicetree/bindings/serial/samsung_uart.yaml
+++ b/Documentation/devicetree/bindings/serial/samsung_uart.yaml
@@ -26,6 +26,7 @@ properties:
           - samsung,s3c6400-uart
           - samsung,s5pv210-uart
           - samsung,exynos4210-uart
+          - samsung,exynos850-uart
 
   reg:
     maxItems: 1
-- 
2.30.2


^ permalink raw reply	[flat|nested] 17+ messages in thread

* [PATCH v3 4/7] tty: serial: samsung: Init USI to keep clocks running
  2021-08-11 11:48 [PATCH v3 0/7] Add minimal support for Exynos850 SoC Sam Protsenko
                   ` (2 preceding siblings ...)
  2021-08-11 11:48 ` [PATCH v3 3/7] dt-bindings: serial: samsung: Add Exynos850 doc Sam Protsenko
@ 2021-08-11 11:48 ` Sam Protsenko
  2021-08-11 11:48 ` [PATCH v3 5/7] tty: serial: samsung: Fix driver data macros style Sam Protsenko
                   ` (3 subsequent siblings)
  7 siblings, 0 replies; 17+ messages in thread
From: Sam Protsenko @ 2021-08-11 11:48 UTC (permalink / raw)
  To: Krzysztof Kozlowski, Sylwester Nawrocki, Paweł Chmiel, Chanwoo Choi
  Cc: Linus Walleij, Tomasz Figa, Marc Zyngier, Rob Herring,
	Stephen Boyd, Michael Turquette, Jiri Slaby, Greg Kroah-Hartman,
	Charles Keepax, Ryu Euiyoul, Tom Gall, Sumit Semwal, John Stultz,
	Amit Pundir, devicetree, linux-arm-kernel, linux-gpio,
	linux-kernel, linux-samsung-soc, linux-serial

UART block is a part of USI (Universal Serial Interface) IP-core in
Samsung SoCs since Exynos9810 (e.g. in Exynos850). USI allows one to
enable one of three types of serial interface: UART, SPI or I2C. That's
possible because USI shares almost all internal circuits within each
protocol. USI also provides some additional registers so it's possible
to configure it.

One USI register called USI_OPTION has reset value of 0x0. Because of
this the clock gating behavior is controlled by hardware (HWACG =
Hardware Auto Clock Gating), which simply means the serial won't work
after reset as is. In order to make it work, USI_OPTION[2:1] bits must
be set to 0b01, so that HWACG is controlled manually (by software).
Bits meaning:
  - CLKREQ_ON = 1: clock is continuously provided to IP
  - CLKSTOP_ON = 0: drive IP_CLKREQ to High (needs to be set along with
                    CLKREQ_ON = 1)

USI is not present on older chips, like s3c2410, s3c2412, s3c2440,
s3c6400, s5pv210, exynos5433, exynos4210. So the new boolean field
'.has_usi' was added to struct s3c24xx_uart_info. USI registers will be
only actually accessed when '.has_usi' field is set to "1".

This feature is needed for further serial enablement on Exynos850, but
some other new Exynos chips (like Exynos9810) may benefit from this
feature as well.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
---
Changes in v3:
  - Added Reviewed-by tag by Krzysztof

Changes in v2:
  - Non-intrusive modification of USI registers
  - Improved comments
  - Rearranged USI register definitions to conform with existing style

 drivers/tty/serial/samsung_tty.c | 32 +++++++++++++++++++++++++++++++-
 include/linux/serial_s3c.h       |  9 +++++++++
 2 files changed, 40 insertions(+), 1 deletion(-)

diff --git a/drivers/tty/serial/samsung_tty.c b/drivers/tty/serial/samsung_tty.c
index 9fbc61151c2e..b8034c1168e0 100644
--- a/drivers/tty/serial/samsung_tty.c
+++ b/drivers/tty/serial/samsung_tty.c
@@ -65,6 +65,7 @@ enum s3c24xx_port_type {
 struct s3c24xx_uart_info {
 	char			*name;
 	enum s3c24xx_port_type	type;
+	unsigned int		has_usi;
 	unsigned int		port_type;
 	unsigned int		fifosize;
 	unsigned long		rx_fifomask;
@@ -1352,6 +1353,28 @@ static int apple_s5l_serial_startup(struct uart_port *port)
 	return ret;
 }
 
+static void exynos_usi_init(struct uart_port *port)
+{
+	struct s3c24xx_uart_port *ourport = to_ourport(port);
+	struct s3c24xx_uart_info *info = ourport->info;
+	unsigned int val;
+
+	if (!info->has_usi)
+		return;
+
+	/* Clear the software reset of USI block (it's set at startup) */
+	val = rd_regl(port, USI_CON);
+	val &= ~USI_CON_RESET_MASK;
+	wr_regl(port, USI_CON, val);
+	udelay(1);
+
+	/* Continuously provide the clock to USI IP w/o gating (for Rx mode) */
+	val = rd_regl(port, USI_OPTION);
+	val &= ~USI_OPTION_HWACG_MASK;
+	val |= USI_OPTION_HWACG_CLKREQ_ON;
+	wr_regl(port, USI_OPTION, val);
+}
+
 /* power power management control */
 
 static void s3c24xx_serial_pm(struct uart_port *port, unsigned int level,
@@ -1379,6 +1402,7 @@ static void s3c24xx_serial_pm(struct uart_port *port, unsigned int level,
 		if (!IS_ERR(ourport->baudclk))
 			clk_prepare_enable(ourport->baudclk);
 
+		exynos_usi_init(port);
 		break;
 	default:
 		dev_err(port->dev, "s3c24xx_serial: unknown pm %d\n", level);
@@ -2102,6 +2126,8 @@ static int s3c24xx_serial_init_port(struct s3c24xx_uart_port *ourport,
 	if (ret)
 		pr_warn("uart: failed to enable baudclk\n");
 
+	exynos_usi_init(port);
+
 	/* Keep all interrupts masked and cleared */
 	switch (ourport->info->type) {
 	case TYPE_S3C6400:
@@ -2750,10 +2776,11 @@ static struct s3c24xx_serial_drv_data s5pv210_serial_drv_data = {
 #endif
 
 #if defined(CONFIG_ARCH_EXYNOS)
-#define EXYNOS_COMMON_SERIAL_DRV_DATA				\
+#define EXYNOS_COMMON_SERIAL_DRV_DATA_USI(_has_usi)		\
 	.info = &(struct s3c24xx_uart_info) {			\
 		.name		= "Samsung Exynos UART",	\
 		.type		= TYPE_S3C6400,			\
+		.has_usi	= _has_usi,			\
 		.port_type	= PORT_S3C6400,			\
 		.has_divslot	= 1,				\
 		.rx_fifomask	= S5PV210_UFSTAT_RXMASK,	\
@@ -2773,6 +2800,9 @@ static struct s3c24xx_serial_drv_data s5pv210_serial_drv_data = {
 		.has_fracval	= 1,				\
 	}							\
 
+#define EXYNOS_COMMON_SERIAL_DRV_DATA				\
+	EXYNOS_COMMON_SERIAL_DRV_DATA_USI(0)
+
 static struct s3c24xx_serial_drv_data exynos4210_serial_drv_data = {
 	EXYNOS_COMMON_SERIAL_DRV_DATA,
 	.fifosize = { 256, 64, 16, 16 },
diff --git a/include/linux/serial_s3c.h b/include/linux/serial_s3c.h
index f6c3323fc4c5..cf0de4a86640 100644
--- a/include/linux/serial_s3c.h
+++ b/include/linux/serial_s3c.h
@@ -27,6 +27,15 @@
 #define S3C2410_UERSTAT	  (0x14)
 #define S3C2410_UFSTAT	  (0x18)
 #define S3C2410_UMSTAT	  (0x1C)
+#define USI_CON		  (0xC4)
+#define USI_OPTION	  (0xC8)
+
+#define USI_CON_RESET			(1<<0)
+#define USI_CON_RESET_MASK		(1<<0)
+
+#define USI_OPTION_HWACG_CLKREQ_ON	(1<<1)
+#define USI_OPTION_HWACG_CLKSTOP_ON	(1<<2)
+#define USI_OPTION_HWACG_MASK		(3<<1)
 
 #define S3C2410_LCON_CFGMASK	  ((0xF<<3)|(0x3))
 
-- 
2.30.2


^ permalink raw reply	[flat|nested] 17+ messages in thread

* [PATCH v3 5/7] tty: serial: samsung: Fix driver data macros style
  2021-08-11 11:48 [PATCH v3 0/7] Add minimal support for Exynos850 SoC Sam Protsenko
                   ` (3 preceding siblings ...)
  2021-08-11 11:48 ` [PATCH v3 4/7] tty: serial: samsung: Init USI to keep clocks running Sam Protsenko
@ 2021-08-11 11:48 ` Sam Protsenko
  2021-08-11 11:48 ` [PATCH v3 6/7] tty: serial: samsung: Add Exynos850 SoC data Sam Protsenko
                   ` (2 subsequent siblings)
  7 siblings, 0 replies; 17+ messages in thread
From: Sam Protsenko @ 2021-08-11 11:48 UTC (permalink / raw)
  To: Krzysztof Kozlowski, Sylwester Nawrocki, Paweł Chmiel, Chanwoo Choi
  Cc: Linus Walleij, Tomasz Figa, Marc Zyngier, Rob Herring,
	Stephen Boyd, Michael Turquette, Jiri Slaby, Greg Kroah-Hartman,
	Charles Keepax, Ryu Euiyoul, Tom Gall, Sumit Semwal, John Stultz,
	Amit Pundir, devicetree, linux-arm-kernel, linux-gpio,
	linux-kernel, linux-samsung-soc, linux-serial

Make checkpatch happy by fixing this error:

    ERROR: Macros with complex values should be enclosed in parentheses

Although this change is made to keep macros consistent with consequent
patches (adding driver data for new SoC), it's intentionally added as a
separate patch to ease possible porting efforts in future.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
---
Changes in v3:
  - None

Changes in v2:
  - Added Reviewed-by tag by Krzysztof Kozlowski

 drivers/tty/serial/samsung_tty.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/tty/serial/samsung_tty.c b/drivers/tty/serial/samsung_tty.c
index b8034c1168e0..130bdc978e93 100644
--- a/drivers/tty/serial/samsung_tty.c
+++ b/drivers/tty/serial/samsung_tty.c
@@ -2816,8 +2816,8 @@ static struct s3c24xx_serial_drv_data exynos5433_serial_drv_data = {
 #define EXYNOS4210_SERIAL_DRV_DATA ((kernel_ulong_t)&exynos4210_serial_drv_data)
 #define EXYNOS5433_SERIAL_DRV_DATA ((kernel_ulong_t)&exynos5433_serial_drv_data)
 #else
-#define EXYNOS4210_SERIAL_DRV_DATA (kernel_ulong_t)NULL
-#define EXYNOS5433_SERIAL_DRV_DATA (kernel_ulong_t)NULL
+#define EXYNOS4210_SERIAL_DRV_DATA ((kernel_ulong_t)NULL)
+#define EXYNOS5433_SERIAL_DRV_DATA ((kernel_ulong_t)NULL)
 #endif
 
 #ifdef CONFIG_ARCH_APPLE
-- 
2.30.2


^ permalink raw reply	[flat|nested] 17+ messages in thread

* [PATCH v3 6/7] tty: serial: samsung: Add Exynos850 SoC data
  2021-08-11 11:48 [PATCH v3 0/7] Add minimal support for Exynos850 SoC Sam Protsenko
                   ` (4 preceding siblings ...)
  2021-08-11 11:48 ` [PATCH v3 5/7] tty: serial: samsung: Fix driver data macros style Sam Protsenko
@ 2021-08-11 11:48 ` Sam Protsenko
  2021-08-11 11:48 ` [PATCH v3 7/7] arm64: dts: exynos: Add Exynos850 SoC support Sam Protsenko
  2021-08-13  7:41 ` [PATCH v3 0/7] Add minimal support for Exynos850 SoC Krzysztof Kozlowski
  7 siblings, 0 replies; 17+ messages in thread
From: Sam Protsenko @ 2021-08-11 11:48 UTC (permalink / raw)
  To: Krzysztof Kozlowski, Sylwester Nawrocki, Paweł Chmiel, Chanwoo Choi
  Cc: Linus Walleij, Tomasz Figa, Marc Zyngier, Rob Herring,
	Stephen Boyd, Michael Turquette, Jiri Slaby, Greg Kroah-Hartman,
	Charles Keepax, Ryu Euiyoul, Tom Gall, Sumit Semwal, John Stultz,
	Amit Pundir, devicetree, linux-arm-kernel, linux-gpio,
	linux-kernel, linux-samsung-soc, linux-serial

Add serial driver data for Exynos850 SoC. This driver data is basically
reusing EXYNOS_COMMON_SERIAL_DRV_DATA, which is common for all Exynos
chips, but also enables USI init, which was added in previous commit:
"tty: serial: samsung: Init USI to keep clocks running".

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
---
Changes in v3:
  - Added Reviewed-by tag by Krzysztof

Changes in v2:
  - Fixed default fifo sizes

 drivers/tty/serial/samsung_tty.c | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/drivers/tty/serial/samsung_tty.c b/drivers/tty/serial/samsung_tty.c
index 130bdc978e93..a069e7bb858f 100644
--- a/drivers/tty/serial/samsung_tty.c
+++ b/drivers/tty/serial/samsung_tty.c
@@ -2813,11 +2813,19 @@ static struct s3c24xx_serial_drv_data exynos5433_serial_drv_data = {
 	.fifosize = { 64, 256, 16, 256 },
 };
 
+static struct s3c24xx_serial_drv_data exynos850_serial_drv_data = {
+	EXYNOS_COMMON_SERIAL_DRV_DATA_USI(1),
+	.fifosize = { 256, 64, 64, 64 },
+};
+
 #define EXYNOS4210_SERIAL_DRV_DATA ((kernel_ulong_t)&exynos4210_serial_drv_data)
 #define EXYNOS5433_SERIAL_DRV_DATA ((kernel_ulong_t)&exynos5433_serial_drv_data)
+#define EXYNOS850_SERIAL_DRV_DATA ((kernel_ulong_t)&exynos850_serial_drv_data)
+
 #else
 #define EXYNOS4210_SERIAL_DRV_DATA ((kernel_ulong_t)NULL)
 #define EXYNOS5433_SERIAL_DRV_DATA ((kernel_ulong_t)NULL)
+#define EXYNOS850_SERIAL_DRV_DATA ((kernel_ulong_t)NULL)
 #endif
 
 #ifdef CONFIG_ARCH_APPLE
@@ -2873,6 +2881,9 @@ static const struct platform_device_id s3c24xx_serial_driver_ids[] = {
 	}, {
 		.name		= "s5l-uart",
 		.driver_data	= S5L_SERIAL_DRV_DATA,
+	}, {
+		.name		= "exynos850-uart",
+		.driver_data	= EXYNOS850_SERIAL_DRV_DATA,
 	},
 	{ },
 };
@@ -2896,6 +2907,8 @@ static const struct of_device_id s3c24xx_uart_dt_match[] = {
 		.data = (void *)EXYNOS5433_SERIAL_DRV_DATA },
 	{ .compatible = "apple,s5l-uart",
 		.data = (void *)S5L_SERIAL_DRV_DATA },
+	{ .compatible = "samsung,exynos850-uart",
+		.data = (void *)EXYNOS850_SERIAL_DRV_DATA },
 	{},
 };
 MODULE_DEVICE_TABLE(of, s3c24xx_uart_dt_match);
-- 
2.30.2


^ permalink raw reply	[flat|nested] 17+ messages in thread

* [PATCH v3 7/7] arm64: dts: exynos: Add Exynos850 SoC support
  2021-08-11 11:48 [PATCH v3 0/7] Add minimal support for Exynos850 SoC Sam Protsenko
                   ` (5 preceding siblings ...)
  2021-08-11 11:48 ` [PATCH v3 6/7] tty: serial: samsung: Add Exynos850 SoC data Sam Protsenko
@ 2021-08-11 11:48 ` Sam Protsenko
  2021-08-12  8:17   ` Krzysztof Kozlowski
  2021-08-17 18:42   ` Rob Herring
  2021-08-13  7:41 ` [PATCH v3 0/7] Add minimal support for Exynos850 SoC Krzysztof Kozlowski
  7 siblings, 2 replies; 17+ messages in thread
From: Sam Protsenko @ 2021-08-11 11:48 UTC (permalink / raw)
  To: Krzysztof Kozlowski, Sylwester Nawrocki, Paweł Chmiel, Chanwoo Choi
  Cc: Linus Walleij, Tomasz Figa, Marc Zyngier, Rob Herring,
	Stephen Boyd, Michael Turquette, Jiri Slaby, Greg Kroah-Hartman,
	Charles Keepax, Ryu Euiyoul, Tom Gall, Sumit Semwal, John Stultz,
	Amit Pundir, devicetree, linux-arm-kernel, linux-gpio,
	linux-kernel, linux-samsung-soc, linux-serial

Samsung Exynos850 is ARMv8-based mobile-oriented SoC.

This patch adds minimal SoC support by including next Device Tree nodes:

1. Octa cores (Cortex-A55), supporting PSCI v1.0
2. ARM architecture timer (armv8-timer)
3. Interrupt controller (GIC-400)
4. Pinctrl nodes for GPIO
5. Serial node

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
---
Changes in v3:
 - Used generic fixed clock for serial

Changes in v2:
 * Commit message:
   - Documented added dts features instead of CPU features

 * exynos850-usi.dtsi:
   - Removed, moved everything to exynos850.dtsi

 * exynos850.dtsi:
   - Root node:
     - Added comment about engineering name (Exynos3830)
     - Renamed pinctrl nodes, adding domain names
     - Used hard coded IRQ numbers instead of named constants everywhere
     - Added soc node, moved next nodes there: gic, clock, pinctrls and
       serial
     - Used address-cells=1 for soc node and removed unneeded 0x0 from
       reg properties
     - Moved exynos850-pinctrl.dtsi include line to the end of
       exynos850.dtsi
     - Coding style fixes
   - cpus:
     - Used address-cells=1 for cpus node
     - Renamed cpu@0001 to cpu@1, and so on
     - Left only "arm,cortex-a55" for cpus compatible
     - Renamed reg = <0x0001> to <0x1> for cpus
   - armv8 timer:
     - Add comment about missing HV timer IRQ to armv8 timer node
     - Removed not existing properties from armv8 timer node
     - Fixed cpu number in CPU_MASK()
     - Removed obsolete clock-frequency property
   - GIC:
     - Fixed GIC type to be GIC-400
     - Fixed size of GIC's 2nd region to be 0x2000
   - serial node:
     - Hard coded clock number for serial_0 for now; will replace with
       named const once proper clock driver is implemented
     - Removed gate_uart_clk0 clock from serial_0, as that clock is not
       supported in serial driver anyway (yet)
   - clock node:
     - Fixed clock controller node name (@0x12.. -> @12..)

 * exynos850-pinctrl.dtsi:
   - Referenced pinctrl nodes instead of defining those again in root node
   - Fixed interrupt-cells (3 -> 2)
   - Fixed USI related comments for pin config nodes
   - Removed decon_f_te_* and fm_lna_en nodes (won't be used)
   - Reordered pin config nodes by pin numbers
   - Improved all comments
   - Used existing named constants for pin-function and pin-pud
   - Fixed node names (used hyphens instead of underscore)
   - Fixed warnings found in W=1 build

 .../boot/dts/exynos/exynos850-pinctrl.dtsi    | 748 ++++++++++++++++++
 arch/arm64/boot/dts/exynos/exynos850.dtsi     | 261 ++++++
 2 files changed, 1009 insertions(+)
 create mode 100644 arch/arm64/boot/dts/exynos/exynos850-pinctrl.dtsi
 create mode 100644 arch/arm64/boot/dts/exynos/exynos850.dtsi

diff --git a/arch/arm64/boot/dts/exynos/exynos850-pinctrl.dtsi b/arch/arm64/boot/dts/exynos/exynos850-pinctrl.dtsi
new file mode 100644
index 000000000000..ba5d5f33e2f6
--- /dev/null
+++ b/arch/arm64/boot/dts/exynos/exynos850-pinctrl.dtsi
@@ -0,0 +1,748 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Samsung's Exynos850 SoC pin-mux and pin-config device tree source
+ *
+ * Copyright (C) 2017 Samsung Electronics Co., Ltd.
+ * Copyright (C) 2021 Linaro Ltd.
+ *
+ * Samsung's Exynos850 SoC pin-mux and pin-config options are listed as device
+ * tree nodes in this file.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/pinctrl/samsung.h>
+
+&pinctrl_alive {
+	gpa0: gpa0 {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+		interrupt-parent = <&gic>;
+		interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	gpa1: gpa1 {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+		interrupt-parent = <&gic>;
+		interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	gpa2: gpa2 {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+		interrupt-parent = <&gic>;
+		interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	gpa3: gpa3 {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+		interrupt-parent = <&gic>;
+		interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	gpa4: gpa4 {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+		interrupt-parent = <&gic>;
+		interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	gpq0: gpq0 {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	/* I2C5 (also called CAM_PMIC_I2C in TRM) */
+	i2c5_bus: i2c5-bus {
+		samsung,pins = "gpa3-5", "gpa3-6";
+		samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+		samsung,pin-drv = <0>;
+	};
+
+	/* I2C6 (also called MOTOR_I2C in TRM) */
+	i2c6_bus: i2c6-bus {
+		samsung,pins = "gpa3-7", "gpa4-0";
+		samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+		samsung,pin-drv = <0>;
+	};
+
+	/* USI: UART */
+	uart0_bus: uart0-bus {
+		samsung,pins = "gpq0-0", "gpq0-1";
+		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+	};
+};
+
+&pinctrl_cmgp {
+	gpm0: gpm0 {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+		interrupt-parent = <&gic>;
+		interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	gpm1: gpm1 {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+		interrupt-parent = <&gic>;
+		interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	gpm2: gpm2 {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+		interrupt-parent = <&gic>;
+		interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	gpm3: gpm3 {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+		interrupt-parent = <&gic>;
+		interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	gpm4: gpm4 {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+		interrupt-parent = <&gic>;
+		interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	gpm5: gpm5 {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+		interrupt-parent = <&gic>;
+		interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	/* USI_CMGP0: HSI2C function */
+	hsi2c3_bus: hsi2c3-bus {
+		samsung,pins = "gpm0-0", "gpm1-0";
+		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+		samsung,pin-drv = <0>;
+	};
+
+	/* USI_CMGP0: UART function (4 pins, Auto Flow Control) */
+	uart1_bus_single: uart1-bus {
+		samsung,pins = "gpm0-0", "gpm1-0", "gpm2-0", "gpm3-0";
+		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+	};
+
+	/* USI_CMGP0: UART function (2 pins, Non-Auto Flow Control) */
+	uart1_bus_dual: uart1-bus-dual {
+		samsung,pins = "gpm0-0", "gpm1-0";
+		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+	};
+
+	/* USI_CMGP0: SPI function */
+	spi1_bus: spi1-bus {
+		samsung,pins = "gpm0-0", "gpm1-0", "gpm2-0";
+		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+		samsung,pin-drv = <0>;
+	};
+
+	spi1_cs: spi1-cs {
+		samsung,pins = "gpm3-0";
+		samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
+		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+		samsung,pin-drv = <0>;
+	};
+
+	spi1_cs_func: spi1-cs-func {
+		samsung,pins = "gpm3-0";
+		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+		samsung,pin-drv = <0>;
+	};
+
+	/* USI_CMGP1: HSI2C function */
+	hsi2c4_bus: hsi2c4-bus {
+		samsung,pins = "gpm4-0", "gpm5-0";
+		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+		samsung,pin-drv = <0>;
+	};
+
+	/* USI_CMGP1: UART function (4 pins, Auto Flow Control) */
+	uart2_bus_single: uart2-bus {
+		samsung,pins = "gpm4-0", "gpm5-0", "gpm6-0", "gpm7-0";
+		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+	};
+
+	/* USI_CMGP1: UART function (2 pins, Non-Auto Flow Control) */
+	uart2_bus_dual: uart2-bus-dual {
+		samsung,pins = "gpm4-0", "gpm5-0";
+		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+	};
+
+	/* USI_CMGP1: SPI function */
+	spi2_bus: spi2-bus {
+		samsung,pins = "gpm4-0", "gpm5-0", "gpm6-0";
+		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+		samsung,pin-drv = <0>;
+	};
+
+	spi2_cs: spi2-cs {
+		samsung,pins = "gpm7-0";
+		samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
+		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+		samsung,pin-drv = <0>;
+	};
+
+	spi2_cs_func: spi2-cs-func {
+		samsung,pins = "gpm7-0";
+		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+		samsung,pin-drv = <0>;
+	};
+};
+
+&pinctrl_aud {
+	gpb0: gpb0 {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpb1: gpb1 {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	aud_codec_mclk: aud-codec-mclk {
+		samsung,pins = "gpb0-0";
+		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+		samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
+	};
+
+	aud_codec_mclk_idle: aud-codec-mclk-idle {
+		samsung,pins = "gpb0-0";
+		samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
+		samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
+	};
+
+	aud_i2s0_bus: aud-i2s0-bus {
+		samsung,pins = "gpb0-1", "gpb0-2", "gpb0-3", "gpb0-4";
+		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+		samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
+	};
+
+	aud_i2s0_idle: aud-i2s0-idle {
+		samsung,pins = "gpb0-1", "gpb0-2", "gpb0-3", "gpb0-4";
+		samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
+		samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
+	};
+
+	aud_i2s1_bus: aud-i2s1-bus {
+		samsung,pins = "gpb1-0", "gpb1-1", "gpb1-2", "gpb1-3";
+		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+		samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
+	};
+
+	aud_i2s1_idle: aud-i2s1-idle {
+		samsung,pins = "gpb1-0", "gpb1-1", "gpb1-2", "gpb1-3";
+		samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
+		samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
+	};
+
+	aud_fm_bus: aud-fm-bus {
+		samsung,pins = "gpb1-4";
+		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+		samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
+	};
+
+	aud_fm_idle: aud-fm-idle {
+		samsung,pins = "gpb1-4";
+		samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
+		samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
+	};
+};
+
+&pinctrl_hsi {
+	gpf2: gpf2 {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	sd2_clk: sd2-clk {
+		samsung,pins = "gpf2-0";
+		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+		samsung,pin-drv = <2>;
+	};
+
+	sd2_clk_fast_slew_rate_1x: sd2-clk-fast-slew-rate-1x {
+		samsung,pins = "gpf2-0";
+		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+		samsung,pin-drv = <0>;
+	};
+
+	sd2_clk_fast_slew_rate_1_5x: sd2-clk-fast-slew-rate-1-5x {
+		samsung,pins = "gpf2-0";
+		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+		samsung,pin-drv = <1>;
+	};
+
+	sd2_clk_fast_slew_rate_2x: sd2-clk-fast-slew-rate-2x {
+		samsung,pins = "gpf2-0";
+		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+		samsung,pin-drv = <2>;
+	};
+
+	sd2_clk_fast_slew_rate_2_5x: sd2-clk-fast-slew-rate-2-5x {
+		samsung,pins = "gpf2-0";
+		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+		samsung,pin-drv = <3>;
+	};
+
+	sd2_clk_fast_slew_rate_3x: sd2-clk-fast-slew-rate-3x {
+		samsung,pins = "gpf2-0";
+		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+		samsung,pin-drv = <4>;
+	};
+
+	sd2_clk_fast_slew_rate_4x: sd2-clk-fast-slew-rate-4x {
+		samsung,pins = "gpf2-0";
+		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+		samsung,pin-drv = <5>;
+	};
+
+	sd2_cmd: sd2-cmd {
+		samsung,pins = "gpf2-1";
+		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+		samsung,pin-drv = <2>;
+	 };
+
+	sd2_bus1: sd2-bus-width1 {
+		samsung,pins = "gpf2-2";
+		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+		samsung,pin-drv = <2>;
+	};
+
+	sd2_bus4: sd2-bus-width4 {
+		samsung,pins = "gpf2-3", "gpf2-4", "gpf2-5";
+		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+		samsung,pin-drv = <2>;
+	};
+
+	sd2_pins_as_pdn: sd2-pins-as-pdn {
+		samsung,pins = "gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3",
+			       "gpf2-4", "gpf2-5";
+		samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
+		samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
+	};
+};
+
+&pinctrl_core {
+	gpf0: gpf0 {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpf1: gpf1 {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	sd0_clk: sd0-clk {
+		samsung,pins = "gpf0-0";
+		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+		samsung,pin-drv = <3>;
+	};
+
+	sd0_clk_fast_slew_rate_1x: sd0-clk-fast-slew-rate-1x {
+		samsung,pins = "gpf0-0";
+		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+		samsung,pin-drv = <1>;
+	};
+
+	sd0_clk_fast_slew_rate_2x: sd0-clk-fast-slew-rate-2x {
+		samsung,pins = "gpf0-0";
+		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+		samsung,pin-drv = <2>;
+	};
+
+	sd0_clk_fast_slew_rate_3x: sd0-clk-fast-slew-rate-3x {
+		samsung,pins = "gpf0-0";
+		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+		samsung,pin-drv = <2>;
+	};
+
+	sd0_clk_fast_slew_rate_4x: sd0-clk-fast-slew-rate-4x {
+		samsung,pins = "gpf0-0";
+		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+		samsung,pin-drv = <3>;
+	};
+
+	sd0_cmd: sd0-cmd {
+		samsung,pins = "gpf0-1";
+		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+		samsung,pin-drv = <3>;
+	};
+
+	sd0_rdqs: sd0-rdqs {
+		samsung,pins = "gpf0-2";
+		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+		samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
+		samsung,pin-drv = <3>;
+	};
+
+	sd0_nreset: sd0-nreset {
+		samsung,pins = "gpf0-3";
+		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+		samsung,pin-drv = <3>;
+	};
+
+	sd0_bus1: sd0-bus-width1 {
+		samsung,pins = "gpf1-0";
+		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+		samsung,pin-drv = <3>;
+	};
+
+	sd0_bus4: sd0-bus-width4 {
+		samsung,pins = "gpf1-1", "gpf1-2", "gpf1-3";
+		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+		samsung,pin-drv = <3>;
+	};
+
+	sd0_bus8: sd0-bus-width8 {
+		samsung,pins = "gpf1-4", "gpf1-5", "gpf1-6", "gpf1-7";
+		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+		samsung,pin-drv = <3>;
+	};
+};
+
+&pinctrl_peri {
+	gpg0: gpg0 {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpp0: gpp0 {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+	gpp1: gpp1 {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpp2: gpp2 {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpg1: gpg1 {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpg2: gpg2 {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpg3: gpg3 {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpc0: gpc0 {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpc1: gpc1 {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	/* USI: HSI2C0 */
+	hsi2c0_bus: hsi2c0-bus {
+		samsung,pins = "gpc1-0", "gpc1-1";
+		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+		samsung,pin-drv = <0>;
+	};
+
+	/* USI: HSI2C1 */
+	hsi2c1_bus: hsi2c1-bus {
+		samsung,pins = "gpc1-2", "gpc1-3";
+		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+		samsung,pin-drv = <0>;
+	};
+
+	/* USI: HSI2C2 */
+	hsi2c2_bus: hsi2c2-bus {
+		samsung,pins = "gpc1-4", "gpc1-5";
+		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+		samsung,pin-drv = <0>;
+	};
+
+	/* USI: SPI */
+	spi0_bus: spi0-bus {
+		samsung,pins = "gpp2-0", "gpp2-2", "gpp2-3";
+		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+		samsung,pin-drv = <0>;
+	};
+
+	spi0_cs: spi0-cs {
+		samsung,pins = "gpp2-1";
+		samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
+		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+		samsung,pin-drv = <0>;
+	};
+
+	spi0_cs_func: spi0-cs-func {
+		samsung,pins = "gpp2-1";
+		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+		samsung,pin-drv = <0>;
+	};
+
+	i2c0_bus: i2c0-bus {
+		samsung,pins = "gpp0-0", "gpp0-1";
+		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+		samsung,pin-drv = <0>;
+	};
+
+	i2c1_bus: i2c1-bus {
+		samsung,pins = "gpp0-2", "gpp0-3";
+		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+		samsung,pin-drv = <0>;
+	};
+
+	i2c2_bus: i2c2-bus {
+		samsung,pins = "gpp0-4", "gpp0-5";
+		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+		samsung,pin-drv = <0>;
+	};
+
+	i2c3_bus: i2c3-bus {
+		samsung,pins = "gpp1-0", "gpp1-1";
+		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+		samsung,pin-drv = <0>;
+	};
+
+	i2c4_bus: i2c4-bus {
+		samsung,pins = "gpp1-2", "gpp1-3";
+		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+		samsung,pin-drv = <0>;
+	};
+
+	sensor_mclk0_in: sensor-mclk0-in {
+		samsung,pins = "gpc0-0";
+		samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
+		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+		samsung,pin-drv = <2>;
+	};
+
+	sensor_mclk0_out: sensor-mclk0-out {
+		samsung,pins = "gpc0-0";
+		samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
+		samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
+		samsung,pin-drv = <2>;
+	};
+
+	sensor_mclk0_fn: sensor-mclk0-fn {
+		samsung,pins = "gpc0-0";
+		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+		samsung,pin-drv = <2>;
+	};
+
+	sensor_mclk1_in: sensor-mclk1-in {
+		samsung,pins = "gpc0-1";
+		samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
+		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+		samsung,pin-drv = <2>;
+	};
+
+	sensor_mclk1_out: sensor-mclk1-out {
+		samsung,pins = "gpc0-1";
+		samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
+		samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
+		samsung,pin-drv = <2>;
+	};
+
+	sensor_mclk1_fn: sensor-mclk1-fn {
+		samsung,pins = "gpc0-1";
+		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+		samsung,pin-drv = <2>;
+	};
+
+	sensor_mclk2_in: sensor-mclk2-in {
+		samsung,pins = "gpc0-2";
+		samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
+		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+		samsung,pin-drv = <2>;
+	};
+
+	sensor_mclk2_out: sensor-mclk2-out {
+		samsung,pins = "gpc0-2";
+		samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
+		samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
+		samsung,pin-drv = <2>;
+	};
+
+	sensor_mclk2_fn: sensor-mclk2-fn {
+		samsung,pins = "gpc0-2";
+		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+		samsung,pin-drv = <2>;
+	};
+
+	xclkout: xclkout {
+		samsung,pins = "gpq0-2";
+		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+	};
+};
diff --git a/arch/arm64/boot/dts/exynos/exynos850.dtsi b/arch/arm64/boot/dts/exynos/exynos850.dtsi
new file mode 100644
index 000000000000..2360f142159f
--- /dev/null
+++ b/arch/arm64/boot/dts/exynos/exynos850.dtsi
@@ -0,0 +1,261 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Samsung Exynos850 SoC device tree source
+ *
+ * Copyright (C) 2018 Samsung Electronics Co., Ltd.
+ * Copyright (C) 2021 Linaro Ltd.
+ *
+ * Samsung Exynos850 SoC device nodes are listed in this file.
+ * Exynos based board files can include this file and provide
+ * values for board specific bindings.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+	/* Also known under engineering name Exynos3830 */
+	compatible = "samsung,exynos850";
+	interrupt-parent = <&gic>;
+	#address-cells = <2>;
+	#size-cells = <1>;
+
+	aliases {
+		pinctrl0 = &pinctrl_alive;
+		pinctrl1 = &pinctrl_cmgp;
+		pinctrl2 = &pinctrl_aud;
+		pinctrl3 = &pinctrl_hsi;
+		pinctrl4 = &pinctrl_core;
+		pinctrl5 = &pinctrl_peri;
+		serial0 = &serial_0;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu-map {
+			cluster0 {
+				core0 {
+					cpu = <&cpu0>;
+				};
+				core1 {
+					cpu = <&cpu1>;
+				};
+				core2 {
+					cpu = <&cpu2>;
+				};
+				core3 {
+					cpu = <&cpu3>;
+				};
+			};
+
+			cluster1 {
+				core0 {
+					cpu = <&cpu4>;
+				};
+				core1 {
+					cpu = <&cpu5>;
+				};
+				core2 {
+					cpu = <&cpu6>;
+				};
+				core3 {
+					cpu = <&cpu7>;
+				};
+			};
+		};
+
+		cpu0: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a55";
+			reg = <0x0>;
+			enable-method = "psci";
+		};
+		cpu1: cpu@1 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a55";
+			reg = <0x1>;
+			enable-method = "psci";
+		};
+		cpu2: cpu@2 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a55";
+			reg = <0x2>;
+			enable-method = "psci";
+		};
+		cpu3: cpu@3 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a55";
+			reg = <0x3>;
+			enable-method = "psci";
+		};
+		cpu4: cpu@4 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a55";
+			reg = <0x100>;
+			enable-method = "psci";
+		};
+		cpu5: cpu@5 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a55";
+			reg = <0x101>;
+			enable-method = "psci";
+		};
+		cpu6: cpu@6 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a55";
+			reg = <0x102>;
+			enable-method = "psci";
+		};
+		cpu7: cpu@7 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a55";
+			reg = <0x103>;
+			enable-method = "psci";
+		};
+	};
+
+	psci {
+		compatible = "arm,psci-1.0";
+		method = "smc";
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		/* Hypervisor Virtual Timer interrupt is not wired to GIC */
+		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) |
+					  IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) |
+					  IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) |
+					  IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) |
+					  IRQ_TYPE_LEVEL_LOW)>;
+	};
+
+	soc: soc@0 {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0x0 0x0 0x0 0x20000000>;
+
+		gic: interrupt-controller@12a01000 {
+			compatible = "arm,gic-400";
+			#interrupt-cells = <3>;
+			#address-cells = <0>;
+			reg = <0x12a01000 0x1000>,
+			      <0x12a02000 0x2000>,
+			      <0x12a04000 0x2000>,
+			      <0x12a06000 0x2000>;
+			interrupt-controller;
+			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) |
+						 IRQ_TYPE_LEVEL_HIGH)>;
+		};
+
+		/*
+		 * Keep the stub clock for serial driver, until proper clock
+		 * driver is implemented.
+		 */
+		uart_clock: uart-clock {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <200000000>;
+			clock-output-names = "uart";
+		};
+
+		pinctrl_alive: pinctrl@11850000 {
+			compatible = "samsung,exynos850-pinctrl";
+			reg = <0x11850000 0x1000>;
+			interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+
+			wakeup-interrupt-controller {
+				compatible = "samsung,exynos7-wakeup-eint";
+			};
+		};
+
+		pinctrl_cmgp: pinctrl@11c30000 {
+			compatible = "samsung,exynos850-pinctrl";
+			reg = <0x11c30000 0x1000>;
+			interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
+
+			wakeup-interrupt-controller {
+				compatible = "samsung,exynos7-wakeup-eint";
+			};
+		};
+
+		pinctrl_aud: pinctrl@14a60000 {
+			compatible = "samsung,exynos850-pinctrl";
+			reg = <0x14a60000 0x1000>;
+		};
+
+		pinctrl_hsi: pinctrl@13430000 {
+			compatible = "samsung,exynos850-pinctrl";
+			reg = <0x13430000 0x1000>;
+			interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		pinctrl_core: pinctrl@12070000 {
+			compatible = "samsung,exynos850-pinctrl";
+			reg = <0x12070000 0x1000>;
+			interrupts = <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		pinctrl_peri: pinctrl@139b0000 {
+			compatible = "samsung,exynos850-pinctrl";
+			reg = <0x139b0000 0x1000>;
+			interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		/* USI: UART */
+		serial_0: uart@13820000 {
+			compatible = "samsung,exynos850-uart";
+			reg = <0x13820000 0x100>;
+			interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&uart0_bus>;
+			clocks = <&uart_clock>;
+			clock-names = "uart";
+			status = "disabled";
+		};
+	};
+};
+
+#include "exynos850-pinctrl.dtsi"
-- 
2.30.2


^ permalink raw reply	[flat|nested] 17+ messages in thread

* Re: [PATCH v3 7/7] arm64: dts: exynos: Add Exynos850 SoC support
  2021-08-11 11:48 ` [PATCH v3 7/7] arm64: dts: exynos: Add Exynos850 SoC support Sam Protsenko
@ 2021-08-12  8:17   ` Krzysztof Kozlowski
  2021-08-12 17:42     ` Sam Protsenko
  2021-08-17 18:42   ` Rob Herring
  1 sibling, 1 reply; 17+ messages in thread
From: Krzysztof Kozlowski @ 2021-08-12  8:17 UTC (permalink / raw)
  To: Sam Protsenko, Sylwester Nawrocki, Paweł Chmiel, Chanwoo Choi
  Cc: Linus Walleij, Tomasz Figa, Marc Zyngier, Rob Herring,
	Stephen Boyd, Michael Turquette, Jiri Slaby, Greg Kroah-Hartman,
	Charles Keepax, Ryu Euiyoul, Tom Gall, Sumit Semwal, John Stultz,
	Amit Pundir, devicetree, linux-arm-kernel, linux-gpio,
	linux-kernel, linux-samsung-soc, linux-serial

On 11/08/2021 13:48, Sam Protsenko wrote:
> Samsung Exynos850 is ARMv8-based mobile-oriented SoC.
> 
> This patch adds minimal SoC support by including next Device Tree nodes:
> 
> 1. Octa cores (Cortex-A55), supporting PSCI v1.0
> 2. ARM architecture timer (armv8-timer)
> 3. Interrupt controller (GIC-400)
> 4. Pinctrl nodes for GPIO
> 5. Serial node
> 
> Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
> ---
> Changes in v3:
>  - Used generic fixed clock for serial
> 
> Changes in v2:
>  * Commit message:
>    - Documented added dts features instead of CPU features
> 
>  * exynos850-usi.dtsi:
>    - Removed, moved everything to exynos850.dtsi
> 
>  * exynos850.dtsi:
>    - Root node:
>      - Added comment about engineering name (Exynos3830)
>      - Renamed pinctrl nodes, adding domain names
>      - Used hard coded IRQ numbers instead of named constants everywhere
>      - Added soc node, moved next nodes there: gic, clock, pinctrls and
>        serial
>      - Used address-cells=1 for soc node and removed unneeded 0x0 from
>        reg properties
>      - Moved exynos850-pinctrl.dtsi include line to the end of
>        exynos850.dtsi
>      - Coding style fixes
>    - cpus:
>      - Used address-cells=1 for cpus node
>      - Renamed cpu@0001 to cpu@1, and so on
>      - Left only "arm,cortex-a55" for cpus compatible
>      - Renamed reg = <0x0001> to <0x1> for cpus
>    - armv8 timer:
>      - Add comment about missing HV timer IRQ to armv8 timer node
>      - Removed not existing properties from armv8 timer node
>      - Fixed cpu number in CPU_MASK()
>      - Removed obsolete clock-frequency property
>    - GIC:
>      - Fixed GIC type to be GIC-400
>      - Fixed size of GIC's 2nd region to be 0x2000
>    - serial node:
>      - Hard coded clock number for serial_0 for now; will replace with
>        named const once proper clock driver is implemented
>      - Removed gate_uart_clk0 clock from serial_0, as that clock is not
>        supported in serial driver anyway (yet)
>    - clock node:
>      - Fixed clock controller node name (@0x12.. -> @12..)
> 
>  * exynos850-pinctrl.dtsi:
>    - Referenced pinctrl nodes instead of defining those again in root node
>    - Fixed interrupt-cells (3 -> 2)
>    - Fixed USI related comments for pin config nodes
>    - Removed decon_f_te_* and fm_lna_en nodes (won't be used)
>    - Reordered pin config nodes by pin numbers
>    - Improved all comments
>    - Used existing named constants for pin-function and pin-pud
>    - Fixed node names (used hyphens instead of underscore)
>    - Fixed warnings found in W=1 build
> 
>  .../boot/dts/exynos/exynos850-pinctrl.dtsi    | 748 ++++++++++++++++++
>  arch/arm64/boot/dts/exynos/exynos850.dtsi     | 261 ++++++
>  2 files changed, 1009 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/exynos/exynos850-pinctrl.dtsi
>  create mode 100644 arch/arm64/boot/dts/exynos/exynos850.dtsi
> 
> diff --git a/arch/arm64/boot/dts/exynos/exynos850-pinctrl.dtsi b/arch/arm64/boot/dts/exynos/exynos850-pinctrl.dtsi
> new file mode 100644
> index 000000000000..ba5d5f33e2f6
> --- /dev/null
> +++ b/arch/arm64/boot/dts/exynos/exynos850-pinctrl.dtsi
> @@ -0,0 +1,748 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Samsung's Exynos850 SoC pin-mux and pin-config device tree source
> + *
> + * Copyright (C) 2017 Samsung Electronics Co., Ltd.
> + * Copyright (C) 2021 Linaro Ltd.
> + *
> + * Samsung's Exynos850 SoC pin-mux and pin-config options are listed as device
> + * tree nodes in this file.
> + */
> +
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/pinctrl/samsung.h>
> +
> +&pinctrl_alive {
> +	gpa0: gpa0 {
> +		gpio-controller;
> +		#gpio-cells = <2>;
> +
> +		interrupt-controller;
> +		#interrupt-cells = <2>;
> +		interrupt-parent = <&gic>;
> +		interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
> +	};
> +
> +	gpa1: gpa1 {
> +		gpio-controller;
> +		#gpio-cells = <2>;
> +
> +		interrupt-controller;
> +		#interrupt-cells = <2>;
> +		interrupt-parent = <&gic>;
> +		interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
> +	};
> +
> +	gpa2: gpa2 {
> +		gpio-controller;
> +		#gpio-cells = <2>;
> +
> +		interrupt-controller;
> +		#interrupt-cells = <2>;
> +		interrupt-parent = <&gic>;
> +		interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
> +	};
> +
> +	gpa3: gpa3 {
> +		gpio-controller;
> +		#gpio-cells = <2>;
> +
> +		interrupt-controller;
> +		#interrupt-cells = <2>;
> +		interrupt-parent = <&gic>;
> +		interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
> +	};
> +
> +	gpa4: gpa4 {
> +		gpio-controller;
> +		#gpio-cells = <2>;
> +
> +		interrupt-controller;
> +		#interrupt-cells = <2>;
> +		interrupt-parent = <&gic>;
> +		interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
> +	};
> +
> +	gpq0: gpq0 {
> +		gpio-controller;
> +		#gpio-cells = <2>;
> +
> +		interrupt-controller;
> +		#interrupt-cells = <2>;
> +	};
> +
> +	/* I2C5 (also called CAM_PMIC_I2C in TRM) */
> +	i2c5_bus: i2c5-bus {
> +		samsung,pins = "gpa3-5", "gpa3-6";
> +		samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
> +		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
> +		samsung,pin-drv = <0>;
> +	};
> +
> +	/* I2C6 (also called MOTOR_I2C in TRM) */
> +	i2c6_bus: i2c6-bus {
> +		samsung,pins = "gpa3-7", "gpa4-0";
> +		samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
> +		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
> +		samsung,pin-drv = <0>;
> +	};
> +
> +	/* USI: UART */
> +	uart0_bus: uart0-bus {
> +		samsung,pins = "gpq0-0", "gpq0-1";
> +		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> +		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> +	};
> +};
> +
> +&pinctrl_cmgp {
> +	gpm0: gpm0 {
> +		gpio-controller;
> +		#gpio-cells = <2>;
> +
> +		interrupt-controller;
> +		#interrupt-cells = <2>;
> +		interrupt-parent = <&gic>;
> +		interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
> +	};
> +
> +	gpm1: gpm1 {
> +		gpio-controller;
> +		#gpio-cells = <2>;
> +
> +		interrupt-controller;
> +		#interrupt-cells = <2>;
> +		interrupt-parent = <&gic>;
> +		interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
> +	};
> +
> +	gpm2: gpm2 {
> +		gpio-controller;
> +		#gpio-cells = <2>;
> +
> +		interrupt-controller;
> +		#interrupt-cells = <2>;
> +		interrupt-parent = <&gic>;
> +		interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
> +	};
> +
> +	gpm3: gpm3 {
> +		gpio-controller;
> +		#gpio-cells = <2>;
> +
> +		interrupt-controller;
> +		#interrupt-cells = <2>;
> +		interrupt-parent = <&gic>;
> +		interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
> +	};
> +
> +	gpm4: gpm4 {
> +		gpio-controller;
> +		#gpio-cells = <2>;
> +
> +		interrupt-controller;
> +		#interrupt-cells = <2>;
> +		interrupt-parent = <&gic>;
> +		interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
> +	};
> +
> +	gpm5: gpm5 {
> +		gpio-controller;
> +		#gpio-cells = <2>;
> +
> +		interrupt-controller;
> +		#interrupt-cells = <2>;
> +		interrupt-parent = <&gic>;
> +		interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
> +	};
> +
> +	/* USI_CMGP0: HSI2C function */
> +	hsi2c3_bus: hsi2c3-bus {
> +		samsung,pins = "gpm0-0", "gpm1-0";
> +		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> +		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
> +		samsung,pin-drv = <0>;

There are also macros for DRV.

I assume you checked whether the actual values of FUNC/PULL/DRV macros
match Exynos850 datasheet.

> +	};
> +
> +	/* USI_CMGP0: UART function (4 pins, Auto Flow Control) */
> +	uart1_bus_single: uart1-bus {
> +		samsung,pins = "gpm0-0", "gpm1-0", "gpm2-0", "gpm3-0";
> +		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> +		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> +	};
> +
> +	/* USI_CMGP0: UART function (2 pins, Non-Auto Flow Control) */
> +	uart1_bus_dual: uart1-bus-dual {
> +		samsung,pins = "gpm0-0", "gpm1-0";
> +		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> +		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> +	};
> +
> +	/* USI_CMGP0: SPI function */
> +	spi1_bus: spi1-bus {
> +		samsung,pins = "gpm0-0", "gpm1-0", "gpm2-0";
> +		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> +		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> +		samsung,pin-drv = <0>;
> +	};
> +
> +	spi1_cs: spi1-cs {
> +		samsung,pins = "gpm3-0";
> +		samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
> +		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> +		samsung,pin-drv = <0>;
> +	};
> +
> +	spi1_cs_func: spi1-cs-func {
> +		samsung,pins = "gpm3-0";
> +		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> +		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> +		samsung,pin-drv = <0>;
> +	};
> +
> +	/* USI_CMGP1: HSI2C function */
> +	hsi2c4_bus: hsi2c4-bus {
> +		samsung,pins = "gpm4-0", "gpm5-0";
> +		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> +		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
> +		samsung,pin-drv = <0>;
> +	};
> +
> +	/* USI_CMGP1: UART function (4 pins, Auto Flow Control) */
> +	uart2_bus_single: uart2-bus {
> +		samsung,pins = "gpm4-0", "gpm5-0", "gpm6-0", "gpm7-0";
> +		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> +		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> +	};
> +
> +	/* USI_CMGP1: UART function (2 pins, Non-Auto Flow Control) */
> +	uart2_bus_dual: uart2-bus-dual {
> +		samsung,pins = "gpm4-0", "gpm5-0";
> +		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> +		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> +	};
> +
> +	/* USI_CMGP1: SPI function */
> +	spi2_bus: spi2-bus {
> +		samsung,pins = "gpm4-0", "gpm5-0", "gpm6-0";
> +		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> +		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> +		samsung,pin-drv = <0>;
> +	};
> +
> +	spi2_cs: spi2-cs {
> +		samsung,pins = "gpm7-0";
> +		samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
> +		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> +		samsung,pin-drv = <0>;
> +	};
> +
> +	spi2_cs_func: spi2-cs-func {
> +		samsung,pins = "gpm7-0";
> +		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> +		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> +		samsung,pin-drv = <0>;
> +	};
> +};
> +
> +&pinctrl_aud {
> +	gpb0: gpb0 {
> +		gpio-controller;
> +		#gpio-cells = <2>;
> +
> +		interrupt-controller;
> +		#interrupt-cells = <2>;
> +	};
> +
> +	gpb1: gpb1 {
> +		gpio-controller;
> +		#gpio-cells = <2>;
> +
> +		interrupt-controller;
> +		#interrupt-cells = <2>;
> +	};
> +
> +	aud_codec_mclk: aud-codec-mclk {
> +		samsung,pins = "gpb0-0";
> +		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> +		samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
> +	};
> +
> +	aud_codec_mclk_idle: aud-codec-mclk-idle {
> +		samsung,pins = "gpb0-0";
> +		samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
> +		samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
> +	};
> +
> +	aud_i2s0_bus: aud-i2s0-bus {
> +		samsung,pins = "gpb0-1", "gpb0-2", "gpb0-3", "gpb0-4";
> +		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> +		samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
> +	};
> +
> +	aud_i2s0_idle: aud-i2s0-idle {
> +		samsung,pins = "gpb0-1", "gpb0-2", "gpb0-3", "gpb0-4";
> +		samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
> +		samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
> +	};
> +
> +	aud_i2s1_bus: aud-i2s1-bus {
> +		samsung,pins = "gpb1-0", "gpb1-1", "gpb1-2", "gpb1-3";
> +		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> +		samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
> +	};
> +
> +	aud_i2s1_idle: aud-i2s1-idle {
> +		samsung,pins = "gpb1-0", "gpb1-1", "gpb1-2", "gpb1-3";
> +		samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
> +		samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
> +	};
> +
> +	aud_fm_bus: aud-fm-bus {
> +		samsung,pins = "gpb1-4";
> +		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> +		samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
> +	};
> +
> +	aud_fm_idle: aud-fm-idle {
> +		samsung,pins = "gpb1-4";
> +		samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
> +		samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
> +	};
> +};
> +
> +&pinctrl_hsi {
> +	gpf2: gpf2 {
> +		gpio-controller;
> +		#gpio-cells = <2>;
> +
> +		interrupt-controller;
> +		#interrupt-cells = <2>;
> +	};
> +
> +	sd2_clk: sd2-clk {
> +		samsung,pins = "gpf2-0";
> +		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> +		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> +		samsung,pin-drv = <2>;
> +	};
> +
> +	sd2_clk_fast_slew_rate_1x: sd2-clk-fast-slew-rate-1x {
> +		samsung,pins = "gpf2-0";
> +		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> +		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> +		samsung,pin-drv = <0>;
> +	};
> +
> +	sd2_clk_fast_slew_rate_1_5x: sd2-clk-fast-slew-rate-1-5x {
> +		samsung,pins = "gpf2-0";
> +		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> +		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> +		samsung,pin-drv = <1>;
> +	};
> +
> +	sd2_clk_fast_slew_rate_2x: sd2-clk-fast-slew-rate-2x {
> +		samsung,pins = "gpf2-0";
> +		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> +		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> +		samsung,pin-drv = <2>;
> +	};
> +
> +	sd2_clk_fast_slew_rate_2_5x: sd2-clk-fast-slew-rate-2-5x {
> +		samsung,pins = "gpf2-0";
> +		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> +		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> +		samsung,pin-drv = <3>;
> +	};
> +
> +	sd2_clk_fast_slew_rate_3x: sd2-clk-fast-slew-rate-3x {
> +		samsung,pins = "gpf2-0";
> +		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> +		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> +		samsung,pin-drv = <4>;
> +	};
> +
> +	sd2_clk_fast_slew_rate_4x: sd2-clk-fast-slew-rate-4x {
> +		samsung,pins = "gpf2-0";
> +		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> +		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> +		samsung,pin-drv = <5>;
> +	};
> +
> +	sd2_cmd: sd2-cmd {
> +		samsung,pins = "gpf2-1";
> +		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> +		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
> +		samsung,pin-drv = <2>;
> +	 };
> +
> +	sd2_bus1: sd2-bus-width1 {
> +		samsung,pins = "gpf2-2";
> +		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> +		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
> +		samsung,pin-drv = <2>;
> +	};
> +
> +	sd2_bus4: sd2-bus-width4 {
> +		samsung,pins = "gpf2-3", "gpf2-4", "gpf2-5";
> +		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> +		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
> +		samsung,pin-drv = <2>;
> +	};
> +
> +	sd2_pins_as_pdn: sd2-pins-as-pdn {
> +		samsung,pins = "gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3",
> +			       "gpf2-4", "gpf2-5";
> +		samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
> +		samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
> +	};
> +};
> +
> +&pinctrl_core {
> +	gpf0: gpf0 {
> +		gpio-controller;
> +		#gpio-cells = <2>;
> +
> +		interrupt-controller;
> +		#interrupt-cells = <2>;
> +	};
> +
> +	gpf1: gpf1 {
> +		gpio-controller;
> +		#gpio-cells = <2>;
> +
> +		interrupt-controller;
> +		#interrupt-cells = <2>;
> +	};
> +
> +	sd0_clk: sd0-clk {
> +		samsung,pins = "gpf0-0";
> +		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> +		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> +		samsung,pin-drv = <3>;
> +	};
> +
> +	sd0_clk_fast_slew_rate_1x: sd0-clk-fast-slew-rate-1x {
> +		samsung,pins = "gpf0-0";
> +		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> +		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> +		samsung,pin-drv = <1>;
> +	};
> +
> +	sd0_clk_fast_slew_rate_2x: sd0-clk-fast-slew-rate-2x {
> +		samsung,pins = "gpf0-0";
> +		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> +		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> +		samsung,pin-drv = <2>;
> +	};
> +
> +	sd0_clk_fast_slew_rate_3x: sd0-clk-fast-slew-rate-3x {
> +		samsung,pins = "gpf0-0";
> +		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> +		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> +		samsung,pin-drv = <2>;
> +	};
> +
> +	sd0_clk_fast_slew_rate_4x: sd0-clk-fast-slew-rate-4x {
> +		samsung,pins = "gpf0-0";
> +		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> +		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> +		samsung,pin-drv = <3>;
> +	};
> +
> +	sd0_cmd: sd0-cmd {
> +		samsung,pins = "gpf0-1";
> +		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> +		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
> +		samsung,pin-drv = <3>;
> +	};
> +
> +	sd0_rdqs: sd0-rdqs {
> +		samsung,pins = "gpf0-2";
> +		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> +		samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
> +		samsung,pin-drv = <3>;
> +	};
> +
> +	sd0_nreset: sd0-nreset {
> +		samsung,pins = "gpf0-3";
> +		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> +		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
> +		samsung,pin-drv = <3>;
> +	};
> +
> +	sd0_bus1: sd0-bus-width1 {
> +		samsung,pins = "gpf1-0";
> +		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> +		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
> +		samsung,pin-drv = <3>;
> +	};
> +
> +	sd0_bus4: sd0-bus-width4 {
> +		samsung,pins = "gpf1-1", "gpf1-2", "gpf1-3";
> +		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> +		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
> +		samsung,pin-drv = <3>;
> +	};
> +
> +	sd0_bus8: sd0-bus-width8 {
> +		samsung,pins = "gpf1-4", "gpf1-5", "gpf1-6", "gpf1-7";
> +		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> +		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
> +		samsung,pin-drv = <3>;
> +	};
> +};
> +
> +&pinctrl_peri {
> +	gpg0: gpg0 {
> +		gpio-controller;
> +		#gpio-cells = <2>;
> +
> +		interrupt-controller;
> +		#interrupt-cells = <2>;
> +	};
> +
> +	gpp0: gpp0 {
> +		gpio-controller;
> +		#gpio-cells = <2>;
> +
> +		interrupt-controller;
> +		#interrupt-cells = <2>;
> +	};
> +	gpp1: gpp1 {
> +		gpio-controller;
> +		#gpio-cells = <2>;
> +
> +		interrupt-controller;
> +		#interrupt-cells = <2>;
> +	};
> +
> +	gpp2: gpp2 {
> +		gpio-controller;
> +		#gpio-cells = <2>;
> +
> +		interrupt-controller;
> +		#interrupt-cells = <2>;
> +	};
> +
> +	gpg1: gpg1 {
> +		gpio-controller;
> +		#gpio-cells = <2>;
> +
> +		interrupt-controller;
> +		#interrupt-cells = <2>;
> +	};
> +
> +	gpg2: gpg2 {
> +		gpio-controller;
> +		#gpio-cells = <2>;
> +
> +		interrupt-controller;
> +		#interrupt-cells = <2>;
> +	};
> +
> +	gpg3: gpg3 {
> +		gpio-controller;
> +		#gpio-cells = <2>;
> +
> +		interrupt-controller;
> +		#interrupt-cells = <2>;
> +	};
> +
> +	gpc0: gpc0 {
> +		gpio-controller;
> +		#gpio-cells = <2>;
> +
> +		interrupt-controller;
> +		#interrupt-cells = <2>;
> +	};
> +
> +	gpc1: gpc1 {
> +		gpio-controller;
> +		#gpio-cells = <2>;
> +
> +		interrupt-controller;
> +		#interrupt-cells = <2>;
> +	};
> +
> +	/* USI: HSI2C0 */
> +	hsi2c0_bus: hsi2c0-bus {
> +		samsung,pins = "gpc1-0", "gpc1-1";
> +		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> +		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
> +		samsung,pin-drv = <0>;
> +	};
> +
> +	/* USI: HSI2C1 */
> +	hsi2c1_bus: hsi2c1-bus {
> +		samsung,pins = "gpc1-2", "gpc1-3";
> +		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> +		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
> +		samsung,pin-drv = <0>;
> +	};
> +
> +	/* USI: HSI2C2 */
> +	hsi2c2_bus: hsi2c2-bus {
> +		samsung,pins = "gpc1-4", "gpc1-5";
> +		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> +		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
> +		samsung,pin-drv = <0>;
> +	};
> +
> +	/* USI: SPI */
> +	spi0_bus: spi0-bus {
> +		samsung,pins = "gpp2-0", "gpp2-2", "gpp2-3";
> +		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> +		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> +		samsung,pin-drv = <0>;
> +	};
> +
> +	spi0_cs: spi0-cs {
> +		samsung,pins = "gpp2-1";
> +		samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
> +		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> +		samsung,pin-drv = <0>;
> +	};
> +
> +	spi0_cs_func: spi0-cs-func {
> +		samsung,pins = "gpp2-1";
> +		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> +		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> +		samsung,pin-drv = <0>;
> +	};
> +
> +	i2c0_bus: i2c0-bus {
> +		samsung,pins = "gpp0-0", "gpp0-1";
> +		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> +		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> +		samsung,pin-drv = <0>;
> +	};
> +
> +	i2c1_bus: i2c1-bus {
> +		samsung,pins = "gpp0-2", "gpp0-3";
> +		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> +		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
> +		samsung,pin-drv = <0>;
> +	};
> +
> +	i2c2_bus: i2c2-bus {
> +		samsung,pins = "gpp0-4", "gpp0-5";
> +		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> +		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
> +		samsung,pin-drv = <0>;
> +	};
> +
> +	i2c3_bus: i2c3-bus {
> +		samsung,pins = "gpp1-0", "gpp1-1";
> +		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> +		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
> +		samsung,pin-drv = <0>;
> +	};
> +
> +	i2c4_bus: i2c4-bus {
> +		samsung,pins = "gpp1-2", "gpp1-3";
> +		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> +		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
> +		samsung,pin-drv = <0>;
> +	};
> +
> +	sensor_mclk0_in: sensor-mclk0-in {
> +		samsung,pins = "gpc0-0";

All these gpc0 go before hsi2c0_bus node (to have them ordered by
datasheet pin name).

> +		samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
> +		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> +		samsung,pin-drv = <2>;
> +	};
> +

Rest looks good but anyway will wait for the board DTS. :)

Best regards,
Krzysztof

^ permalink raw reply	[flat|nested] 17+ messages in thread

* Re: [PATCH v3 7/7] arm64: dts: exynos: Add Exynos850 SoC support
  2021-08-12  8:17   ` Krzysztof Kozlowski
@ 2021-08-12 17:42     ` Sam Protsenko
  2021-08-16  9:45       ` Krzysztof Kozlowski
  0 siblings, 1 reply; 17+ messages in thread
From: Sam Protsenko @ 2021-08-12 17:42 UTC (permalink / raw)
  To: Krzysztof Kozlowski
  Cc: Sylwester Nawrocki, Paweł Chmiel, Chanwoo Choi,
	Linus Walleij, Tomasz Figa, Marc Zyngier, Rob Herring,
	Stephen Boyd, Michael Turquette, Jiri Slaby, Greg Kroah-Hartman,
	Charles Keepax, Ryu Euiyoul, Tom Gall, Sumit Semwal, John Stultz,
	Amit Pundir, devicetree, linux-arm Mailing List,
	open list:GPIO SUBSYSTEM, Linux Kernel Mailing List,
	Linux Samsung SOC, open list:SERIAL DRIVERS

On Thu, 12 Aug 2021 at 11:17, Krzysztof Kozlowski
<krzysztof.kozlowski@canonical.com> wrote:
>
> On 11/08/2021 13:48, Sam Protsenko wrote:
> > Samsung Exynos850 is ARMv8-based mobile-oriented SoC.
> >
> > This patch adds minimal SoC support by including next Device Tree nodes:
> >
> > 1. Octa cores (Cortex-A55), supporting PSCI v1.0
> > 2. ARM architecture timer (armv8-timer)
> > 3. Interrupt controller (GIC-400)
> > 4. Pinctrl nodes for GPIO
> > 5. Serial node
> >
> > Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
> > ---
> > Changes in v3:
> >  - Used generic fixed clock for serial
> >
> > Changes in v2:
> >  * Commit message:
> >    - Documented added dts features instead of CPU features
> >
> >  * exynos850-usi.dtsi:
> >    - Removed, moved everything to exynos850.dtsi
> >
> >  * exynos850.dtsi:
> >    - Root node:
> >      - Added comment about engineering name (Exynos3830)
> >      - Renamed pinctrl nodes, adding domain names
> >      - Used hard coded IRQ numbers instead of named constants everywhere
> >      - Added soc node, moved next nodes there: gic, clock, pinctrls and
> >        serial
> >      - Used address-cells=1 for soc node and removed unneeded 0x0 from
> >        reg properties
> >      - Moved exynos850-pinctrl.dtsi include line to the end of
> >        exynos850.dtsi
> >      - Coding style fixes
> >    - cpus:
> >      - Used address-cells=1 for cpus node
> >      - Renamed cpu@0001 to cpu@1, and so on
> >      - Left only "arm,cortex-a55" for cpus compatible
> >      - Renamed reg = <0x0001> to <0x1> for cpus
> >    - armv8 timer:
> >      - Add comment about missing HV timer IRQ to armv8 timer node
> >      - Removed not existing properties from armv8 timer node
> >      - Fixed cpu number in CPU_MASK()
> >      - Removed obsolete clock-frequency property
> >    - GIC:
> >      - Fixed GIC type to be GIC-400
> >      - Fixed size of GIC's 2nd region to be 0x2000
> >    - serial node:
> >      - Hard coded clock number for serial_0 for now; will replace with
> >        named const once proper clock driver is implemented
> >      - Removed gate_uart_clk0 clock from serial_0, as that clock is not
> >        supported in serial driver anyway (yet)
> >    - clock node:
> >      - Fixed clock controller node name (@0x12.. -> @12..)
> >
> >  * exynos850-pinctrl.dtsi:
> >    - Referenced pinctrl nodes instead of defining those again in root node
> >    - Fixed interrupt-cells (3 -> 2)
> >    - Fixed USI related comments for pin config nodes
> >    - Removed decon_f_te_* and fm_lna_en nodes (won't be used)
> >    - Reordered pin config nodes by pin numbers
> >    - Improved all comments
> >    - Used existing named constants for pin-function and pin-pud
> >    - Fixed node names (used hyphens instead of underscore)
> >    - Fixed warnings found in W=1 build
> >
> >  .../boot/dts/exynos/exynos850-pinctrl.dtsi    | 748 ++++++++++++++++++
> >  arch/arm64/boot/dts/exynos/exynos850.dtsi     | 261 ++++++
> >  2 files changed, 1009 insertions(+)
> >  create mode 100644 arch/arm64/boot/dts/exynos/exynos850-pinctrl.dtsi
> >  create mode 100644 arch/arm64/boot/dts/exynos/exynos850.dtsi
> >
> > diff --git a/arch/arm64/boot/dts/exynos/exynos850-pinctrl.dtsi b/arch/arm64/boot/dts/exynos/exynos850-pinctrl.dtsi
> > new file mode 100644
> > index 000000000000..ba5d5f33e2f6
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/exynos/exynos850-pinctrl.dtsi
> > @@ -0,0 +1,748 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Samsung's Exynos850 SoC pin-mux and pin-config device tree source
> > + *
> > + * Copyright (C) 2017 Samsung Electronics Co., Ltd.
> > + * Copyright (C) 2021 Linaro Ltd.
> > + *
> > + * Samsung's Exynos850 SoC pin-mux and pin-config options are listed as device
> > + * tree nodes in this file.
> > + */
> > +
> > +#include <dt-bindings/interrupt-controller/arm-gic.h>
> > +#include <dt-bindings/pinctrl/samsung.h>
> > +
> > +&pinctrl_alive {
> > +     gpa0: gpa0 {
> > +             gpio-controller;
> > +             #gpio-cells = <2>;
> > +
> > +             interrupt-controller;
> > +             #interrupt-cells = <2>;
> > +             interrupt-parent = <&gic>;
> > +             interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
> > +                          <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
> > +                          <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
> > +                          <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
> > +                          <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
> > +                          <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
> > +                          <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
> > +                          <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
> > +     };
> > +
> > +     gpa1: gpa1 {
> > +             gpio-controller;
> > +             #gpio-cells = <2>;
> > +
> > +             interrupt-controller;
> > +             #interrupt-cells = <2>;
> > +             interrupt-parent = <&gic>;
> > +             interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
> > +                          <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
> > +                          <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
> > +                          <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
> > +                          <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
> > +                          <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
> > +                          <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
> > +                          <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
> > +     };
> > +
> > +     gpa2: gpa2 {
> > +             gpio-controller;
> > +             #gpio-cells = <2>;
> > +
> > +             interrupt-controller;
> > +             #interrupt-cells = <2>;
> > +             interrupt-parent = <&gic>;
> > +             interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
> > +                          <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
> > +                          <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
> > +                          <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
> > +                          <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
> > +                          <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
> > +                          <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
> > +                          <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
> > +     };
> > +
> > +     gpa3: gpa3 {
> > +             gpio-controller;
> > +             #gpio-cells = <2>;
> > +
> > +             interrupt-controller;
> > +             #interrupt-cells = <2>;
> > +             interrupt-parent = <&gic>;
> > +             interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
> > +                          <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
> > +                          <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
> > +                          <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
> > +                          <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
> > +                          <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
> > +                          <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
> > +                          <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
> > +     };
> > +
> > +     gpa4: gpa4 {
> > +             gpio-controller;
> > +             #gpio-cells = <2>;
> > +
> > +             interrupt-controller;
> > +             #interrupt-cells = <2>;
> > +             interrupt-parent = <&gic>;
> > +             interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
> > +                          <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
> > +                          <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
> > +                          <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
> > +     };
> > +
> > +     gpq0: gpq0 {
> > +             gpio-controller;
> > +             #gpio-cells = <2>;
> > +
> > +             interrupt-controller;
> > +             #interrupt-cells = <2>;
> > +     };
> > +
> > +     /* I2C5 (also called CAM_PMIC_I2C in TRM) */
> > +     i2c5_bus: i2c5-bus {
> > +             samsung,pins = "gpa3-5", "gpa3-6";
> > +             samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
> > +             samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
> > +             samsung,pin-drv = <0>;
> > +     };
> > +
> > +     /* I2C6 (also called MOTOR_I2C in TRM) */
> > +     i2c6_bus: i2c6-bus {
> > +             samsung,pins = "gpa3-7", "gpa4-0";
> > +             samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
> > +             samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
> > +             samsung,pin-drv = <0>;
> > +     };
> > +
> > +     /* USI: UART */
> > +     uart0_bus: uart0-bus {
> > +             samsung,pins = "gpq0-0", "gpq0-1";
> > +             samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> > +             samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> > +     };
> > +};
> > +
> > +&pinctrl_cmgp {
> > +     gpm0: gpm0 {
> > +             gpio-controller;
> > +             #gpio-cells = <2>;
> > +
> > +             interrupt-controller;
> > +             #interrupt-cells = <2>;
> > +             interrupt-parent = <&gic>;
> > +             interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
> > +     };
> > +
> > +     gpm1: gpm1 {
> > +             gpio-controller;
> > +             #gpio-cells = <2>;
> > +
> > +             interrupt-controller;
> > +             #interrupt-cells = <2>;
> > +             interrupt-parent = <&gic>;
> > +             interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
> > +     };
> > +
> > +     gpm2: gpm2 {
> > +             gpio-controller;
> > +             #gpio-cells = <2>;
> > +
> > +             interrupt-controller;
> > +             #interrupt-cells = <2>;
> > +             interrupt-parent = <&gic>;
> > +             interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
> > +     };
> > +
> > +     gpm3: gpm3 {
> > +             gpio-controller;
> > +             #gpio-cells = <2>;
> > +
> > +             interrupt-controller;
> > +             #interrupt-cells = <2>;
> > +             interrupt-parent = <&gic>;
> > +             interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
> > +     };
> > +
> > +     gpm4: gpm4 {
> > +             gpio-controller;
> > +             #gpio-cells = <2>;
> > +
> > +             interrupt-controller;
> > +             #interrupt-cells = <2>;
> > +             interrupt-parent = <&gic>;
> > +             interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
> > +     };
> > +
> > +     gpm5: gpm5 {
> > +             gpio-controller;
> > +             #gpio-cells = <2>;
> > +
> > +             interrupt-controller;
> > +             #interrupt-cells = <2>;
> > +             interrupt-parent = <&gic>;
> > +             interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
> > +     };
> > +
> > +     /* USI_CMGP0: HSI2C function */
> > +     hsi2c3_bus: hsi2c3-bus {
> > +             samsung,pins = "gpm0-0", "gpm1-0";
> > +             samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> > +             samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
> > +             samsung,pin-drv = <0>;
>
> There are also macros for DRV.
>

Unfortunately, existing DRV macros won't work for Exynos850. DRV
constants have different meaning for different GPIO domains in
Exynos850, so I thought introducing several groups of DRV constants
might be confusing. But please let me know if you still want me do
that.

> I assume you checked whether the actual values of FUNC/PULL/DRV macros
> match Exynos850 datasheet.
>

Yep, they are good.

> > +     };
> > +
> > +     /* USI_CMGP0: UART function (4 pins, Auto Flow Control) */
> > +     uart1_bus_single: uart1-bus {
> > +             samsung,pins = "gpm0-0", "gpm1-0", "gpm2-0", "gpm3-0";
> > +             samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> > +             samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> > +     };
> > +
> > +     /* USI_CMGP0: UART function (2 pins, Non-Auto Flow Control) */
> > +     uart1_bus_dual: uart1-bus-dual {
> > +             samsung,pins = "gpm0-0", "gpm1-0";
> > +             samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> > +             samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> > +     };
> > +
> > +     /* USI_CMGP0: SPI function */
> > +     spi1_bus: spi1-bus {
> > +             samsung,pins = "gpm0-0", "gpm1-0", "gpm2-0";
> > +             samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> > +             samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> > +             samsung,pin-drv = <0>;
> > +     };
> > +
> > +     spi1_cs: spi1-cs {
> > +             samsung,pins = "gpm3-0";
> > +             samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
> > +             samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> > +             samsung,pin-drv = <0>;
> > +     };
> > +
> > +     spi1_cs_func: spi1-cs-func {
> > +             samsung,pins = "gpm3-0";
> > +             samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> > +             samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> > +             samsung,pin-drv = <0>;
> > +     };
> > +
> > +     /* USI_CMGP1: HSI2C function */
> > +     hsi2c4_bus: hsi2c4-bus {
> > +             samsung,pins = "gpm4-0", "gpm5-0";
> > +             samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> > +             samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
> > +             samsung,pin-drv = <0>;
> > +     };
> > +
> > +     /* USI_CMGP1: UART function (4 pins, Auto Flow Control) */
> > +     uart2_bus_single: uart2-bus {
> > +             samsung,pins = "gpm4-0", "gpm5-0", "gpm6-0", "gpm7-0";
> > +             samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> > +             samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> > +     };
> > +
> > +     /* USI_CMGP1: UART function (2 pins, Non-Auto Flow Control) */
> > +     uart2_bus_dual: uart2-bus-dual {
> > +             samsung,pins = "gpm4-0", "gpm5-0";
> > +             samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> > +             samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> > +     };
> > +
> > +     /* USI_CMGP1: SPI function */
> > +     spi2_bus: spi2-bus {
> > +             samsung,pins = "gpm4-0", "gpm5-0", "gpm6-0";
> > +             samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> > +             samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> > +             samsung,pin-drv = <0>;
> > +     };
> > +
> > +     spi2_cs: spi2-cs {
> > +             samsung,pins = "gpm7-0";
> > +             samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
> > +             samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> > +             samsung,pin-drv = <0>;
> > +     };
> > +
> > +     spi2_cs_func: spi2-cs-func {
> > +             samsung,pins = "gpm7-0";
> > +             samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> > +             samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> > +             samsung,pin-drv = <0>;
> > +     };
> > +};
> > +
> > +&pinctrl_aud {
> > +     gpb0: gpb0 {
> > +             gpio-controller;
> > +             #gpio-cells = <2>;
> > +
> > +             interrupt-controller;
> > +             #interrupt-cells = <2>;
> > +     };
> > +
> > +     gpb1: gpb1 {
> > +             gpio-controller;
> > +             #gpio-cells = <2>;
> > +
> > +             interrupt-controller;
> > +             #interrupt-cells = <2>;
> > +     };
> > +
> > +     aud_codec_mclk: aud-codec-mclk {
> > +             samsung,pins = "gpb0-0";
> > +             samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> > +             samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
> > +     };
> > +
> > +     aud_codec_mclk_idle: aud-codec-mclk-idle {
> > +             samsung,pins = "gpb0-0";
> > +             samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
> > +             samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
> > +     };
> > +
> > +     aud_i2s0_bus: aud-i2s0-bus {
> > +             samsung,pins = "gpb0-1", "gpb0-2", "gpb0-3", "gpb0-4";
> > +             samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> > +             samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
> > +     };
> > +
> > +     aud_i2s0_idle: aud-i2s0-idle {
> > +             samsung,pins = "gpb0-1", "gpb0-2", "gpb0-3", "gpb0-4";
> > +             samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
> > +             samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
> > +     };
> > +
> > +     aud_i2s1_bus: aud-i2s1-bus {
> > +             samsung,pins = "gpb1-0", "gpb1-1", "gpb1-2", "gpb1-3";
> > +             samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> > +             samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
> > +     };
> > +
> > +     aud_i2s1_idle: aud-i2s1-idle {
> > +             samsung,pins = "gpb1-0", "gpb1-1", "gpb1-2", "gpb1-3";
> > +             samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
> > +             samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
> > +     };
> > +
> > +     aud_fm_bus: aud-fm-bus {
> > +             samsung,pins = "gpb1-4";
> > +             samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> > +             samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
> > +     };
> > +
> > +     aud_fm_idle: aud-fm-idle {
> > +             samsung,pins = "gpb1-4";
> > +             samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
> > +             samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
> > +     };
> > +};
> > +
> > +&pinctrl_hsi {
> > +     gpf2: gpf2 {
> > +             gpio-controller;
> > +             #gpio-cells = <2>;
> > +
> > +             interrupt-controller;
> > +             #interrupt-cells = <2>;
> > +     };
> > +
> > +     sd2_clk: sd2-clk {
> > +             samsung,pins = "gpf2-0";
> > +             samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> > +             samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> > +             samsung,pin-drv = <2>;
> > +     };
> > +
> > +     sd2_clk_fast_slew_rate_1x: sd2-clk-fast-slew-rate-1x {
> > +             samsung,pins = "gpf2-0";
> > +             samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> > +             samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> > +             samsung,pin-drv = <0>;
> > +     };
> > +
> > +     sd2_clk_fast_slew_rate_1_5x: sd2-clk-fast-slew-rate-1-5x {
> > +             samsung,pins = "gpf2-0";
> > +             samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> > +             samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> > +             samsung,pin-drv = <1>;
> > +     };
> > +
> > +     sd2_clk_fast_slew_rate_2x: sd2-clk-fast-slew-rate-2x {
> > +             samsung,pins = "gpf2-0";
> > +             samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> > +             samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> > +             samsung,pin-drv = <2>;
> > +     };
> > +
> > +     sd2_clk_fast_slew_rate_2_5x: sd2-clk-fast-slew-rate-2-5x {
> > +             samsung,pins = "gpf2-0";
> > +             samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> > +             samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> > +             samsung,pin-drv = <3>;
> > +     };
> > +
> > +     sd2_clk_fast_slew_rate_3x: sd2-clk-fast-slew-rate-3x {
> > +             samsung,pins = "gpf2-0";
> > +             samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> > +             samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> > +             samsung,pin-drv = <4>;
> > +     };
> > +
> > +     sd2_clk_fast_slew_rate_4x: sd2-clk-fast-slew-rate-4x {
> > +             samsung,pins = "gpf2-0";
> > +             samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> > +             samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> > +             samsung,pin-drv = <5>;
> > +     };
> > +
> > +     sd2_cmd: sd2-cmd {
> > +             samsung,pins = "gpf2-1";
> > +             samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> > +             samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
> > +             samsung,pin-drv = <2>;
> > +      };
> > +
> > +     sd2_bus1: sd2-bus-width1 {
> > +             samsung,pins = "gpf2-2";
> > +             samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> > +             samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
> > +             samsung,pin-drv = <2>;
> > +     };
> > +
> > +     sd2_bus4: sd2-bus-width4 {
> > +             samsung,pins = "gpf2-3", "gpf2-4", "gpf2-5";
> > +             samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> > +             samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
> > +             samsung,pin-drv = <2>;
> > +     };
> > +
> > +     sd2_pins_as_pdn: sd2-pins-as-pdn {
> > +             samsung,pins = "gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3",
> > +                            "gpf2-4", "gpf2-5";
> > +             samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
> > +             samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
> > +     };
> > +};
> > +
> > +&pinctrl_core {
> > +     gpf0: gpf0 {
> > +             gpio-controller;
> > +             #gpio-cells = <2>;
> > +
> > +             interrupt-controller;
> > +             #interrupt-cells = <2>;
> > +     };
> > +
> > +     gpf1: gpf1 {
> > +             gpio-controller;
> > +             #gpio-cells = <2>;
> > +
> > +             interrupt-controller;
> > +             #interrupt-cells = <2>;
> > +     };
> > +
> > +     sd0_clk: sd0-clk {
> > +             samsung,pins = "gpf0-0";
> > +             samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> > +             samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> > +             samsung,pin-drv = <3>;
> > +     };
> > +
> > +     sd0_clk_fast_slew_rate_1x: sd0-clk-fast-slew-rate-1x {
> > +             samsung,pins = "gpf0-0";
> > +             samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> > +             samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> > +             samsung,pin-drv = <1>;
> > +     };
> > +
> > +     sd0_clk_fast_slew_rate_2x: sd0-clk-fast-slew-rate-2x {
> > +             samsung,pins = "gpf0-0";
> > +             samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> > +             samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> > +             samsung,pin-drv = <2>;
> > +     };
> > +
> > +     sd0_clk_fast_slew_rate_3x: sd0-clk-fast-slew-rate-3x {
> > +             samsung,pins = "gpf0-0";
> > +             samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> > +             samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> > +             samsung,pin-drv = <2>;
> > +     };
> > +
> > +     sd0_clk_fast_slew_rate_4x: sd0-clk-fast-slew-rate-4x {
> > +             samsung,pins = "gpf0-0";
> > +             samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> > +             samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> > +             samsung,pin-drv = <3>;
> > +     };
> > +
> > +     sd0_cmd: sd0-cmd {
> > +             samsung,pins = "gpf0-1";
> > +             samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> > +             samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
> > +             samsung,pin-drv = <3>;
> > +     };
> > +
> > +     sd0_rdqs: sd0-rdqs {
> > +             samsung,pins = "gpf0-2";
> > +             samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> > +             samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
> > +             samsung,pin-drv = <3>;
> > +     };
> > +
> > +     sd0_nreset: sd0-nreset {
> > +             samsung,pins = "gpf0-3";
> > +             samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> > +             samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
> > +             samsung,pin-drv = <3>;
> > +     };
> > +
> > +     sd0_bus1: sd0-bus-width1 {
> > +             samsung,pins = "gpf1-0";
> > +             samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> > +             samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
> > +             samsung,pin-drv = <3>;
> > +     };
> > +
> > +     sd0_bus4: sd0-bus-width4 {
> > +             samsung,pins = "gpf1-1", "gpf1-2", "gpf1-3";
> > +             samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> > +             samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
> > +             samsung,pin-drv = <3>;
> > +     };
> > +
> > +     sd0_bus8: sd0-bus-width8 {
> > +             samsung,pins = "gpf1-4", "gpf1-5", "gpf1-6", "gpf1-7";
> > +             samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> > +             samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
> > +             samsung,pin-drv = <3>;
> > +     };
> > +};
> > +
> > +&pinctrl_peri {
> > +     gpg0: gpg0 {
> > +             gpio-controller;
> > +             #gpio-cells = <2>;
> > +
> > +             interrupt-controller;
> > +             #interrupt-cells = <2>;
> > +     };
> > +
> > +     gpp0: gpp0 {
> > +             gpio-controller;
> > +             #gpio-cells = <2>;
> > +
> > +             interrupt-controller;
> > +             #interrupt-cells = <2>;
> > +     };
> > +     gpp1: gpp1 {
> > +             gpio-controller;
> > +             #gpio-cells = <2>;
> > +
> > +             interrupt-controller;
> > +             #interrupt-cells = <2>;
> > +     };
> > +
> > +     gpp2: gpp2 {
> > +             gpio-controller;
> > +             #gpio-cells = <2>;
> > +
> > +             interrupt-controller;
> > +             #interrupt-cells = <2>;
> > +     };
> > +
> > +     gpg1: gpg1 {
> > +             gpio-controller;
> > +             #gpio-cells = <2>;
> > +
> > +             interrupt-controller;
> > +             #interrupt-cells = <2>;
> > +     };
> > +
> > +     gpg2: gpg2 {
> > +             gpio-controller;
> > +             #gpio-cells = <2>;
> > +
> > +             interrupt-controller;
> > +             #interrupt-cells = <2>;
> > +     };
> > +
> > +     gpg3: gpg3 {
> > +             gpio-controller;
> > +             #gpio-cells = <2>;
> > +
> > +             interrupt-controller;
> > +             #interrupt-cells = <2>;
> > +     };
> > +
> > +     gpc0: gpc0 {
> > +             gpio-controller;
> > +             #gpio-cells = <2>;
> > +
> > +             interrupt-controller;
> > +             #interrupt-cells = <2>;
> > +     };
> > +
> > +     gpc1: gpc1 {
> > +             gpio-controller;
> > +             #gpio-cells = <2>;
> > +
> > +             interrupt-controller;
> > +             #interrupt-cells = <2>;
> > +     };
> > +
> > +     /* USI: HSI2C0 */
> > +     hsi2c0_bus: hsi2c0-bus {
> > +             samsung,pins = "gpc1-0", "gpc1-1";
> > +             samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> > +             samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
> > +             samsung,pin-drv = <0>;
> > +     };
> > +
> > +     /* USI: HSI2C1 */
> > +     hsi2c1_bus: hsi2c1-bus {
> > +             samsung,pins = "gpc1-2", "gpc1-3";
> > +             samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> > +             samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
> > +             samsung,pin-drv = <0>;
> > +     };
> > +
> > +     /* USI: HSI2C2 */
> > +     hsi2c2_bus: hsi2c2-bus {
> > +             samsung,pins = "gpc1-4", "gpc1-5";
> > +             samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> > +             samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
> > +             samsung,pin-drv = <0>;
> > +     };
> > +
> > +     /* USI: SPI */
> > +     spi0_bus: spi0-bus {
> > +             samsung,pins = "gpp2-0", "gpp2-2", "gpp2-3";
> > +             samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> > +             samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> > +             samsung,pin-drv = <0>;
> > +     };
> > +
> > +     spi0_cs: spi0-cs {
> > +             samsung,pins = "gpp2-1";
> > +             samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
> > +             samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> > +             samsung,pin-drv = <0>;
> > +     };
> > +
> > +     spi0_cs_func: spi0-cs-func {
> > +             samsung,pins = "gpp2-1";
> > +             samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> > +             samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> > +             samsung,pin-drv = <0>;
> > +     };
> > +
> > +     i2c0_bus: i2c0-bus {
> > +             samsung,pins = "gpp0-0", "gpp0-1";
> > +             samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> > +             samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> > +             samsung,pin-drv = <0>;
> > +     };
> > +
> > +     i2c1_bus: i2c1-bus {
> > +             samsung,pins = "gpp0-2", "gpp0-3";
> > +             samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> > +             samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
> > +             samsung,pin-drv = <0>;
> > +     };
> > +
> > +     i2c2_bus: i2c2-bus {
> > +             samsung,pins = "gpp0-4", "gpp0-5";
> > +             samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> > +             samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
> > +             samsung,pin-drv = <0>;
> > +     };
> > +
> > +     i2c3_bus: i2c3-bus {
> > +             samsung,pins = "gpp1-0", "gpp1-1";
> > +             samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> > +             samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
> > +             samsung,pin-drv = <0>;
> > +     };
> > +
> > +     i2c4_bus: i2c4-bus {
> > +             samsung,pins = "gpp1-2", "gpp1-3";
> > +             samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> > +             samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
> > +             samsung,pin-drv = <0>;
> > +     };
> > +
> > +     sensor_mclk0_in: sensor-mclk0-in {
> > +             samsung,pins = "gpc0-0";
>
> All these gpc0 go before hsi2c0_bus node (to have them ordered by
> datasheet pin name).
>

Done.

> > +             samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
> > +             samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> > +             samsung,pin-drv = <2>;
> > +     };
> > +
>
> Rest looks good but anyway will wait for the board DTS. :)
>

Sure. I'll probably send next patch series only when the board gets
announced, and will include board's dts of course.

> Best regards,
> Krzysztof

^ permalink raw reply	[flat|nested] 17+ messages in thread

* Re: [PATCH v3 0/7] Add minimal support for Exynos850 SoC
  2021-08-11 11:48 [PATCH v3 0/7] Add minimal support for Exynos850 SoC Sam Protsenko
                   ` (6 preceding siblings ...)
  2021-08-11 11:48 ` [PATCH v3 7/7] arm64: dts: exynos: Add Exynos850 SoC support Sam Protsenko
@ 2021-08-13  7:41 ` Krzysztof Kozlowski
  7 siblings, 0 replies; 17+ messages in thread
From: Krzysztof Kozlowski @ 2021-08-13  7:41 UTC (permalink / raw)
  To: Sam Protsenko, Sylwester Nawrocki, Chanwoo Choi, Paweł Chmiel
  Cc: Krzysztof Kozlowski, linux-kernel, John Stultz, linux-serial,
	Michael Turquette, Jiri Slaby, Linus Walleij, Ryu Euiyoul,
	Stephen Boyd, Tom Gall, linux-gpio, devicetree, Sumit Semwal,
	Charles Keepax, Rob Herring, linux-samsung-soc, Tomasz Figa,
	linux-arm-kernel, Marc Zyngier, Amit Pundir, Greg Kroah-Hartman

On Wed, 11 Aug 2021 14:48:20 +0300, Sam Protsenko wrote:
> This patch series adds initial platform support for Samsung Exynos850
> SoC [1]. With this patchset it's possible to run the kernel with BusyBox
> rootfs as a RAM disk. More advanced platform support (like MMC driver
> additions) will be added later. The idea is to keep the first submission
> minimal to ease the review, and then build up on top of that.
> 
> [1] https://www.samsung.com/semiconductor/minisite/exynos/products/mobileprocessor/exynos-850/
> 
> [...]

Applied, thanks!

[1/7] dt-bindings: pinctrl: samsung: Add Exynos850 doc
      commit: 71b833b329d65236285cc73f4528f08c7d3c274c
[2/7] pinctrl: samsung: Add Exynos850 SoC specific data
      commit: cdd3d945dcec0d0dab845175dc9400ab54512aa6

Best regards,
-- 
Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>

^ permalink raw reply	[flat|nested] 17+ messages in thread

* Re: [PATCH v3 7/7] arm64: dts: exynos: Add Exynos850 SoC support
  2021-08-12 17:42     ` Sam Protsenko
@ 2021-08-16  9:45       ` Krzysztof Kozlowski
  0 siblings, 0 replies; 17+ messages in thread
From: Krzysztof Kozlowski @ 2021-08-16  9:45 UTC (permalink / raw)
  To: Sam Protsenko
  Cc: Sylwester Nawrocki, Paweł Chmiel, Chanwoo Choi,
	Linus Walleij, Tomasz Figa, Marc Zyngier, Rob Herring,
	Stephen Boyd, Michael Turquette, Jiri Slaby, Greg Kroah-Hartman,
	Charles Keepax, Ryu Euiyoul, Tom Gall, Sumit Semwal, John Stultz,
	Amit Pundir, devicetree, linux-arm Mailing List,
	open list:GPIO SUBSYSTEM, Linux Kernel Mailing List,
	Linux Samsung SOC, open list:SERIAL DRIVERS

On 12/08/2021 19:42, Sam Protsenko wrote:
> On Thu, 12 Aug 2021 at 11:17, Krzysztof Kozlowski
> <krzysztof.kozlowski@canonical.com> wrote:
>>
>> On 11/08/2021 13:48, Sam Protsenko wrote:
>>> Samsung Exynos850 is ARMv8-based mobile-oriented SoC.
>>>
>>> This patch adds minimal SoC support by including next Device Tree nodes:
>>>
>>> 1. Octa cores (Cortex-A55), supporting PSCI v1.0
>>> 2. ARM architecture timer (armv8-timer)
>>> 3. Interrupt controller (GIC-400)
>>> 4. Pinctrl nodes for GPIO
>>> 5. Serial node
>>>
>>> Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
>>> ---
>>> Changes in v3:
>>>  - Used generic fixed clock for serial
>>>
>>> Changes in v2:
>>>  * Commit message:
>>>    - Documented added dts features instead of CPU features
>>>
>>>  * exynos850-usi.dtsi:
>>>    - Removed, moved everything to exynos850.dtsi
>>>
>>>  * exynos850.dtsi:
>>>    - Root node:
>>>      - Added comment about engineering name (Exynos3830)
>>>      - Renamed pinctrl nodes, adding domain names
>>>      - Used hard coded IRQ numbers instead of named constants everywhere
>>>      - Added soc node, moved next nodes there: gic, clock, pinctrls and
>>>        serial
>>>      - Used address-cells=1 for soc node and removed unneeded 0x0 from
>>>        reg properties
>>>      - Moved exynos850-pinctrl.dtsi include line to the end of
>>>        exynos850.dtsi
>>>      - Coding style fixes
>>>    - cpus:
>>>      - Used address-cells=1 for cpus node
>>>      - Renamed cpu@0001 to cpu@1, and so on
>>>      - Left only "arm,cortex-a55" for cpus compatible
>>>      - Renamed reg = <0x0001> to <0x1> for cpus
>>>    - armv8 timer:
>>>      - Add comment about missing HV timer IRQ to armv8 timer node
>>>      - Removed not existing properties from armv8 timer node
>>>      - Fixed cpu number in CPU_MASK()
>>>      - Removed obsolete clock-frequency property
>>>    - GIC:
>>>      - Fixed GIC type to be GIC-400
>>>      - Fixed size of GIC's 2nd region to be 0x2000
>>>    - serial node:
>>>      - Hard coded clock number for serial_0 for now; will replace with
>>>        named const once proper clock driver is implemented
>>>      - Removed gate_uart_clk0 clock from serial_0, as that clock is not
>>>        supported in serial driver anyway (yet)
>>>    - clock node:
>>>      - Fixed clock controller node name (@0x12.. -> @12..)
>>>
>>>  * exynos850-pinctrl.dtsi:
>>>    - Referenced pinctrl nodes instead of defining those again in root node
>>>    - Fixed interrupt-cells (3 -> 2)
>>>    - Fixed USI related comments for pin config nodes
>>>    - Removed decon_f_te_* and fm_lna_en nodes (won't be used)
>>>    - Reordered pin config nodes by pin numbers
>>>    - Improved all comments
>>>    - Used existing named constants for pin-function and pin-pud
>>>    - Fixed node names (used hyphens instead of underscore)
>>>    - Fixed warnings found in W=1 build
>>>
>>>  .../boot/dts/exynos/exynos850-pinctrl.dtsi    | 748 ++++++++++++++++++
>>>  arch/arm64/boot/dts/exynos/exynos850.dtsi     | 261 ++++++
>>>  2 files changed, 1009 insertions(+)
>>>  create mode 100644 arch/arm64/boot/dts/exynos/exynos850-pinctrl.dtsi
>>>  create mode 100644 arch/arm64/boot/dts/exynos/exynos850.dtsi
>>>
>>> diff --git a/arch/arm64/boot/dts/exynos/exynos850-pinctrl.dtsi b/arch/arm64/boot/dts/exynos/exynos850-pinctrl.dtsi
>>> new file mode 100644
>>> index 000000000000..ba5d5f33e2f6
>>> --- /dev/null
>>> +++ b/arch/arm64/boot/dts/exynos/exynos850-pinctrl.dtsi
>>> @@ -0,0 +1,748 @@
>>> +// SPDX-License-Identifier: GPL-2.0
>>> +/*
>>> + * Samsung's Exynos850 SoC pin-mux and pin-config device tree source
>>> + *
>>> + * Copyright (C) 2017 Samsung Electronics Co., Ltd.
>>> + * Copyright (C) 2021 Linaro Ltd.
>>> + *
>>> + * Samsung's Exynos850 SoC pin-mux and pin-config options are listed as device
>>> + * tree nodes in this file.
>>> + */
>>> +
>>> +#include <dt-bindings/interrupt-controller/arm-gic.h>
>>> +#include <dt-bindings/pinctrl/samsung.h>
>>> +
>>> +&pinctrl_alive {
>>> +     gpa0: gpa0 {
>>> +             gpio-controller;
>>> +             #gpio-cells = <2>;
>>> +
>>> +             interrupt-controller;
>>> +             #interrupt-cells = <2>;
>>> +             interrupt-parent = <&gic>;
>>> +             interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
>>> +                          <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
>>> +                          <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
>>> +                          <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
>>> +                          <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
>>> +                          <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
>>> +                          <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
>>> +                          <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
>>> +     };
>>> +
>>> +     gpa1: gpa1 {
>>> +             gpio-controller;
>>> +             #gpio-cells = <2>;
>>> +
>>> +             interrupt-controller;
>>> +             #interrupt-cells = <2>;
>>> +             interrupt-parent = <&gic>;
>>> +             interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
>>> +                          <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
>>> +                          <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
>>> +                          <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
>>> +                          <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
>>> +                          <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
>>> +                          <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
>>> +                          <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
>>> +     };
>>> +
>>> +     gpa2: gpa2 {
>>> +             gpio-controller;
>>> +             #gpio-cells = <2>;
>>> +
>>> +             interrupt-controller;
>>> +             #interrupt-cells = <2>;
>>> +             interrupt-parent = <&gic>;
>>> +             interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
>>> +                          <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
>>> +                          <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
>>> +                          <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
>>> +                          <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
>>> +                          <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
>>> +                          <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
>>> +                          <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
>>> +     };
>>> +
>>> +     gpa3: gpa3 {
>>> +             gpio-controller;
>>> +             #gpio-cells = <2>;
>>> +
>>> +             interrupt-controller;
>>> +             #interrupt-cells = <2>;
>>> +             interrupt-parent = <&gic>;
>>> +             interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
>>> +                          <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
>>> +                          <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
>>> +                          <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
>>> +                          <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
>>> +                          <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
>>> +                          <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
>>> +                          <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
>>> +     };
>>> +
>>> +     gpa4: gpa4 {
>>> +             gpio-controller;
>>> +             #gpio-cells = <2>;
>>> +
>>> +             interrupt-controller;
>>> +             #interrupt-cells = <2>;
>>> +             interrupt-parent = <&gic>;
>>> +             interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
>>> +                          <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
>>> +                          <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
>>> +                          <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
>>> +     };
>>> +
>>> +     gpq0: gpq0 {
>>> +             gpio-controller;
>>> +             #gpio-cells = <2>;
>>> +
>>> +             interrupt-controller;
>>> +             #interrupt-cells = <2>;
>>> +     };
>>> +
>>> +     /* I2C5 (also called CAM_PMIC_I2C in TRM) */
>>> +     i2c5_bus: i2c5-bus {
>>> +             samsung,pins = "gpa3-5", "gpa3-6";
>>> +             samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
>>> +             samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
>>> +             samsung,pin-drv = <0>;
>>> +     };
>>> +
>>> +     /* I2C6 (also called MOTOR_I2C in TRM) */
>>> +     i2c6_bus: i2c6-bus {
>>> +             samsung,pins = "gpa3-7", "gpa4-0";
>>> +             samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
>>> +             samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
>>> +             samsung,pin-drv = <0>;
>>> +     };
>>> +
>>> +     /* USI: UART */
>>> +     uart0_bus: uart0-bus {
>>> +             samsung,pins = "gpq0-0", "gpq0-1";
>>> +             samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
>>> +             samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
>>> +     };
>>> +};
>>> +
>>> +&pinctrl_cmgp {
>>> +     gpm0: gpm0 {
>>> +             gpio-controller;
>>> +             #gpio-cells = <2>;
>>> +
>>> +             interrupt-controller;
>>> +             #interrupt-cells = <2>;
>>> +             interrupt-parent = <&gic>;
>>> +             interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
>>> +     };
>>> +
>>> +     gpm1: gpm1 {
>>> +             gpio-controller;
>>> +             #gpio-cells = <2>;
>>> +
>>> +             interrupt-controller;
>>> +             #interrupt-cells = <2>;
>>> +             interrupt-parent = <&gic>;
>>> +             interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
>>> +     };
>>> +
>>> +     gpm2: gpm2 {
>>> +             gpio-controller;
>>> +             #gpio-cells = <2>;
>>> +
>>> +             interrupt-controller;
>>> +             #interrupt-cells = <2>;
>>> +             interrupt-parent = <&gic>;
>>> +             interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
>>> +     };
>>> +
>>> +     gpm3: gpm3 {
>>> +             gpio-controller;
>>> +             #gpio-cells = <2>;
>>> +
>>> +             interrupt-controller;
>>> +             #interrupt-cells = <2>;
>>> +             interrupt-parent = <&gic>;
>>> +             interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
>>> +     };
>>> +
>>> +     gpm4: gpm4 {
>>> +             gpio-controller;
>>> +             #gpio-cells = <2>;
>>> +
>>> +             interrupt-controller;
>>> +             #interrupt-cells = <2>;
>>> +             interrupt-parent = <&gic>;
>>> +             interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
>>> +     };
>>> +
>>> +     gpm5: gpm5 {
>>> +             gpio-controller;
>>> +             #gpio-cells = <2>;
>>> +
>>> +             interrupt-controller;
>>> +             #interrupt-cells = <2>;
>>> +             interrupt-parent = <&gic>;
>>> +             interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
>>> +     };
>>> +
>>> +     /* USI_CMGP0: HSI2C function */
>>> +     hsi2c3_bus: hsi2c3-bus {
>>> +             samsung,pins = "gpm0-0", "gpm1-0";
>>> +             samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
>>> +             samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
>>> +             samsung,pin-drv = <0>;
>>
>> There are also macros for DRV.
>>
> 
> Unfortunately, existing DRV macros won't work for Exynos850. DRV
> constants have different meaning for different GPIO domains in
> Exynos850, so I thought introducing several groups of DRV constants
> might be confusing. But please let me know if you still want me do
> that.
> 

Oh, damn, raw values are ok then.


Best regards,
Krzysztof

^ permalink raw reply	[flat|nested] 17+ messages in thread

* Re: [PATCH v3 7/7] arm64: dts: exynos: Add Exynos850 SoC support
  2021-08-11 11:48 ` [PATCH v3 7/7] arm64: dts: exynos: Add Exynos850 SoC support Sam Protsenko
  2021-08-12  8:17   ` Krzysztof Kozlowski
@ 2021-08-17 18:42   ` Rob Herring
  2021-08-21 20:04     ` Sam Protsenko
  1 sibling, 1 reply; 17+ messages in thread
From: Rob Herring @ 2021-08-17 18:42 UTC (permalink / raw)
  To: Sam Protsenko
  Cc: Krzysztof Kozlowski, Sylwester Nawrocki, Paweł Chmiel,
	Chanwoo Choi, Linus Walleij, Tomasz Figa, Marc Zyngier,
	Stephen Boyd, Michael Turquette, Jiri Slaby, Greg Kroah-Hartman,
	Charles Keepax, Ryu Euiyoul, Tom Gall, Sumit Semwal, John Stultz,
	Amit Pundir, devicetree, linux-arm-kernel, linux-gpio,
	linux-kernel, linux-samsung-soc, linux-serial

On Wed, Aug 11, 2021 at 02:48:27PM +0300, Sam Protsenko wrote:
> Samsung Exynos850 is ARMv8-based mobile-oriented SoC.
> 
> This patch adds minimal SoC support by including next Device Tree nodes:
> 
> 1. Octa cores (Cortex-A55), supporting PSCI v1.0
> 2. ARM architecture timer (armv8-timer)
> 3. Interrupt controller (GIC-400)
> 4. Pinctrl nodes for GPIO
> 5. Serial node
> 
> Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
> ---
> Changes in v3:
>  - Used generic fixed clock for serial
> 
> Changes in v2:
>  * Commit message:
>    - Documented added dts features instead of CPU features
> 
>  * exynos850-usi.dtsi:
>    - Removed, moved everything to exynos850.dtsi
> 
>  * exynos850.dtsi:
>    - Root node:
>      - Added comment about engineering name (Exynos3830)
>      - Renamed pinctrl nodes, adding domain names
>      - Used hard coded IRQ numbers instead of named constants everywhere
>      - Added soc node, moved next nodes there: gic, clock, pinctrls and
>        serial
>      - Used address-cells=1 for soc node and removed unneeded 0x0 from
>        reg properties
>      - Moved exynos850-pinctrl.dtsi include line to the end of
>        exynos850.dtsi
>      - Coding style fixes
>    - cpus:
>      - Used address-cells=1 for cpus node
>      - Renamed cpu@0001 to cpu@1, and so on
>      - Left only "arm,cortex-a55" for cpus compatible
>      - Renamed reg = <0x0001> to <0x1> for cpus
>    - armv8 timer:
>      - Add comment about missing HV timer IRQ to armv8 timer node
>      - Removed not existing properties from armv8 timer node
>      - Fixed cpu number in CPU_MASK()
>      - Removed obsolete clock-frequency property
>    - GIC:
>      - Fixed GIC type to be GIC-400
>      - Fixed size of GIC's 2nd region to be 0x2000
>    - serial node:
>      - Hard coded clock number for serial_0 for now; will replace with
>        named const once proper clock driver is implemented
>      - Removed gate_uart_clk0 clock from serial_0, as that clock is not
>        supported in serial driver anyway (yet)
>    - clock node:
>      - Fixed clock controller node name (@0x12.. -> @12..)
> 
>  * exynos850-pinctrl.dtsi:
>    - Referenced pinctrl nodes instead of defining those again in root node
>    - Fixed interrupt-cells (3 -> 2)
>    - Fixed USI related comments for pin config nodes
>    - Removed decon_f_te_* and fm_lna_en nodes (won't be used)
>    - Reordered pin config nodes by pin numbers
>    - Improved all comments
>    - Used existing named constants for pin-function and pin-pud
>    - Fixed node names (used hyphens instead of underscore)
>    - Fixed warnings found in W=1 build
> 
>  .../boot/dts/exynos/exynos850-pinctrl.dtsi    | 748 ++++++++++++++++++
>  arch/arm64/boot/dts/exynos/exynos850.dtsi     | 261 ++++++
>  2 files changed, 1009 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/exynos/exynos850-pinctrl.dtsi
>  create mode 100644 arch/arm64/boot/dts/exynos/exynos850.dtsi
> 
> diff --git a/arch/arm64/boot/dts/exynos/exynos850-pinctrl.dtsi b/arch/arm64/boot/dts/exynos/exynos850-pinctrl.dtsi
> new file mode 100644
> index 000000000000..ba5d5f33e2f6
> --- /dev/null
> +++ b/arch/arm64/boot/dts/exynos/exynos850-pinctrl.dtsi
> @@ -0,0 +1,748 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Samsung's Exynos850 SoC pin-mux and pin-config device tree source
> + *
> + * Copyright (C) 2017 Samsung Electronics Co., Ltd.
> + * Copyright (C) 2021 Linaro Ltd.
> + *
> + * Samsung's Exynos850 SoC pin-mux and pin-config options are listed as device
> + * tree nodes in this file.
> + */
> +
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/pinctrl/samsung.h>
> +
> +&pinctrl_alive {
> +	gpa0: gpa0 {
> +		gpio-controller;
> +		#gpio-cells = <2>;
> +
> +		interrupt-controller;
> +		#interrupt-cells = <2>;
> +		interrupt-parent = <&gic>;
> +		interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
> +	};
> +
> +	gpa1: gpa1 {
> +		gpio-controller;
> +		#gpio-cells = <2>;
> +
> +		interrupt-controller;
> +		#interrupt-cells = <2>;
> +		interrupt-parent = <&gic>;
> +		interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
> +	};
> +
> +	gpa2: gpa2 {
> +		gpio-controller;
> +		#gpio-cells = <2>;
> +
> +		interrupt-controller;
> +		#interrupt-cells = <2>;
> +		interrupt-parent = <&gic>;
> +		interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
> +	};
> +
> +	gpa3: gpa3 {
> +		gpio-controller;
> +		#gpio-cells = <2>;
> +
> +		interrupt-controller;
> +		#interrupt-cells = <2>;
> +		interrupt-parent = <&gic>;
> +		interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
> +	};
> +
> +	gpa4: gpa4 {
> +		gpio-controller;
> +		#gpio-cells = <2>;
> +
> +		interrupt-controller;
> +		#interrupt-cells = <2>;
> +		interrupt-parent = <&gic>;
> +		interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
> +	};
> +
> +	gpq0: gpq0 {
> +		gpio-controller;
> +		#gpio-cells = <2>;
> +
> +		interrupt-controller;
> +		#interrupt-cells = <2>;
> +	};
> +
> +	/* I2C5 (also called CAM_PMIC_I2C in TRM) */
> +	i2c5_bus: i2c5-bus {

Please name all the pinctrl nodes with some pattern you can match on 
once there is a schema. '-pins$' is my suggestion.

> +		samsung,pins = "gpa3-5", "gpa3-6";
> +		samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
> +		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
> +		samsung,pin-drv = <0>;
> +	};
> +
> +	/* I2C6 (also called MOTOR_I2C in TRM) */
> +	i2c6_bus: i2c6-bus {
> +		samsung,pins = "gpa3-7", "gpa4-0";
> +		samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
> +		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
> +		samsung,pin-drv = <0>;
> +	};

^ permalink raw reply	[flat|nested] 17+ messages in thread

* Re: [PATCH v3 3/7] dt-bindings: serial: samsung: Add Exynos850 doc
  2021-08-11 11:48 ` [PATCH v3 3/7] dt-bindings: serial: samsung: Add Exynos850 doc Sam Protsenko
@ 2021-08-17 21:21   ` Rob Herring
  2021-09-06 16:27     ` Sam Protsenko
  0 siblings, 1 reply; 17+ messages in thread
From: Rob Herring @ 2021-08-17 21:21 UTC (permalink / raw)
  To: Sam Protsenko
  Cc: linux-serial, Tomasz Figa, linux-samsung-soc, Linus Walleij,
	linux-kernel, Jiri Slaby, Greg Kroah-Hartman, Tom Gall,
	Marc Zyngier, Paweł Chmiel, Amit Pundir, linux-arm-kernel,
	Ryu Euiyoul, John Stultz, Charles Keepax, Krzysztof Kozlowski,
	Stephen Boyd, devicetree, linux-gpio, Sumit Semwal,
	Sylwester Nawrocki, Michael Turquette, Rob Herring, Chanwoo Choi

On Wed, 11 Aug 2021 14:48:23 +0300, Sam Protsenko wrote:
> Add compatible string for Exynos850 SoC.
> 
> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
> Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
> ---
> Changes in v3:
>   - None
> 
> Changes in v2:
>   - None
> 
>  Documentation/devicetree/bindings/serial/samsung_uart.yaml | 1 +
>  1 file changed, 1 insertion(+)
> 

Acked-by: Rob Herring <robh@kernel.org>

^ permalink raw reply	[flat|nested] 17+ messages in thread

* Re: [PATCH v3 7/7] arm64: dts: exynos: Add Exynos850 SoC support
  2021-08-17 18:42   ` Rob Herring
@ 2021-08-21 20:04     ` Sam Protsenko
  0 siblings, 0 replies; 17+ messages in thread
From: Sam Protsenko @ 2021-08-21 20:04 UTC (permalink / raw)
  To: Rob Herring
  Cc: Krzysztof Kozlowski, Sylwester Nawrocki, Paweł Chmiel,
	Chanwoo Choi, Linus Walleij, Tomasz Figa, Marc Zyngier,
	Stephen Boyd, Michael Turquette, Jiri Slaby, Greg Kroah-Hartman,
	Charles Keepax, Ryu Euiyoul, Tom Gall, Sumit Semwal, John Stultz,
	Amit Pundir, devicetree, linux-arm Mailing List,
	open list:GPIO SUBSYSTEM, Linux Kernel Mailing List,
	Linux Samsung SOC, open list:SERIAL DRIVERS

On Tue, 17 Aug 2021 at 21:42, Rob Herring <robh@kernel.org> wrote:
>
> On Wed, Aug 11, 2021 at 02:48:27PM +0300, Sam Protsenko wrote:
> > Samsung Exynos850 is ARMv8-based mobile-oriented SoC.
> >
> > This patch adds minimal SoC support by including next Device Tree nodes:
> >
> > 1. Octa cores (Cortex-A55), supporting PSCI v1.0
> > 2. ARM architecture timer (armv8-timer)
> > 3. Interrupt controller (GIC-400)
> > 4. Pinctrl nodes for GPIO
> > 5. Serial node
> >
> > Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
> > ---
> > Changes in v3:
> >  - Used generic fixed clock for serial
> >
> > Changes in v2:
> >  * Commit message:
> >    - Documented added dts features instead of CPU features
> >
> >  * exynos850-usi.dtsi:
> >    - Removed, moved everything to exynos850.dtsi
> >
> >  * exynos850.dtsi:
> >    - Root node:
> >      - Added comment about engineering name (Exynos3830)
> >      - Renamed pinctrl nodes, adding domain names
> >      - Used hard coded IRQ numbers instead of named constants everywhere
> >      - Added soc node, moved next nodes there: gic, clock, pinctrls and
> >        serial
> >      - Used address-cells=1 for soc node and removed unneeded 0x0 from
> >        reg properties
> >      - Moved exynos850-pinctrl.dtsi include line to the end of
> >        exynos850.dtsi
> >      - Coding style fixes
> >    - cpus:
> >      - Used address-cells=1 for cpus node
> >      - Renamed cpu@0001 to cpu@1, and so on
> >      - Left only "arm,cortex-a55" for cpus compatible
> >      - Renamed reg = <0x0001> to <0x1> for cpus
> >    - armv8 timer:
> >      - Add comment about missing HV timer IRQ to armv8 timer node
> >      - Removed not existing properties from armv8 timer node
> >      - Fixed cpu number in CPU_MASK()
> >      - Removed obsolete clock-frequency property
> >    - GIC:
> >      - Fixed GIC type to be GIC-400
> >      - Fixed size of GIC's 2nd region to be 0x2000
> >    - serial node:
> >      - Hard coded clock number for serial_0 for now; will replace with
> >        named const once proper clock driver is implemented
> >      - Removed gate_uart_clk0 clock from serial_0, as that clock is not
> >        supported in serial driver anyway (yet)
> >    - clock node:
> >      - Fixed clock controller node name (@0x12.. -> @12..)
> >
> >  * exynos850-pinctrl.dtsi:
> >    - Referenced pinctrl nodes instead of defining those again in root node
> >    - Fixed interrupt-cells (3 -> 2)
> >    - Fixed USI related comments for pin config nodes
> >    - Removed decon_f_te_* and fm_lna_en nodes (won't be used)
> >    - Reordered pin config nodes by pin numbers
> >    - Improved all comments
> >    - Used existing named constants for pin-function and pin-pud
> >    - Fixed node names (used hyphens instead of underscore)
> >    - Fixed warnings found in W=1 build
> >
> >  .../boot/dts/exynos/exynos850-pinctrl.dtsi    | 748 ++++++++++++++++++
> >  arch/arm64/boot/dts/exynos/exynos850.dtsi     | 261 ++++++
> >  2 files changed, 1009 insertions(+)
> >  create mode 100644 arch/arm64/boot/dts/exynos/exynos850-pinctrl.dtsi
> >  create mode 100644 arch/arm64/boot/dts/exynos/exynos850.dtsi
> >
> > diff --git a/arch/arm64/boot/dts/exynos/exynos850-pinctrl.dtsi b/arch/arm64/boot/dts/exynos/exynos850-pinctrl.dtsi
> > new file mode 100644
> > index 000000000000..ba5d5f33e2f6
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/exynos/exynos850-pinctrl.dtsi
> > @@ -0,0 +1,748 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Samsung's Exynos850 SoC pin-mux and pin-config device tree source
> > + *
> > + * Copyright (C) 2017 Samsung Electronics Co., Ltd.
> > + * Copyright (C) 2021 Linaro Ltd.
> > + *
> > + * Samsung's Exynos850 SoC pin-mux and pin-config options are listed as device
> > + * tree nodes in this file.
> > + */
> > +
> > +#include <dt-bindings/interrupt-controller/arm-gic.h>
> > +#include <dt-bindings/pinctrl/samsung.h>
> > +
> > +&pinctrl_alive {
> > +     gpa0: gpa0 {
> > +             gpio-controller;
> > +             #gpio-cells = <2>;
> > +
> > +             interrupt-controller;
> > +             #interrupt-cells = <2>;
> > +             interrupt-parent = <&gic>;
> > +             interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
> > +                          <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
> > +                          <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
> > +                          <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
> > +                          <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
> > +                          <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
> > +                          <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
> > +                          <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
> > +     };
> > +
> > +     gpa1: gpa1 {
> > +             gpio-controller;
> > +             #gpio-cells = <2>;
> > +
> > +             interrupt-controller;
> > +             #interrupt-cells = <2>;
> > +             interrupt-parent = <&gic>;
> > +             interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
> > +                          <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
> > +                          <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
> > +                          <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
> > +                          <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
> > +                          <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
> > +                          <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
> > +                          <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
> > +     };
> > +
> > +     gpa2: gpa2 {
> > +             gpio-controller;
> > +             #gpio-cells = <2>;
> > +
> > +             interrupt-controller;
> > +             #interrupt-cells = <2>;
> > +             interrupt-parent = <&gic>;
> > +             interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
> > +                          <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
> > +                          <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
> > +                          <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
> > +                          <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
> > +                          <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
> > +                          <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
> > +                          <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
> > +     };
> > +
> > +     gpa3: gpa3 {
> > +             gpio-controller;
> > +             #gpio-cells = <2>;
> > +
> > +             interrupt-controller;
> > +             #interrupt-cells = <2>;
> > +             interrupt-parent = <&gic>;
> > +             interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
> > +                          <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
> > +                          <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
> > +                          <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
> > +                          <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
> > +                          <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
> > +                          <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
> > +                          <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
> > +     };
> > +
> > +     gpa4: gpa4 {
> > +             gpio-controller;
> > +             #gpio-cells = <2>;
> > +
> > +             interrupt-controller;
> > +             #interrupt-cells = <2>;
> > +             interrupt-parent = <&gic>;
> > +             interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
> > +                          <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
> > +                          <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
> > +                          <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
> > +     };
> > +
> > +     gpq0: gpq0 {
> > +             gpio-controller;
> > +             #gpio-cells = <2>;
> > +
> > +             interrupt-controller;
> > +             #interrupt-cells = <2>;
> > +     };
> > +
> > +     /* I2C5 (also called CAM_PMIC_I2C in TRM) */
> > +     i2c5_bus: i2c5-bus {
>
> Please name all the pinctrl nodes with some pattern you can match on
> once there is a schema. '-pins$' is my suggestion.
>

Done. This looks much better, the change will be present in new patch
series including board dts.

Can I ask for more info about schema you mentioned: is there some doc
or examples I can check? And is it something generic, or I have to
implement it for Exynos850 dts?

Thanks!

> > +             samsung,pins = "gpa3-5", "gpa3-6";
> > +             samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
> > +             samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
> > +             samsung,pin-drv = <0>;
> > +     };
> > +
> > +     /* I2C6 (also called MOTOR_I2C in TRM) */
> > +     i2c6_bus: i2c6-bus {
> > +             samsung,pins = "gpa3-7", "gpa4-0";
> > +             samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
> > +             samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
> > +             samsung,pin-drv = <0>;
> > +     };

^ permalink raw reply	[flat|nested] 17+ messages in thread

* Re: [PATCH v3 3/7] dt-bindings: serial: samsung: Add Exynos850 doc
  2021-08-17 21:21   ` Rob Herring
@ 2021-09-06 16:27     ` Sam Protsenko
  2021-09-07  7:52       ` Krzysztof Kozlowski
  0 siblings, 1 reply; 17+ messages in thread
From: Sam Protsenko @ 2021-09-06 16:27 UTC (permalink / raw)
  To: Rob Herring, Krzysztof Kozlowski
  Cc: open list:SERIAL DRIVERS, Tomasz Figa, Linux Samsung SOC,
	Linus Walleij, Linux Kernel Mailing List, Jiri Slaby,
	Greg Kroah-Hartman, Tom Gall, Marc Zyngier, Paweł Chmiel,
	Amit Pundir, linux-arm Mailing List, Ryu Euiyoul, John Stultz,
	Charles Keepax, Stephen Boyd, devicetree,
	open list:GPIO SUBSYSTEM, Sumit Semwal, Sylwester Nawrocki,
	Michael Turquette, Rob Herring, Chanwoo Choi

On Wed, 18 Aug 2021 at 00:22, Rob Herring <robh@kernel.org> wrote:
>
> On Wed, 11 Aug 2021 14:48:23 +0300, Sam Protsenko wrote:
> > Add compatible string for Exynos850 SoC.
> >
> > Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
> > Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
> > ---
> > Changes in v3:
> >   - None
> >
> > Changes in v2:
> >   - None
> >
> >  Documentation/devicetree/bindings/serial/samsung_uart.yaml | 1 +
> >  1 file changed, 1 insertion(+)
> >
>
> Acked-by: Rob Herring <robh@kernel.org>

Hi guys,

Can we please merge this one? I can see that corresponding driver
changes were pulled in already into malinline, but this one seems to
be missed.

Thanks!

^ permalink raw reply	[flat|nested] 17+ messages in thread

* Re: [PATCH v3 3/7] dt-bindings: serial: samsung: Add Exynos850 doc
  2021-09-06 16:27     ` Sam Protsenko
@ 2021-09-07  7:52       ` Krzysztof Kozlowski
  0 siblings, 0 replies; 17+ messages in thread
From: Krzysztof Kozlowski @ 2021-09-07  7:52 UTC (permalink / raw)
  To: Sam Protsenko, Rob Herring
  Cc: open list:SERIAL DRIVERS, Tomasz Figa, Linux Samsung SOC,
	Linus Walleij, Linux Kernel Mailing List, Jiri Slaby,
	Greg Kroah-Hartman, Tom Gall, Marc Zyngier, Paweł Chmiel,
	Amit Pundir, linux-arm Mailing List, Ryu Euiyoul, John Stultz,
	Charles Keepax, Stephen Boyd, devicetree,
	open list:GPIO SUBSYSTEM, Sumit Semwal, Sylwester Nawrocki,
	Michael Turquette, Rob Herring, Chanwoo Choi

On 06/09/2021 18:27, Sam Protsenko wrote:
> On Wed, 18 Aug 2021 at 00:22, Rob Herring <robh@kernel.org> wrote:
>>
>> On Wed, 11 Aug 2021 14:48:23 +0300, Sam Protsenko wrote:
>>> Add compatible string for Exynos850 SoC.
>>>
>>> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
>>> Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
>>> ---
>>> Changes in v3:
>>>   - None
>>>
>>> Changes in v2:
>>>   - None
>>>
>>>  Documentation/devicetree/bindings/serial/samsung_uart.yaml | 1 +
>>>  1 file changed, 1 insertion(+)
>>>
>>
>> Acked-by: Rob Herring <robh@kernel.org>
> 
> Hi guys,
> 
> Can we please merge this one? I can see that corresponding driver
> changes were pulled in already into malinline, but this one seems to
> be missed.

It's a merge window, so this has to wait.

Originally, it should go via Greg's tree along with the drivers. I guess
Rob will skip it now because it has his review/ack. :) If it is still
pending after the merge window, ping me. With Rob's tag I can pick it up
via Samsung SoC.

Best regards,
Krzysztof

^ permalink raw reply	[flat|nested] 17+ messages in thread

end of thread, other threads:[~2021-09-07  7:52 UTC | newest]

Thread overview: 17+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-08-11 11:48 [PATCH v3 0/7] Add minimal support for Exynos850 SoC Sam Protsenko
2021-08-11 11:48 ` [PATCH v3 1/7] dt-bindings: pinctrl: samsung: Add Exynos850 doc Sam Protsenko
2021-08-11 11:48 ` [PATCH v3 2/7] pinctrl: samsung: Add Exynos850 SoC specific data Sam Protsenko
2021-08-11 11:48 ` [PATCH v3 3/7] dt-bindings: serial: samsung: Add Exynos850 doc Sam Protsenko
2021-08-17 21:21   ` Rob Herring
2021-09-06 16:27     ` Sam Protsenko
2021-09-07  7:52       ` Krzysztof Kozlowski
2021-08-11 11:48 ` [PATCH v3 4/7] tty: serial: samsung: Init USI to keep clocks running Sam Protsenko
2021-08-11 11:48 ` [PATCH v3 5/7] tty: serial: samsung: Fix driver data macros style Sam Protsenko
2021-08-11 11:48 ` [PATCH v3 6/7] tty: serial: samsung: Add Exynos850 SoC data Sam Protsenko
2021-08-11 11:48 ` [PATCH v3 7/7] arm64: dts: exynos: Add Exynos850 SoC support Sam Protsenko
2021-08-12  8:17   ` Krzysztof Kozlowski
2021-08-12 17:42     ` Sam Protsenko
2021-08-16  9:45       ` Krzysztof Kozlowski
2021-08-17 18:42   ` Rob Herring
2021-08-21 20:04     ` Sam Protsenko
2021-08-13  7:41 ` [PATCH v3 0/7] Add minimal support for Exynos850 SoC Krzysztof Kozlowski

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