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[84.20.244.219]) by smtp.gmail.com with ESMTPSA id f24sm6703253edc.40.2021.09.15.01.59.25 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 15 Sep 2021 01:59:27 -0700 (PDT) To: Sam Protsenko , Sylwester Nawrocki , =?UTF-8?Q?Pawe=c5=82_Chmiel?= , Chanwoo Choi , Tomasz Figa , Rob Herring , Stephen Boyd , Michael Turquette Cc: Ryu Euiyoul , Tom Gall , Sumit Semwal , John Stultz , Amit Pundir , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org References: <20210914155607.14122-1-semen.protsenko@linaro.org> <20210914155607.14122-7-semen.protsenko@linaro.org> From: Krzysztof Kozlowski Subject: Re: [PATCH 6/6] clk: samsung: Introduce Exynos850 clock driver Message-ID: <3da75dbe-2f98-39db-c455-46adead7097b@canonical.com> Date: Wed, 15 Sep 2021 10:59:24 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.13.0 MIME-Version: 1.0 In-Reply-To: <20210914155607.14122-7-semen.protsenko@linaro.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org On 14/09/2021 17:56, Sam Protsenko wrote: > This is the initial implementation adding only basic clocks like UART, > MMC, I2C and corresponding parent clocks. Design is influenced by > Exynos7 and Exynos5433 clock drivers. > > Signed-off-by: Sam Protsenko > --- > drivers/clk/samsung/Makefile | 1 + > drivers/clk/samsung/clk-exynos850.c | 700 ++++++++++++++++++++++++++++ > 2 files changed, 701 insertions(+) > create mode 100644 drivers/clk/samsung/clk-exynos850.c > > diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile > index 028b2e27a37e..c46cf11e4d0b 100644 > --- a/drivers/clk/samsung/Makefile > +++ b/drivers/clk/samsung/Makefile > @@ -17,6 +17,7 @@ obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos5433.o > obj-$(CONFIG_EXYNOS_AUDSS_CLK_CON) += clk-exynos-audss.o > obj-$(CONFIG_EXYNOS_CLKOUT) += clk-exynos-clkout.o > obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos7.o > +obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos850.o > obj-$(CONFIG_S3C2410_COMMON_CLK)+= clk-s3c2410.o > obj-$(CONFIG_S3C2410_COMMON_DCLK)+= clk-s3c2410-dclk.o > obj-$(CONFIG_S3C2412_COMMON_CLK)+= clk-s3c2412.o > diff --git a/drivers/clk/samsung/clk-exynos850.c b/drivers/clk/samsung/clk-exynos850.c > new file mode 100644 > index 000000000000..1028caa2102e > --- /dev/null > +++ b/drivers/clk/samsung/clk-exynos850.c > @@ -0,0 +1,700 @@ > +// SPDX-License-Identifier: GPL-2.0-only > +/* > + * Copyright (C) 2021 Linaro Ltd. > + * Author: Sam Protsenko > + * > + * Common Clock Framework support for Exynos850 SoC. > + */ > + > +#include > +#include > +#include > + > +#include > + > +#include "clk.h" > + > +/* Gate register bits */ > +#define GATE_MANUAL BIT(20) > +#define GATE_ENABLE_HWACG BIT(28) > + > +/* Gate register offsets range */ > +#define GATE_OFF_START 0x2000 > +#define GATE_OFF_END 0x2fff > + > +/** > + * exynos850_init_clocks - Set clocks initial configuration > + * @np: CMU device tree node with "reg" property (CMU addr) > + * @reg_offs: Register offsets array for clocks to init > + * @reg_offs_len: Number of register offsets in reg_offs array > + * > + * Set manual control mode for all gate clocks. > + */ > +static void __init exynos850_init_clocks(struct device_node *np, > + const unsigned long *reg_offs, size_t reg_offs_len) > +{ > + const __be32 *regaddr_p; > + u64 regaddr; > + u32 base; > + size_t i; > + > + /* Get the base address ("reg" property in dts) */ > + regaddr_p = of_get_address(np, 0, NULL, NULL); > + if (!regaddr_p) > + panic("%s: failed to get reg regaddr\n", __func__); > + > + regaddr = of_translate_address(np, regaddr_p); > + if (regaddr == OF_BAD_ADDR || !regaddr) > + panic("%s: bad reg regaddr\n", __func__); > + > + base = (u32)regaddr; > + > + for (i = 0; i < reg_offs_len; ++i) { > + void __iomem *reg; > + u32 val; > + > + /* Modify only gate clock registers */ > + if (reg_offs[i] < GATE_OFF_START || reg_offs[i] > GATE_OFF_END) > + continue; > + > + reg = ioremap(base + reg_offs[i], 4); You first translate the address to CPU physical address and then apply offset. This should be equivalent to one of_iomap() of entire range and iterate starting from the base pointer. IOW, I don't get why you have to map each register instead of mapping entire SFR/IO range? > + val = ioread32(reg); > + val |= GATE_MANUAL; > + val &= ~GATE_ENABLE_HWACG; > + iowrite32(val, reg); All other drivers use readl/writel, so how about keeping it consistent? Rest looks good but I did not verify the numbers :) Best regards, Krzysztof