From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.0 required=3.0 tests=BAYES_00,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D5B0FC4320A for ; Wed, 4 Aug 2021 15:01:10 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B5A8760F58 for ; Wed, 4 Aug 2021 15:01:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237104AbhHDPBW convert rfc822-to-8bit (ORCPT ); Wed, 4 Aug 2021 11:01:22 -0400 Received: from mail.kernel.org ([198.145.29.99]:35142 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231255AbhHDPBW (ORCPT ); Wed, 4 Aug 2021 11:01:22 -0400 Received: from disco-boy.misterjones.org (disco-boy.misterjones.org [51.254.78.96]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 8D34D60D07; Wed, 4 Aug 2021 15:01:09 +0000 (UTC) Received: from sofa.misterjones.org ([185.219.108.64] helo=why.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1mBIOJ-002wYT-Gx; Wed, 04 Aug 2021 16:01:07 +0100 Date: Wed, 04 Aug 2021 16:01:06 +0100 Message-ID: <87k0l1w8y5.wl-maz@kernel.org> From: Marc Zyngier To: Sam Protsenko Cc: Sylwester Nawrocki , Chanwoo Choi , Krzysztof Kozlowski , Linus Walleij , Tomasz Figa , Rob Herring , Stephen Boyd , Michael Turquette , Jiri Slaby , Greg Kroah-Hartman , Charles Keepax , Ryu Euiyoul , Tom Gall , Sumit Semwal , John Stultz , Amit Pundir , devicetree , linux-arm Mailing List , linux-clk , "open list:GPIO SUBSYSTEM" , Linux Kernel Mailing List , Linux Samsung SOC , "open list:SERIAL DRIVERS" Subject: Re: [PATCH 12/12] arm64: dts: exynos: Add Exynos850 SoC support In-Reply-To: References: <20210730144922.29111-1-semen.protsenko@linaro.org> <20210730144922.29111-13-semen.protsenko@linaro.org> <15871f8ced3c757fad1ab3b6e62c4e64@misterjones.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 8BIT X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: semen.protsenko@linaro.org, s.nawrocki@samsung.com, cw00.choi@samsung.com, krzysztof.kozlowski@canonical.com, linus.walleij@linaro.org, tomasz.figa@gmail.com, robh+dt@kernel.org, sboyd@kernel.org, mturquette@baylibre.com, jirislaby@kernel.org, gregkh@linuxfoundation.org, ckeepax@opensource.wolfsonmicro.com, ryu.real@samsung.com, tom.gall@linaro.org, sumit.semwal@linaro.org, john.stultz@linaro.org, amit.pundir@linaro.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-serial@vger.kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org On Wed, 04 Aug 2021 15:39:38 +0100, Sam Protsenko wrote: > > You are also missing the hypervisor virtual timer interrupt. > > > > Checked SoC TRM, there is no PPI for hypervisor virtual timer > interrupt, and no mentioning of it at all. Likewise, I checked ARMv8 > ARM and TRM, almost no description of it. Also, I checked other > platforms, and seems like everyone does the same (having only 4 > interrupts). And I wasn't able to find any documentation on that, so I > guess I'll leave it as is, if you don't mind. I *do* mind, and other DTs being wrong isn't a good enough excuse! ;-) >From the ARMv8 ARM (ARM DDI 0487G.b) D11.2.4 Timers In an implementation of the Generic Timer that includes EL3, if EL3 can use AArch64, the following timers are implemented: * An EL1 physical timer, that: - In Secure state, can be accessed from EL1. - In Non-secure state, can be accessed from EL1 unless those accesses are trapped to EL2. When this timer can be accessed from EL1, an EL1 control determines whether it can be accessed from EL0. * A Non-secure EL2 physical timer. * A Secure EL3 physical timer. An EL3 control determines whether this register is accessible from Secure EL1. * An EL1 virtual timer. * When FEAT_VHE is implemented, a Non-secure EL2 virtual timer. * When FEAT_SEL2 is implemented, a Secure EL2 physical timer. * When FEAT_SEL2 is implemented, a Secure EL2 virtual timer. Cortex-A55 being an ARMv8.2 implementation, it has FEAT_VHE, and thus it does have a NS-EL2 virtual timer. This is further confirmed by the TRM which documents CNTHV*_EL2 as valid system registers[1]. So the timer exists, the signal is routed out of the core, and it is likely that it is connected to the GIC. If the designers have omitted it, then it needs to be documented as such. Thanks, M. [1] https://developer.arm.com/documentation/100442/0100/register-descriptions/aarch64-system-registers/aarch64-architectural-system-register-summary -- Without deviation from the norm, progress is not possible.