From: Vivek Gautam <vivek.gautam@codeaurora.org>
To: Jaehoon Chung <jh80.chung@samsung.com>
Cc: linux-pci@vger.kernel.org,
"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"linux-samsung-soc@vger.kernel.org"
<linux-samsung-soc@vger.kernel.org>,
Bjorn Helgaas <bhelgaas@google.com>, robh+dt <robh+dt@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
Kukjin Kim <kgene@kernel.org>,
krzk@kernel.org, javier@osg.samsung.com, kishon <kishon@ti.com>,
Will Deacon <will.deacon@arm.com>,
catalin.marinas@arm.com, CPGS <cpgs@samsung.com>
Subject: Re: [RFC PATCH 1/6] phy: exynos-pcie: Add support for Exynos PCIe phy
Date: Wed, 28 Dec 2016 14:28:19 +0530 [thread overview]
Message-ID: <CAFp+6iEOvdaRdvmz45ZVpqPrdSmeKk9je0bHg9FtNg8hE8YUxg@mail.gmail.com> (raw)
In-Reply-To: <21de9ca7-e586-e5c8-ecda-d30c18bb6e40@samsung.com>
Hi Jaehoon,
On Wed, Dec 28, 2016 at 8:19 AM, Jaehoon Chung <jh80.chung@samsung.com> wrote:
> Hi Vivek,
>
> On 12/27/2016 02:53 PM, Vivek Gautam wrote:
>> Hi Jaehoon,
>>
>>
>> On Mon, Dec 26, 2016 at 10:50 AM, Jaehoon Chung <jh80.chung@samsung.com> wrote:
>>> This patch supports to use Generic Phy framework for Exynos PCIe phy.
>>> When Exynos that supported the pcie want to use the PCIe,
>>> it needs to control the phy resgister.
>>> But it should be more complex to control in their own PCIe device drivers.
>>>
>>> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
>>> ---
>>> drivers/phy/Kconfig | 9 ++
>>> drivers/phy/Makefile | 1 +
>>> drivers/phy/phy-exynos-pcie.c | 227 ++++++++++++++++++++++++++++++++++++++++++
>>> 3 files changed, 237 insertions(+)
>>> create mode 100644 drivers/phy/phy-exynos-pcie.c
>>>
>>> diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
>>> index fe00f91..94b0433 100644
>>> --- a/drivers/phy/Kconfig
>>> +++ b/drivers/phy/Kconfig
>>> @@ -341,6 +341,15 @@ config PHY_EXYNOS5_USBDRD
>>> This driver provides PHY interface for USB 3.0 DRD controller
>>> present on Exynos5 SoC series.
>>>
>>> +config PHY_EXYNOS_PCIE
>>> + bool "Exynos PCIe PHY driver"
>>
>> Is there a reason for this not being 'tristate' ?
>
> Will change.
I notice that PCI_EXYNOS5433 is bool as well.
If the host has to be 'bool' then it makes sense to have phy
also bool as well. But if PCI_EXYNOS5433 can be made
tristate, then this also changes to tristate.
>
>>
>>> + depends on ARCH_EXYNOS && OF
>>> + depends on PCI_EXYNOS5433
>>> + select GENERIC_PHY
>>> + help
>>> + Enable PCIe PHY support for Exynos SoC series.
>>
>> If this driver is for Exynos5433, then same should come in this help
>> text as well.
>
> will support the other exynos series.
> I'm working on refactoring exynos5440 with PHY generic Framework.
> Then this drive is not for only Exnyos5433. how about?
Ok, it's good then. My only concern is 'depends on PCI_EXYNOS5433'
makes it look like it is for EXYNOS5433. I am fine if that changes as well.
[...]
>>> +
>>> +#define PCIE_EXYNOS5433_PMU_PHY_OFFSET 0x730
>>> +#define PCIE_PHY_OFFSET(x) ((x) * 0x4)
>>> +
>>> +/* Sysreg Fsys register offset and bit for Exynos5433 */
>>> +#define PCIE_PHY_MAC_RESET 0x208
>>> +#define PCIE_MAC_RESET_MASK 0xFF
>>> +#define PCIE_MAC_RESET BIT(4)
>>> +#define PCIE_L1SUB_CM_CON 0x1010
>>> +#define PCIE_REFCLK_GATING_EN BIT(0)
>>> +#define PCIE_PHY_COMMON_RESET 0x1020
>>> +#define PCIE_PHY_RESET BIT(0)
>>> +#define PCIE_PHY_GLOBAL_RESET 0x1040
>>> +#define PCIE_GLOBAL_RESET BIT(0)
>>> +#define PCIE_REFCLK BIT(1)
>>> +#define PCIE_REFCLK_MASK 0x16
>>> +#define PCIE_APP_REQ_EXIT_L1_MODE BIT(5)
>>> +
>>> +enum exynos_pcie_phy_data_type {
>>> + PCIE_PHY_TYPE_EXYNOS5433,
>>> +};
>>> +
>>> +struct exynos_pcie_phy_data {
>>> + enum exynos_pcie_phy_data_type ctrl_type;
>>
>> Why do we need this controller type ?
>> If there are changes in the IP between different version,
>> then you can as well use different compatibles.
>
> Do you mean is the using "of_device_is_compatible()"?
I meant that multiple compatible strings can be added based on the
IP versions. And any IP specific data can be put in the .data field
of 'of_device_id' structure.
If there's more to differentiate between the IP versions at runtime,
you can use of_device_is_compatible().
[...]
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
next prev parent reply other threads:[~2016-12-28 8:58 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <CGME20161226052030epcas1p45f543765960d14ccf9cd40c2b9cca84b@epcas1p4.samsung.com>
2016-12-26 5:20 ` [RFC PATCH 0/6] Support the PCIe for TM2(exynos5433) Jaehoon Chung
[not found] ` <CGME20161226052030epcas5p4ea673fc4ee5c0b2664e80f53d4758553@epcas5p4.samsung.com>
2016-12-26 5:20 ` [RFC PATCH 1/6] phy: exynos-pcie: Add support for Exynos PCIe phy Jaehoon Chung
[not found] ` <20161226052029.10552-2-jh80.chung-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
2016-12-27 5:53 ` Vivek Gautam
2016-12-28 2:49 ` Jaehoon Chung
2016-12-28 8:58 ` Vivek Gautam [this message]
2016-12-28 9:35 ` Jaehoon Chung
[not found] ` <ebdb57b1-9a24-f83e-ac26-887f7a2263d3-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
2016-12-28 10:12 ` Vivek Gautam
[not found] ` <CGME20161226052030epcas1p40f87c865223a9ad8cd0cd1d6e4d54b32@epcas1p4.samsung.com>
2016-12-26 5:20 ` [RFC PATCH 2/6] Documetation: samsung-phy: add the exynos-pcie-phy binding Jaehoon Chung
[not found] ` <CGME20161226052031epcas5p451b1352d6c8c5205a69246c2994b9506@epcas5p4.samsung.com>
[not found] ` <20161226052029.10552-1-jh80.chung-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
2016-12-26 5:20 ` [RFC PATCH 3/6] ARM64: dts: exynos5433: add the pcie_phy node for PCIe Jaehoon Chung
2016-12-27 16:11 ` Krzysztof Kozlowski
2016-12-27 22:57 ` Jaehoon Chung
2016-12-26 5:20 ` [RFC PATCH 4/6] PCI: exynos5433: Add new exynos pci host controller for Exynos5433 Jaehoon Chung
[not found] ` <20161226052029.10552-5-jh80.chung-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
2016-12-26 11:49 ` Joao Pinto
2016-12-27 1:43 ` Jaehoon Chung
[not found] ` <CGME20161226052031epcas5p4f151c41189f7b3811979ca1e10aab1be@epcas5p4.samsung.com>
2016-12-26 5:20 ` [RFC PATCH 5/6] Documentation: pci: add the exynos5433-pcie binding Jaehoon Chung
2016-12-27 16:19 ` Krzysztof Kozlowski
2016-12-27 23:03 ` Jaehoon Chung
[not found] ` <CGME20161226052031epcas1p43a300fe9e59c2af410c48861cd8554d1@epcas1p4.samsung.com>
2016-12-26 5:20 ` [RFC PATCH 6/6] ARM64: exynos: add the pcie node for TM2 Jaehoon Chung
2016-12-27 16:32 ` Krzysztof Kozlowski
2016-12-27 16:33 ` Krzysztof Kozlowski
2016-12-27 23:05 ` Jaehoon Chung
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=CAFp+6iEOvdaRdvmz45ZVpqPrdSmeKk9je0bHg9FtNg8hE8YUxg@mail.gmail.com \
--to=vivek.gautam@codeaurora.org \
--cc=bhelgaas@google.com \
--cc=catalin.marinas@arm.com \
--cc=cpgs@samsung.com \
--cc=devicetree@vger.kernel.org \
--cc=javier@osg.samsung.com \
--cc=jh80.chung@samsung.com \
--cc=kgene@kernel.org \
--cc=kishon@ti.com \
--cc=krzk@kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-pci@vger.kernel.org \
--cc=linux-samsung-soc@vger.kernel.org \
--cc=mark.rutland@arm.com \
--cc=robh+dt@kernel.org \
--cc=will.deacon@arm.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).