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 <20220829184031.1863663-8-jagan@amarulasolutions.com> <CAHCN7xKxS6oaX8kGYv_bhWfCFUEMBykN87BwXMPkcCg=OwKXrw@mail.gmail.com>
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From:   Jagan Teki <jagan@amarulasolutions.com>
Date:   Wed, 14 Sep 2022 13:52:01 +0530
Message-ID: <CAMty3ZAKjpXpdK1ZNw9dX_ojC4NKCZZ36HaQZGPDfrqiMk0kpQ@mail.gmail.com>
Subject: Re: [PATCH v4 07/12] drm: bridge: samsung-dsim: Fix PLL_P (PMS_P) offset
To:     Adam Ford <aford173@gmail.com>
Cc:     Andrzej Hajda <andrzej.hajda@intel.com>,
        Inki Dae <inki.dae@samsung.com>,
        Marek Szyprowski <m.szyprowski@samsung.com>,
        Joonyoung Shim <jy0922.shim@samsung.com>,
        Seung-Woo Kim <sw0312.kim@samsung.com>,
        Kyungmin Park <kyungmin.park@samsung.com>,
        Frieder Schrempf <frieder.schrempf@kontron.de>,
        Fancy Fang <chen.fang@nxp.com>,
        Tim Harvey <tharvey@gateworks.com>,
        Michael Nazzareno Trimarchi <michael@amarulasolutions.com>,
        Neil Armstrong <narmstrong@baylibre.com>,
        Robert Foss <robert.foss@linaro.org>,
        Laurent Pinchart <Laurent.pinchart@ideasonboard.com>,
        Tommaso Merciai <tommaso.merciai@amarulasolutions.com>,
        Marek Vasut <marex@denx.de>,
        Matteo Lisi <matteo.lisi@engicam.com>,
        dri-devel <dri-devel@lists.freedesktop.org>,
        linux-samsung-soc <linux-samsung-soc@vger.kernel.org>,
        arm-soc <linux-arm-kernel@lists.infradead.org>,
        NXP Linux Team <linux-imx@nxp.com>,
        linux-amarula <linux-amarula@amarulasolutions.com>
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On Tue, Aug 30, 2022 at 1:12 AM Adam Ford <aford173@gmail.com> wrote:
>
> On Mon, Aug 29, 2022 at 1:41 PM Jagan Teki <jagan@amarulasolutions.com> wrote:
> >
> > The i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020
> > with 13.7.10.1 Master PLL PMS Value setting Register mentioned PMS_P offset
> > range from BIT[18-13] and the upstream driver is using the same offset.
> >
> > However, offset 13 is not working on i.MX8M Mini platforms but downstream
> > NXP driver is using 14 [1] and it is working with i.MX8M Mini SoC.
>
> From the line you highlighted in the link, the downstream NXP ones
> shows 13 if I'm reading it correctly.
>
> #define PLLCTRL_SET_P(x) REG_PUT(x, 18, 13)

PMS_P value set in sec_mipi_dsim_check_pll_out using PLLCTRL_SET_P()
with offset 13 and then an additional offset of one bit added in
sec_mipi_dsim_config_pll via PLLCTRL_SET_PMS().

Please check this for additional information
https://github.com/fschrempf/linux/commit/bbb3549a99e162ef6ad4c83d5fd4d39a6daa6d56

I'll update the additional information in commit messages in v5.

Thanks,
Jagan.