From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 062D8C43214 for ; Wed, 4 Aug 2021 18:37:39 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id DDEFB60FC4 for ; Wed, 4 Aug 2021 18:37:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240338AbhHDShv (ORCPT ); Wed, 4 Aug 2021 14:37:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55934 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240324AbhHDShu (ORCPT ); Wed, 4 Aug 2021 14:37:50 -0400 Received: from mail-vs1-xe29.google.com (mail-vs1-xe29.google.com [IPv6:2607:f8b0:4864:20::e29]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9D370C06179A for ; Wed, 4 Aug 2021 11:37:36 -0700 (PDT) Received: by mail-vs1-xe29.google.com with SMTP id j19so1580561vso.0 for ; Wed, 04 Aug 2021 11:37:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=4v3mD/G2snz9EPb0n2yEtj1B1wrpxfXSkVM/rZ+bK44=; b=UiEa1uta1KUv8TDKZIseoNOvN58KiK/nQxRPJnKuD5lTZrBcITzinwOi4xZm8Cf4H7 UiXfhR3HHnQsZdXRk1ePk1j0+K+W3KAgbIxU6qZuLGNoAozeTSlsHGPoM7wZY5MDzNcr nveFZTkbRVI2YLs8FY39dWLY7KkMtLVbsWaz+tBzVbl9V8lH0yCJF0cQPx2vikXmRrG2 nUuq5oRb71+g/PXYHLEFMPSy6yT9mfdb8ACD9+l7s9e9iPFbUwtqj7AiMeAevCmCZCCb JjlI17bXqD6S7+vljkvff8HX3byQ9kVXLeGHgLOhEdUm9VXdFRVnY2TRpbfwZKlBgO1i O3Cw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=4v3mD/G2snz9EPb0n2yEtj1B1wrpxfXSkVM/rZ+bK44=; b=YB3TfGsB5T5QJrkIwwikM1QPe1DgOYAVYJ6uhxQYI8Fg4CEnK81a/t+1w4U4KYG//1 iz2YGz+Cg4I//iYuwMPoBl4dasUylyKCXJV2KT4OjTgiO9lsCUhC3LEfhi2ugkpcU5sM d5K3fqxiBZNDXxkGqvGlI7p6pXYnTP10I4X4uhkn5I6Sn4DJuFCqX4FKH09MW45hnkoR L68vRu/v0cNG4grxHDZJGDuTBWjZ9AEAIRNUIOhLc31qQJwB0pgDsay8rq2H46aYGOf7 Q0PafKlLBMxeMzOFlxi9yaAWWjImshw0sipuTuXwi6esj6ClKGMeVjKkQ+QoWprcqQlT YVYw== X-Gm-Message-State: AOAM5309rePVPojohutdYvzZXV4+qEQO0ZhZSjX2PqZZLBCUeuEBuiuJ 9DRq+w/zeOWQIDgXJ49Se8/KvzFsmcg5bMR/etP3EA== X-Google-Smtp-Source: ABdhPJxf7txyKVStc9ONgBFPDBEr31m+shBvV8OvMRDu9d7Qql+uwVOjtKWRAB+wjysr6bHm+4qOzLKEIRe9Sx5O90o= X-Received: by 2002:a67:f60e:: with SMTP id k14mr1496697vso.30.1628102255703; Wed, 04 Aug 2021 11:37:35 -0700 (PDT) MIME-Version: 1.0 References: <20210730144922.29111-1-semen.protsenko@linaro.org> <20210730144922.29111-13-semen.protsenko@linaro.org> <15871f8ced3c757fad1ab3b6e62c4e64@misterjones.org> <87k0l1w8y5.wl-maz@kernel.org> In-Reply-To: <87k0l1w8y5.wl-maz@kernel.org> From: Sam Protsenko Date: Wed, 4 Aug 2021 21:37:24 +0300 Message-ID: Subject: Re: [PATCH 12/12] arm64: dts: exynos: Add Exynos850 SoC support To: Marc Zyngier Cc: Sylwester Nawrocki , Chanwoo Choi , Krzysztof Kozlowski , Linus Walleij , Tomasz Figa , Rob Herring , Stephen Boyd , Michael Turquette , Jiri Slaby , Greg Kroah-Hartman , Charles Keepax , Ryu Euiyoul , Tom Gall , Sumit Semwal , John Stultz , Amit Pundir , devicetree , linux-arm Mailing List , linux-clk , "open list:GPIO SUBSYSTEM" , Linux Kernel Mailing List , Linux Samsung SOC , "open list:SERIAL DRIVERS" Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org On Wed, 4 Aug 2021 at 18:01, Marc Zyngier wrote: > > On Wed, 04 Aug 2021 15:39:38 +0100, > Sam Protsenko wrote: > > > > You are also missing the hypervisor virtual timer interrupt. > > > > > > > Checked SoC TRM, there is no PPI for hypervisor virtual timer > > interrupt, and no mentioning of it at all. Likewise, I checked ARMv8 > > ARM and TRM, almost no description of it. Also, I checked other > > platforms, and seems like everyone does the same (having only 4 > > interrupts). And I wasn't able to find any documentation on that, so I > > guess I'll leave it as is, if you don't mind. > > I *do* mind, and other DTs being wrong isn't a good enough excuse! ;-) > > From the ARMv8 ARM (ARM DDI 0487G.b) > > D11.2.4 Timers > > In an implementation of the Generic Timer that includes EL3, if EL3 > can use AArch64, the following timers are implemented: > > * An EL1 physical timer, that: > - In Secure state, can be accessed from EL1. > - In Non-secure state, can be accessed from EL1 unless those > accesses are trapped to EL2. > When this timer can be accessed from EL1, an EL1 control > determines whether it can be accessed from EL0. > * A Non-secure EL2 physical timer. > * A Secure EL3 physical timer. An EL3 control determines whether this > register is accessible from Secure EL1. > * An EL1 virtual timer. > * When FEAT_VHE is implemented, a Non-secure EL2 virtual timer. > * When FEAT_SEL2 is implemented, a Secure EL2 physical timer. > * When FEAT_SEL2 is implemented, a Secure EL2 virtual timer. > > > Cortex-A55 being an ARMv8.2 implementation, it has FEAT_VHE, and thus > it does have a NS-EL2 virtual timer. This is further confirmed by the > TRM which documents CNTHV*_EL2 as valid system registers[1]. > > So the timer exists, the signal is routed out of the core, and it > is likely that it is connected to the GIC. > > If the designers have omitted it, then it needs to be documented as > such. > Ok, I've checked thoroughly all docs again, and it seems like there is no dedicated PPI number for this "EL2 Hypervisor Virtual Timer" in Exynos850 SoC. The timer instance itself might exist of course, but interrupt line is probably wasn't connected to GIC by SoC designers, at least it's not documented. Moreover, from [1,2] it looks like if it were existing it would have been PPI=12 (INTID=28). But in GIC-400 TRM this PPI is assigned to "Legacy FIQ signal", and all there is no PPI for Hypervisor Virtual Timer documented there as well. In Exynos850 TRM the source for this PPI's interrupt source is marked as "-", which means it's not used. So if you know something that I don't know -- please point me out the doc where this PPI line is documented. Otherwise I can add the comment to device tree, stating that this interrupt line is not present in SoC's GIC, i.e. something like this: 8<------------------------------------------------------------------------------->8 timer { compatible = "arm,armv8-timer"; interrupts = , , , ; /* Hypervisor Virtual Timer PPI is not present in this SoC GIC */ }; 8<------------------------------------------------------------------------------->8 Is that ok with you? [1] https://developer.arm.com/documentation/102379/0000/The-processor-timers?lang=en [2] https://gem5.googlesource.com/public/gem5/+/refs/heads/master/src/arch/arm/fastmodel/CortexA76/FastModelCortexA76.py#150 > Thanks, > > M. > > [1] https://developer.arm.com/documentation/100442/0100/register-descriptions/aarch64-system-registers/aarch64-architectural-system-register-summary > > -- > Without deviation from the norm, progress is not possible.