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Thu, 19 Dec 2019 10:05:05 +0000 (GMT) Subject: Re: [PATCH v2] clk: samsung: exynos5420: Keep top G3D clocks enabled To: Marek Szyprowski , linux-clk@vger.kernel.org, Stephen Boyd Cc: linux-samsung-soc@vger.kernel.org, Sylwester Nawrocki , Chanwoo Choi , Krzysztof Kozlowski , Bartlomiej Zolnierkiewicz , Marian Mihailescu From: Sylwester Nawrocki Message-ID: Date: Thu, 19 Dec 2019 11:05:04 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.2 MIME-Version: 1.0 In-Reply-To: <20191216131407.17225-1-m.szyprowski@samsung.com> Content-Language: en-GB Content-Transfer-Encoding: 7bit X-Brightmail-Tracker: H4sIAAAAAAAAA02Sa0hTYRjHeXfO2TlbTt9NzQeVgqFlQZpZcKJQg4KBRWFkIQ1bebyUU9m8 ZFGIZtlSEY201QeRQB3ovGXmyNQ0CTMNzBRZVi5l4cDLyCuax2Pkt9/zPv/n8n94GUJRS3kz iclpnC5Zk6QUS8mW90sDByIjVtQHZ8xubEO5mWK/OqcodmCgnmZnC75RbPlAu4it7bbSrPnJ EsWuDTeQ7INfdiJconpttNKqRtNDsaqo2YRU8427zpHR0uOxXFJiBqcLCr0iTcgffUmnduOb 6z+islGdzIAYBvBhmHsmNyApo8DVCKyrI6QQOBEYvrxAQjCPYKjTRhmQZLNitfSNmGcFrkIw 3y8T2IGguyyaZ3d8Fgy51k29B9ZCjr2J4hsROE8EJlPVZkKMg6GwpwjxLMOhMLzYRPNMYn+o LbOIePbEl8A2NEEJGjl8eGojeZZs6O/Nrm0uQWAvyHHWUALvhleO5wQ/DHA7Da3tc1tbn4QS 4xQS2B1+9zbTAvtCX2kBKRTkIiiwjNFCUIxgvLdiq+IYvOv9TPEXI/A+MLcFCcc7Ad8rwwV0 hRGHXNjBFUpaygjhWQb59xVCDz9YMZWJBPaGR7Z1shgpjducGbe5MW5zY/w/tgKRJuTFpeu1 8Zz+UDKXGajXaPXpyfGB11K0jWjjE/Wt9TpbUdvq1S6EGaR0kS2eWlYrKE2GPkvbhYAhlB6y sfwltUIWq8m6xelSYnTpSZy+C/kwpNJLFlJpVytwvCaNu8FxqZzuX1bESLyzUW1+QEzHqDxv j8RylLi+1z5XrzrzMbLzSM30zlKLW0hcJR39uC4gsyjM92LL+MTP0MS34XdcdnjE6eBTj+0u 94d14sv9C2zHeaYaWNdJx+RCX89tzzGt7nSoyeGxvDQ9cUFVbjf5hwxGRbSvWQeLS+NJ37Au 8Uydn1HsA4VKUp+gCd5P6PSav4sLVGZAAwAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrIIsWRmVeSWpSXmKPExsVy+t/xu7qB3r9jDVZ1WFpsnLGe1eL6l+es FufPb2C3+Nhzj9Vixvl9TBZrj9xlt1g/7Serxb9rG1ks2p++ZHbg9Ng56y67x6ZVnWwefVtW MXp83iQXwBKlZ1OUX1qSqpCRX1xiqxRtaGGkZ2hpoWdkYqlnaGwea2VkqqRvZ5OSmpNZllqk b5egl9Fxcyt7wRGBiv8PwxoY1/F2MXJySAiYSPyZvJeti5GLQ0hgKaPErt51zF2MHEAJKYn5 LUoQNcISf651QdW8ZpTY0DCZESQhLOAr8a/jFBNIvYhArsTpSfYgNcwC7UwSBya/ZIJomMgo Mb3rDQtIA5uAoUTv0T6wZl4BO4lrPzazg9gsAqoSa6fvZgKxRQUiJN7+vskKUSMocXLmE7Be TqD6lo//2EBsZgF1iT/zLjFD2OISTV9WskLY8hLb385hnsAoNAtJ+ywkLbOQtMxC0rKAkWUV o0hqaXFuem6xoV5xYm5xaV66XnJ+7iZGYPRtO/Zz8w7GSxuDDzEKcDAq8fD+cP0VK8SaWFZc mXuIUYKDWUmE93bHz1gh3pTEyqrUovz4otKc1OJDjKZAz01klhJNzgcmhrySeENTQ3MLS0Nz Y3NjMwslcd4OgYMxQgLpiSWp2ampBalFMH1MHJxSDYzsRkcFN+WmrG6ac2PFhL1yPSrbnVXu ea9ZUKpo6iNxPOHq3hhf6UDGm3MbFdM3nH4WGbn8cpREx0Svx785nVqsJ+TejYlddnb5tg+Z FvePrecJ5runsqFBJulx5qlWVTfX110pYhJvjqb5dTSKm6sX1XmcflvB9nB7+iw9nnXHNjY3 nerlXqbEUpyRaKjFXFScCABM1Utv1AIAAA== X-CMS-MailID: 20191219100505eucas1p1a5b0dc6c4ef9014dbfaacaf73a4f0ec2 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-RootMTR: 20191216131423eucas1p2162d6bf0a870357be9f0ab308641015b X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20191216131423eucas1p2162d6bf0a870357be9f0ab308641015b References: <20191216131407.17225-1-m.szyprowski@samsung.com> Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org On 12/16/19 14:14, Marek Szyprowski wrote: > In Exynos542x/5800 SoCs, the G3D leaf clocks are located in the G3D power > domain. This is similar to the other hardware modules and their power > domains. However there is one thing specific to G3D clocks hierarchy. > Unlike other hardware modules, the G3D clocks hierarchy doesn't have any > gate clock between the TOP part of the hierarchy and the part located in > the power domain and some SoC internal busses are sourced directly from > the TOP muxes. The consequence of this design if the fact that the TOP > part of the hierarchy has to be enabled permanently to ensure proper > operation of the SoC power related components (G3D power domain and > Exynos Power Management Unit for system suspend/resume). > > This patch adds an explicit call to clk_prepare_enable() on the last MUX > in the TOP part of G3D clock hierarchy to keep it enabled permanently to > ensure that the internal busses get their clock regardless of the main > G3D clock enablement status. > --- > diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c > index 3a991ca1ee36..c9e5a1fb6653 100644 > --- a/drivers/clk/samsung/clk-exynos5420.c > +++ b/drivers/clk/samsung/clk-exynos5420.c > @@ -1646,6 +1647,13 @@ static void __init exynos5x_clk_init(struct device_node *np, > exynos5x_subcmus); > } > > + /* > + * Keep top part of G3D clock path enabled permanently to ensure > + * that the internal busses get their clock regardless of the > + * main G3D clock enablement status. > + */ > + clk_prepare_enable(__clk_lookup("mout_sw_aclk_g3d")); > + > samsung_clk_of_add_provider(np, ctx); > } It's a bit unfortunate we don't store that clock in the driver internally, which would let us avoid the __clk_lookup() call. I can't come up with any simple alternative though so let's apply it for now. Acked-by: Sylwester Nawrocki I don't have any other bug fix patches for clk/samsung, could you take it directly into your tree Stephen? -- Thanks, Sylwester