From: Alim Akhtar <alim.akhtar@samsung.com>
To: linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-scsi@vger.kernel.org,
linux-phy@lists.infradead.org
Cc: devicetree@vger.kernel.org, robh+dt@kernel.org,
krzysztof.kozlowski+dt@linaro.org, vkoul@kernel.org,
avri.altman@wdc.com, bvanassche@acm.org,
martin.petersen@oracle.com, chanho61.park@samsung.com,
pankaj.dubey@samsung.com, Alim Akhtar <alim.akhtar@samsung.com>,
Bharat Uppal <bharat.uppal@samsung.com>
Subject: [PATCH v4 2/6] phy: samsung-ufs: move cdr offset to drvdata
Date: Fri, 10 Jun 2022 16:11:15 +0530 [thread overview]
Message-ID: <20220610104119.66401-3-alim.akhtar@samsung.com> (raw)
In-Reply-To: <20220610104119.66401-1-alim.akhtar@samsung.com>
Move CDR lock offset to drv data so that it can be extended for other SoCs
which are having CDR lock at different register offset.
Signed-off-by: Bharat Uppal <bharat.uppal@samsung.com>
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Reviewed-by: Chanho Park <chanho61.park@samsung.com>
---
drivers/phy/samsung/phy-exynos7-ufs.c | 3 +++
drivers/phy/samsung/phy-exynosautov9-ufs.c | 2 ++
drivers/phy/samsung/phy-samsung-ufs.c | 4 +++-
drivers/phy/samsung/phy-samsung-ufs.h | 2 +-
4 files changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/phy/samsung/phy-exynos7-ufs.c b/drivers/phy/samsung/phy-exynos7-ufs.c
index d1e9d0ae5c1d..72854336f59d 100644
--- a/drivers/phy/samsung/phy-exynos7-ufs.c
+++ b/drivers/phy/samsung/phy-exynos7-ufs.c
@@ -11,6 +11,8 @@
#define EXYNOS7_EMBEDDED_COMBO_PHY_CTRL_MASK 0x1
#define EXYNOS7_EMBEDDED_COMBO_PHY_CTRL_EN BIT(0)
+#define EXYNOS7_EMBEDDED_COMBO_PHY_CDR_LOCK_STATUS 0x5e
+
/* Calibration for phy initialization */
static const struct samsung_ufs_phy_cfg exynos7_pre_init_cfg[] = {
PHY_COMN_REG_CFG(0x00f, 0xfa, PWR_MODE_ANY),
@@ -74,4 +76,5 @@ const struct samsung_ufs_phy_drvdata exynos7_ufs_phy = {
.en = EXYNOS7_EMBEDDED_COMBO_PHY_CTRL_EN,
},
.has_symbol_clk = 1,
+ .cdr_lock_status_offset = EXYNOS7_EMBEDDED_COMBO_PHY_CDR_LOCK_STATUS,
};
diff --git a/drivers/phy/samsung/phy-exynosautov9-ufs.c b/drivers/phy/samsung/phy-exynosautov9-ufs.c
index fa4d2983eec6..2b256070d657 100644
--- a/drivers/phy/samsung/phy-exynosautov9-ufs.c
+++ b/drivers/phy/samsung/phy-exynosautov9-ufs.c
@@ -10,6 +10,7 @@
#define EXYNOSAUTOV9_EMBEDDED_COMBO_PHY_CTRL 0x728
#define EXYNOSAUTOV9_EMBEDDED_COMBO_PHY_CTRL_MASK 0x1
#define EXYNOSAUTOV9_EMBEDDED_COMBO_PHY_CTRL_EN BIT(0)
+#define EXYNOSAUTOV9_EMBEDDED_COMBO_PHY_CDR_LOCK_STATUS 0x5e
#define PHY_TRSV_REG_CFG_AUTOV9(o, v, d) \
PHY_TRSV_REG_CFG_OFFSET(o, v, d, 0x50)
@@ -64,4 +65,5 @@ const struct samsung_ufs_phy_drvdata exynosautov9_ufs_phy = {
.en = EXYNOSAUTOV9_EMBEDDED_COMBO_PHY_CTRL_EN,
},
.has_symbol_clk = 0,
+ .cdr_lock_status_offset = EXYNOSAUTOV9_EMBEDDED_COMBO_PHY_CDR_LOCK_STATUS,
};
diff --git a/drivers/phy/samsung/phy-samsung-ufs.c b/drivers/phy/samsung/phy-samsung-ufs.c
index 206a79c69a6c..8cec7652b459 100644
--- a/drivers/phy/samsung/phy-samsung-ufs.c
+++ b/drivers/phy/samsung/phy-samsung-ufs.c
@@ -63,7 +63,8 @@ static int samsung_ufs_phy_wait_for_lock_acq(struct phy *phy)
}
err = readl_poll_timeout(
- ufs_phy->reg_pma + PHY_APB_ADDR(PHY_CDR_LOCK_STATUS),
+ ufs_phy->reg_pma +
+ PHY_APB_ADDR(ufs_phy->drvdata->cdr_lock_status_offset),
val, (val & PHY_CDR_LOCK_BIT), sleep_us, timeout_us);
if (err)
dev_err(ufs_phy->dev,
@@ -327,6 +328,7 @@ static int samsung_ufs_phy_probe(struct platform_device *pdev)
drvdata = match->data;
phy->dev = dev;
+ phy->drvdata = drvdata;
phy->cfgs = drvdata->cfgs;
phy->has_symbol_clk = drvdata->has_symbol_clk;
memcpy(&phy->isol, &drvdata->isol, sizeof(phy->isol));
diff --git a/drivers/phy/samsung/phy-samsung-ufs.h b/drivers/phy/samsung/phy-samsung-ufs.h
index 854b53bdf347..913542ebff7a 100644
--- a/drivers/phy/samsung/phy-samsung-ufs.h
+++ b/drivers/phy/samsung/phy-samsung-ufs.h
@@ -40,7 +40,6 @@
/* UFS PHY registers */
#define PHY_PLL_LOCK_STATUS 0x1e
-#define PHY_CDR_LOCK_STATUS 0x5e
#define PHY_PLL_LOCK_BIT BIT(5)
#define PHY_CDR_LOCK_BIT BIT(4)
@@ -111,6 +110,7 @@ struct samsung_ufs_phy_drvdata {
const struct samsung_ufs_phy_cfg **cfgs;
struct samsung_ufs_phy_pmu_isol isol;
bool has_symbol_clk;
+ u32 cdr_lock_status_offset;
};
struct samsung_ufs_phy {
--
2.25.1
next prev parent reply other threads:[~2022-06-10 10:48 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <CGME20220610104340epcas5p1d6cee31aba4dc2952ef09003c9e67863@epcas5p1.samsung.com>
2022-06-10 10:41 ` [PATCH v4 0/6] Add support for UFS controller found in FSD SoC Alim Akhtar
[not found] ` <CGME20220610104343epcas5p3f9f61a6c66cf52c203b29c2af376dfc3@epcas5p3.samsung.com>
2022-06-10 10:41 ` [PATCH v4 1/6] dt-bindings: phy: Add FSD UFS PHY bindings Alim Akhtar
[not found] ` <CGME20220610104346epcas5p4f59c073d15b3cd8fbc99de03d9cd1c41@epcas5p4.samsung.com>
2022-06-10 10:41 ` Alim Akhtar [this message]
2022-06-13 7:04 ` [PATCH v4 2/6] phy: samsung-ufs: move cdr offset to drvdata Chanho Park
2022-06-13 9:46 ` Krzysztof Kozlowski
[not found] ` <CGME20220610104350epcas5p2a42643432e60d7ba18f2a2afcffadfaf@epcas5p2.samsung.com>
2022-06-10 10:41 ` [PATCH v4 3/6] phy: samsung-ufs: add support for FSD ufs phy driver Alim Akhtar
2022-06-13 9:47 ` Krzysztof Kozlowski
[not found] ` <CGME20220610104353epcas5p19324d8bb48a250d4788ce24f859a3ec3@epcas5p1.samsung.com>
2022-06-10 10:41 ` [PATCH v4 4/6] dt-bindings: ufs: exynos-ufs: add fsd compatible Alim Akhtar
[not found] ` <CGME20220610104356epcas5p4343acd45f6677723a1b44534fcc4e289@epcas5p4.samsung.com>
2022-06-10 10:41 ` [PATCH v4 5/6] ufs: host: ufs-exynos: add mphy apb clock mask Alim Akhtar
2022-06-13 9:47 ` Krzysztof Kozlowski
[not found] ` <CGME20220610104359epcas5p17a61f0254148bc1bdb15d91ff6b3f12c@epcas5p1.samsung.com>
2022-06-10 10:41 ` [PATCH v4 6/6] ufs: host: ufs-exynos: add support for fsd ufs hci Alim Akhtar
2022-06-13 6:54 ` Chanho Park
2022-06-14 16:13 ` [PATCH v4 0/6] Add support for UFS controller found in FSD SoC Alim Akhtar
2022-06-17 0:18 ` Vinod Koul
2022-06-17 2:21 ` Martin K. Petersen
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