From: Michael Schmitz <firstname.lastname@example.org> To: Kars de Jong <email@example.com> Cc: James Bottomley <firstname.lastname@example.org>, "Martin K. Petersen" <email@example.com>, firstname.lastname@example.org, email@example.com Subject: Re: [PATCH] zorro_esp: increase maximum dma length to 65536 bytes Date: Mon, 11 Nov 2019 08:26:32 +1300 Message-ID: <firstname.lastname@example.org> (raw) In-Reply-To: <CACz-3rjUh8tcShX5OPi+37JvF8PqG-8AEf5uMQHjMynSaVa1gw@mail.gmail.com> Hi Kars, thanks for your patch! On 10/11/19 10:01 PM, Kars de Jong wrote: > Hi Michael, > > Op zo 10 nov. 2019 om 03:36 schreef Michael Schmitz <email@example.com>: >> All of the old board-specific drivers used a max transfer length of >> 0x1000000, only the fastlane driver used 0xfffc. > Yes, I also found this when checking the old drivers. > >> That lower limit might >> be due to a DMA limitation on the fastlane board. We could accommodate >> the different limit for this board by using a board-specific >> dma_length_limit() callback... > Yes, I think that's the best idea for now. Oktagon also used to have a > different limit but that was never ported to the new ESP core. I can't remember the details, but as far as I recall it, the Oktagon used pseudo-DMA rather than hardware DMA. At the time I started porting Zorro ESP drivers to the new core, pseudo-DMA code was available for Mac only, and no PIO transfer for data phases at all, so I decided to leave that out altogether. Might be a lot easier now that Finn has moved the PIO support code into the core driver. Someone could start with a PIO mode driver and add PDMA later. >>> case for any of the cards the zorro_esp drives, it might be better to >>> lower the max length to 61440 (64k-4k) so the residual is a page. >> For the benefit of keeping the code simple, and avoid retesting the >> fastlane board, that might indeed be the better solution. > But it's slower... :-P I wonder what max. transfer size had been used so far, in the majority of cases. I hadn't observed this bug in my tests of the ESP driver on elgar. So it might not matter so much in practice. > Also, I may be adding another board-specific version for the Blizzard > 12x0 IV to enable 24-bit transfers, like the am53c974 driver does, in > a later patch. If we can differentiate between the Mark IV board and the Mark II board in a reliable way, fine. I can't remember whether I've had a report on that ever. I'd suggest to change the transfer size limit to 60k in the first instance, and add board-specific tweaks as needed when you add 24 bit DMA support for the Mark IV. Cheers, Michael > > Kind regards, > > Kars.
next prev parent reply index Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top [not found] <CACz-3rh9ZCyU1825yU8xxty5BGrwFhpbjKNoWnn0mGiv_h2Kag@mail.gmail.com> 2019-11-09 19:14 ` Kars de Jong 2019-11-09 20:12 ` James Bottomley 2019-11-10 2:36 ` Michael Schmitz 2019-11-10 9:01 ` Kars de Jong 2019-11-10 19:26 ` Michael Schmitz [this message] 2019-11-11 8:47 ` Kars de Jong 2019-11-10 19:35 ` James Bottomley 2019-11-12 17:55 ` [PATCH v2] zorro_esp: Limit DMA transfers to 65536 bytes (except on Fastlane) Kars de Jong 2019-11-12 22:46 ` Finn Thain 2019-11-13 2:27 ` Martin K. Petersen 2019-11-12 9:34 ` [PATCH] zorro_esp: increase maximum dma length to 65536 bytes Kars de Jong 2019-11-09 22:53 ` Finn Thain 2019-11-10 9:06 ` Kars de Jong
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