Re: Enabling interrupts in QEMU TPM TIS

From: Stefan Berger <stefanb@linux.ibm.com>
To: Jason Gunthorpe <jgg@ziepe.ca>
Cc: Jerry Snitselaar <jsnitsel@redhat.com>,
	linux-integrity <linux-integrity@vger.kernel.org>,
	Jarkko Sakkinen <jarkko.sakkinen@linux.intel.com>,
	LSM List <linux-security-module@vger.kernel.org>,
	LKML <linux-kernel@vger.kernel.org>
Subject: Re: Enabling interrupts in QEMU TPM TIS
Date: Thu, 25 Jun 2020 17:26:32 -0400	[thread overview]
Message-ID: <0a524093-e744-e266-6087-ddc17b5c598c@linux.ibm.com> (raw)
In-Reply-To: <20200625172802.GS6578@ziepe.ca>

On 6/25/20 1:28 PM, Jason Gunthorpe wrote:
> On Thu, Jun 25, 2020 at 10:56:43AM -0400, Stefan Berger wrote:
>> Hello!
>>
>>   I want to enable IRQs now in QEMU's TPM TIS device model and I need to work
>> with the following patch to Linux TIS. I am wondering whether the changes
>> there look reasonable to you? Windows works with the QEMU modifications
>> as-is, so maybe it's a bug in the TIS code (which I had not run into
>> before).
>>
>>
>> The point of the loop I need to introduce in the interrupt handler is that
>> while the interrupt handler is running another interrupt may occur/be posted
>> that then does NOT cause the interrupt handler to be invoked again but
>> causes a stall, unless the loop is there.
> That seems like a qemu bug, TPM interrupts are supposed to be level
> interrupts, not edge.

Following this document here the hardware may choose to support 
different types of interrutps:

https://trustedcomputinggroup.org/wp-content/uploads/PC-Client-Specific-Platform-TPM-Profile-for-TPM-2p0-v1p04_r0p37_pub-1.pdf

Table 23. Edge falling or rising, level low or level high.

So with different steps in the driver causing different types of 
interrupts, we may get into such situations where we process some 
interrupt 'reasons' but then another one gets posted, I guess due to 
parallel processing.

   Stefan