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From: "Hyunki Koo" <hyunki00.koo@samsung.com>
To: "'Bartlomiej Zolnierkiewicz'" <b.zolnierkie@samsung.com>
Cc: "'Kukjin Kim'" <kgene@kernel.org>,
	"'Krzysztof Kozlowski'" <krzk@kernel.org>,
	"'Greg Kroah-Hartman'" <gregkh@linuxfoundation.org>,
	"'Jiri Slaby'" <jslaby@suse.com>,
	<linux-arm-kernel@lists.infradead.org>,
	<linux-samsung-soc@vger.kernel.org>,
	<linux-serial@vger.kernel.org>, <linux-kernel@vger.kernel.org>
Subject: RE: [PATCH v10 3/3] tty: samsung_tty: 32-bit access for TX/RX hold registers
Date: Thu, 7 May 2020 08:05:20 +0900	[thread overview]
Message-ID: <010b01d623fa$d0f26130$72d72390$@samsung.com> (raw)
In-Reply-To: <1b230724-c87b-aa28-f850-ecdeb0542dba@samsung.com>

On 5/6/20 8:03 PM, Bartlomiej Zolnierkiewicz wrote:
> On 5/6/20 10:02 AM, Hyunki Koo wrote:
> > Support 32-bit access for the TX/RX hold registers UTXH and URXH.
> >
> > This is required for some newer SoCs.
> 
> Krzysztof has asked this previously but I couldn't find the answer in
> previous mails:
> 
> Do you plan to upstream support for these newer SoCs?
> 
> If not (i.e. this code is only to support Android GKI) then the code you are
> adding now may be removed at any time later during cleanups (due to
> lack of the in-kernel users).
> 
> Best regards,
> --
> Bartlomiej Zolnierkiewicz
> Samsung R&D Institute Poland
> Samsung Electronics
> 
> > Signed-off-by: Hyunki Koo <hyunki00.koo@samsung.com>
> > Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Tested on Odroid
> > HC1 (Exynos5422):
> > Tested-by: Krzysztof Kozlowski <krzk@kernel.org>
> > ---
> >  drivers/tty/serial/samsung_tty.c | 62
> > ++++++++++++++++++++++++++++++++++++----
> >  1 file changed, 57 insertions(+), 5 deletions(-)
> >
> > diff --git a/drivers/tty/serial/samsung_tty.c
> > b/drivers/tty/serial/samsung_tty.c
> > index 326b0164609c..6ef614d8648c 100644
> > --- a/drivers/tty/serial/samsung_tty.c
> > +++ b/drivers/tty/serial/samsung_tty.c
> > @@ -154,10 +154,33 @@ struct s3c24xx_uart_port {  #define
> > portaddrl(port, reg) \
> >  	((unsigned long *)(unsigned long)((port)->membase + (reg)))
> >
> > -#define rd_reg(port, reg) (readb_relaxed(portaddr(port, reg)))
> > +static u32 rd_reg(struct uart_port *port, u32 reg) {
> > +	switch (port->iotype) {
> > +	case UPIO_MEM:
> > +		return readb_relaxed(portaddr(port, reg));
> > +	case UPIO_MEM32:
> > +		return readl_relaxed(portaddr(port, reg));
> > +	default:
> > +		return 0;
> > +	}
> > +	return 0;
> > +}
> > +
> >  #define rd_regl(port, reg) (readl_relaxed(portaddr(port, reg)))
> >
> > -#define wr_reg(port, reg, val) writeb_relaxed(val, portaddr(port,
> > reg))
> > +static void wr_reg(struct uart_port *port, u32 reg, u32 val) {
> > +	switch (port->iotype) {
> > +	case UPIO_MEM:
> > +		writeb_relaxed(val, portaddr(port, reg));
> > +		break;
> > +	case UPIO_MEM32:
> > +		writel_relaxed(val, portaddr(port, reg));
> > +		break;
> > +	}
> > +}
> > +
> >  #define wr_regl(port, reg, val) writel_relaxed(val, portaddr(port,
> > reg))
> >
> >  /* Byte-order aware bit setting/clearing functions. */ @@ -1974,7
> > +1997,7 @@ static int s3c24xx_serial_probe(struct platform_device
> *pdev)
> >  	struct device_node *np = pdev->dev.of_node;
> >  	struct s3c24xx_uart_port *ourport;
> >  	int index = probe_index;
> > -	int ret;
> > +	int ret, prop = 0;
> >
> >  	if (np) {
> >  		ret = of_alias_get_id(np, "serial"); @@ -2000,10
> +2023,27 @@ static
> > int s3c24xx_serial_probe(struct platform_device *pdev)
> >  			dev_get_platdata(&pdev->dev) :
> >  			ourport->drv_data->def_cfg;
> >
> > -	if (np)
> > +	if (np) {
> >  		of_property_read_u32(np,
> >  			"samsung,uart-fifosize", &ourport->port.fifosize);
> >
> > +		if (of_property_read_u32(np, "reg-io-width", &prop) ==
> 0) {
> > +			switch (prop) {
> > +			case 1:
> > +				ourport->port.iotype = UPIO_MEM;
> > +				break;
> > +			case 4:
> > +				ourport->port.iotype = UPIO_MEM32;
> > +				break;
> > +			default:
> > +				dev_warn(&pdev->dev, "unsupported
> reg-io-width (%d)\n",
> > +						prop);
> > +				ret = -EINVAL;
> > +				break;
> > +			}
> > +		}
> > +	}
> > +
> >  	if (ourport->drv_data->fifosize[index])
> >  		ourport->port.fifosize = ourport->drv_data-
> >fifosize[index];
> >  	else if (ourport->info->fifosize)
> > @@ -2587,6 +2627,18 @@
> module_platform_driver(samsung_serial_driver);
> >   * Early console.
> >   */
> >
> > +static void wr_reg_barrier(struct uart_port *port, u32 reg, u32 val)
> > +{
> > +	switch (port->iotype) {
> > +	case UPIO_MEM:
> > +		writeb(val, portaddr(port, reg));
> > +		break;
> > +	case UPIO_MEM32:
> > +		writel(val, portaddr(port, reg));
> > +		break;
> > +	}
> > +}
> > +
> >  struct samsung_early_console_data {
> >  	u32 txfull_mask;
> >  };
> > @@ -2612,7 +2664,7 @@ static void samsung_early_putc(struct
> uart_port *port, int c)
> >  	else
> >  		samsung_early_busyuart(port);
> >
> > -	writeb(c, port->membase + S3C2410_UTXH);
> > +	wr_reg_barrier(port, S3C2410_UTXH, c);
> >  }
> >
> >  static void samsung_early_write(struct console *con, const char *s,
> >
Hi
We don't have plan to upstream for new SOCs yet,
This code is only to support Android GKI, 
But it should not be not removed 


  reply	other threads:[~2020-05-06 23:05 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
     [not found] <CGME20200506080249epcas2p47ffb915f9c469d208224cbdecb2d723d@epcas2p4.samsung.com>
2020-05-06  8:02 ` [PATCH v10 1/3] serial: samsung: Replace rd_regb/wr_regb with rd_reg/wr_reg Hyunki Koo
     [not found]   ` <CGME20200506080255epcas2p2bbaae2e0f3fa181bafa5012f069200be@epcas2p2.samsung.com>
2020-05-06  8:02     ` [PATCH v10 2/3] dt-bindings: serial: Add reg-io-width compatible Hyunki Koo
     [not found]   ` <CGME20200506080258epcas2p4f242fb66a2145f76b0e108014ee351fb@epcas2p4.samsung.com>
2020-05-06  8:02     ` [PATCH v10 3/3] tty: samsung_tty: 32-bit access for TX/RX hold registers Hyunki Koo
2020-05-06 11:02       ` Bartlomiej Zolnierkiewicz
2020-05-06 23:05         ` Hyunki Koo [this message]
2020-05-19  5:55       ` Jiri Slaby

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