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([2a02:810d:15c0:828:9827:5f65:8269:a95f]) by smtp.gmail.com with ESMTPSA id y21-20020a1709064b1500b00905a1abecbfsm3476379eju.47.2023.03.16.00.35.49 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 16 Mar 2023 00:35:50 -0700 (PDT) Message-ID: <0ad8521d-90b9-29c7-62e6-2d65aa2a7a27@linaro.org> Date: Thu, 16 Mar 2023 08:35:49 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.8.0 Subject: Re: [PATCH 08/15] dt-bindings: clock: Document ma35d1 clock controller bindings Content-Language: en-US To: Jacky Huang , robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, lee@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, p.zabel@pengutronix.de, gregkh@linuxfoundation.org, jirislaby@kernel.org Cc: devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org, schung@nuvoton.com, Jacky Huang References: <20230315072902.9298-1-ychuang570808@gmail.com> <20230315072902.9298-9-ychuang570808@gmail.com> From: Krzysztof Kozlowski In-Reply-To: <20230315072902.9298-9-ychuang570808@gmail.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org On 15/03/2023 08:28, Jacky Huang wrote: > From: Jacky Huang > > Add documentation to describe nuvoton ma35d1 clock driver bindings. Subject: drop second/last, redundant "bindings". The "dt-bindings" prefix is already stating that these are bindings. > > Signed-off-by: Jacky Huang > --- > .../bindings/clock/nuvoton,ma35d1-clk.yaml | 83 +++++++++++++++++++ > 1 file changed, 83 insertions(+) > create mode 100644 Documentation/devicetree/bindings/clock/nuvoton,ma35d1-clk.yaml > > diff --git a/Documentation/devicetree/bindings/clock/nuvoton,ma35d1-clk.yaml b/Documentation/devicetree/bindings/clock/nuvoton,ma35d1-clk.yaml > new file mode 100644 > index 000000000000..5c2dea071b38 > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/nuvoton,ma35d1-clk.yaml > @@ -0,0 +1,83 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/clock/nuvoton,ma35d1-clk.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Nuvoton MA35D1 Clock Controller Module Binding > + > +maintainers: > + - Chi-Fang Li > + - Jacky Huang > + > +description: | > + The MA35D1 clock controller generates clocks for the whole chip, > + including system clocks and all peripheral clocks. > + > + See also: > + include/dt-bindings/clock/ma35d1-clk.h > + > +properties: > + compatible: > + items: > + - const: nuvoton,ma35d1-clk > + - const: syscon > + > + reg: > + maxItems: 1 > + > + "#clock-cells": > + const: 1 > + > + clocks: > + maxItems: 1 > + > + clock-names: > + const: clk_hxt Drop clock-names. You do not need it for one clock. > + > + assigned-clocks: > + maxItems: 5 > + > + assigned-clock-rates: > + maxItems: 5 Drop both properties, you do not need them in the binding. > + > + nuvoton,pll-mode: > + description: > + A list of PLL operation mode corresponding to CAPLL, DDRPLL, APLL, > + EPLL, and VPLL in sequential. The operation mode value 0 is for > + integer mode, 1 is for fractional mode, and 2 is for spread > + spectrum mode. > + $ref: /schemas/types.yaml#/definitions/uint32-array > + maxItems: 5 > + items: > + minimum: 0 > + maximum: 2 Why exactly this is suitable for DT? > + > + nuvoton,sys: > + description: > + Phandle to the system management controller. > + $ref: "/schemas/types.yaml#/definitions/phandle-array" Drop quotes. You need here constraints, look for existing examples. Best regards, Krzysztof