From: Akash Asthana <akashast@codeaurora.org>
To: gregkh@linuxfoundation.org, agross@kernel.org,
bjorn.andersson@linaro.org, wsa@the-dreams.de,
broonie@kernel.org, mark.rutland@arm.com, robh+dt@kernel.org
Cc: linux-i2c@vger.kernel.org, linux-spi@vger.kernel.org,
devicetree@vger.kernel.org, swboyd@chromium.org,
mgautam@codeaurora.org, linux-arm-msm@vger.kernel.org,
linux-serial@vger.kernel.org, mka@chromium.org,
dianders@chromium.org, msavaliy@codeaurora.org,
evgreen@chromium.org, Akash Asthana <akashast@codeaurora.org>
Subject: [PATCH V6 4/7] spi: spi-geni-qcom: Add interconnect support
Date: Thu, 21 May 2020 13:59:21 +0530 [thread overview]
Message-ID: <1590049764-20912-5-git-send-email-akashast@codeaurora.org> (raw)
In-Reply-To: <1590049764-20912-1-git-send-email-akashast@codeaurora.org>
Get the interconnect paths for SPI based Serial Engine device
and vote according to the current bus speed of the driver.
Signed-off-by: Akash Asthana <akashast@codeaurora.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Acked-by: Mark Brown <broonie@kernel.org>
---
Changes in V2:
- As per Bjorn's comment, removed se == NULL check from geni_spi_icc_get
- As per Bjorn's comment, removed code to set se->icc_path* to NULL in failure
- As per Bjorn's comment, introduced and using devm_of_icc_get API for getting
path handle
- As per Matthias comment, added error handling for icc_set_bw call
Changes in V3:
- As per Matthias's comment, use helper ICC function from geni-se driver.
Changes in V4:
- Move peak_bw guess as twice of avg_bw if nothing mentioned explicitly
to ICC core.
Changes in V5:
- Use icc_enable/disable in power on/off call.
- Save some non-zero avg/peak value to ICC core by calling geni_icc_set_bw
from probe so that when resume/icc_enable is called NOC are running at
some non-zero value. No need to call icc_disable after BW vote because
device will resume and suspend before probe return and will leave ICC in
disabled state.
Changes in V6:
- No change
drivers/spi/spi-geni-qcom.c | 31 ++++++++++++++++++++++++++++++-
1 file changed, 30 insertions(+), 1 deletion(-)
diff --git a/drivers/spi/spi-geni-qcom.c b/drivers/spi/spi-geni-qcom.c
index c397242..cc637d2 100644
--- a/drivers/spi/spi-geni-qcom.c
+++ b/drivers/spi/spi-geni-qcom.c
@@ -234,6 +234,13 @@ static int setup_fifo_params(struct spi_device *spi_slv,
return ret;
}
+ /* Set BW quota for CPU as driver supports FIFO mode only. */
+ geni_icc_bw_init(&se->icc_paths[CPU_TO_GENI],
+ Bps_to_icc(mas->cur_speed_hz), 0);
+ ret = geni_icc_set_bw(se);
+ if (ret)
+ return ret;
+
clk_sel = idx & CLK_SEL_MSK;
m_clk_cfg = (div << CLK_DIV_SHFT) | SER_CLK_EN;
spi_setup_word_len(mas, spi_slv->mode, spi_slv->bits_per_word);
@@ -578,6 +585,18 @@ static int spi_geni_probe(struct platform_device *pdev)
spin_lock_init(&mas->lock);
pm_runtime_enable(dev);
+ ret = geni_icc_get(&mas->se, NULL);
+ if (ret)
+ goto spi_geni_probe_runtime_disable;
+ /* Set the bus quota to a reasonable value for register access */
+ geni_icc_bw_init(&mas->se.icc_paths[GENI_TO_CORE],
+ Bps_to_icc(CORE_2X_50_MHZ), 0);
+ geni_icc_bw_init(&mas->se.icc_paths[CPU_TO_GENI], GENI_DEFAULT_BW, 0);
+
+ ret = geni_icc_set_bw(&mas->se);
+ if (ret)
+ goto spi_geni_probe_runtime_disable;
+
ret = spi_geni_init(mas);
if (ret)
goto spi_geni_probe_runtime_disable;
@@ -616,14 +635,24 @@ static int __maybe_unused spi_geni_runtime_suspend(struct device *dev)
{
struct spi_master *spi = dev_get_drvdata(dev);
struct spi_geni_master *mas = spi_master_get_devdata(spi);
+ int ret;
+
+ ret = geni_se_resources_off(&mas->se);
+ if (ret)
+ return ret;
- return geni_se_resources_off(&mas->se);
+ return geni_icc_disable(&mas->se);
}
static int __maybe_unused spi_geni_runtime_resume(struct device *dev)
{
struct spi_master *spi = dev_get_drvdata(dev);
struct spi_geni_master *mas = spi_master_get_devdata(spi);
+ int ret;
+
+ ret = geni_icc_enable(&mas->se);
+ if (ret)
+ return ret;
return geni_se_resources_on(&mas->se);
}
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,\na Linux Foundation Collaborative Project
next prev parent reply other threads:[~2020-05-21 8:30 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-21 8:29 [PATCH V6 0/7] [PATCH V5 0/7] Add interconnect support to QSPI and QUP drivers Akash Asthana
2020-05-21 8:29 ` [PATCH V6 1/7] soc: qcom: geni: Support for ICC voting Akash Asthana
2020-05-21 15:50 ` Matthias Kaehlcke
2020-05-26 12:41 ` Akash Asthana
2020-05-21 8:29 ` [PATCH V6 2/7] soc: qcom-geni-se: Add interconnect support to fix earlycon crash Akash Asthana
2020-05-21 16:00 ` Matthias Kaehlcke
2020-05-21 18:12 ` Matthias Kaehlcke
2020-05-22 18:31 ` kbuild test robot
2020-05-21 8:29 ` [PATCH V6 3/7] i2c: i2c-qcom-geni: Add interconnect support Akash Asthana
2020-05-21 8:29 ` Akash Asthana [this message]
2020-05-21 8:29 ` [PATCH V6 5/7] tty: serial: qcom_geni_serial: " Akash Asthana
2020-05-21 8:39 ` Greg KH
2020-05-21 8:29 ` [PATCH V6 6/7] spi: spi-qcom-qspi: " Akash Asthana
2020-05-23 1:11 ` kbuild test robot
2020-05-21 8:29 ` [PATCH V6 7/7] arm64: dts: sc7180: Add interconnect for QUP and QSPI Akash Asthana
2020-05-23 14:05 ` kbuild test robot
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